CN105679764B - The production method of TFT substrate - Google Patents
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- CN105679764B CN105679764B CN201610011881.6A CN201610011881A CN105679764B CN 105679764 B CN105679764 B CN 105679764B CN 201610011881 A CN201610011881 A CN 201610011881A CN 105679764 B CN105679764 B CN 105679764B
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Abstract
The present invention provides a kind of production method of TFT substrate, by forming antistatic convex block in the side of controlling grid scan line, the second via hole above the corresponding antistatic convex block is formed on interlayer insulating film later, to after sedimentary origin drain metal layer, the source-drain electrode metal layer is in contact by the second via hole with the antistatic convex block of the controlling grid scan line side, due to controlling grid scan line connection first, second grid, to the source-drain electrode metal layer and described first, second grid is connected, the source-drain electrode metal layer is also connected with polysilicon layer simultaneously, so that polysilicon layer and first, voltage between second grid is zero, can not only ensure that static discharge phenomenon will not occur in the film forming procedure of source-drain electrode metal layer, and it can be effectively reduced the static discharge before the lithographic process of source-drain electrode metal layer is completed The incidence of phenomenon.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of production methods of TFT substrate.
Background technique
With the development of display technology, the planes such as liquid crystal display (Liquid Crystal Display, LCD) display dress
It sets because having many advantages, such as that high image quality, power saving, fuselage is thin and has a wide range of application, and is widely used in mobile phone, TV, a number
The various consumer electrical products such as word assistant, digital camera, laptop, desktop computer, become the master in display device
Stream.
Liquid crystal display device on existing market is largely backlight liquid crystal display comprising liquid crystal display panel and
Backlight module (backlight module).The working principle of liquid crystal display panel is put in the parallel glass substrate of two panels
Liquid crystal molecule is set, there are many tiny electric wires vertically and horizontally for two panels glass substrate centre, control liquid crystal whether by being powered
The light refraction of backlight module is come out and generates picture by molecular changes direction.
Usual liquid crystal display panel is by color film (CF, Color Filter) substrate, thin film transistor (TFT) (TFT, Thin Film
Transistor) substrate, the liquid crystal (LC, Liquid Crystal) that is sandwiched between color membrane substrates and thin film transistor base plate and close
Sealing frame (Sealant) composition, moulding process generally comprise: leading portion array (Array) processing procedure (film, yellow light, etching and stripping
Film), middle section is at box (Cell) processing procedure (TFT substrate is bonded with CF substrate) and back segment module group assembling processing procedure (driving IC and printing electricity
Road plate pressing).Wherein, leading portion Array processing procedure mainly forms TFT substrate, in order to control the movement of liquid crystal molecule；Middle section
Cell processing procedure mainly adds liquid crystal between TFT substrate and CF substrate；Back segment module group assembling processing procedure mainly drives IC pressing
With the integration of printed circuit board, and then drive liquid crystal molecule rotation, show image.
With the fast development of smart phone, mobile display is that LTPS is (low via a-Si (amorphous silicon) TFT-LCD transition
Warm polysilicon) TFT-LCD.Due to the advantage that LTPS technology has electron mobility high, it is highly suitable for production high-resolution
Display device.But in current LTPS technology, static discharge (ESD) protection in tft array substrate manufacturing process is a problem.
In the manufacturing process of tft array substrate, ESD once occurs for pixel region, then the TFT work that will lead to single-point pixel is different
Often or all pixels of row, column where ESD show that exception, array substrate can not work normally.As shown in Figure 1, especially adopting
It is carried out in the coating process of source-drain electrode metal layer 100 with physical vapour deposition (PVD) (PVD) method, it is easy in grid 200 and polycrystalline
ESD occurs between silicon layer 300.In order to reduce the incidence of ESD in tft array substrate manufacturing process, technical staff is taken
Equipment installs the various measures such as ion bar (Bar), ground connection additional, but the effect of these measures is not significant.
Summary of the invention
The purpose of the present invention is to provide a kind of production methods of TFT substrate, can not only ensure in source-drain electrode metal layer
Film forming procedure in static discharge phenomenon will not occur, and can be effectively reduced source-drain electrode metal layer lithographic process completion
The incidence of preceding static discharge phenomenon.
To achieve the above object, the present invention provides a kind of production method of TFT substrate, includes the following steps:
Step 1 provides a substrate, forms shading metal layer on the substrate, carries out pattern to the shading metal layer
Change processing, obtains several shading metal blocks, forms buffer layer on several shading metal blocks and substrate；
Step 2 forms several spaced polysilicon layers on the buffer layer, and each polysilicon layer includes being located at two
End the first heavily doped region and the second heavily doped region, be located in the middle third heavily doped region, be located at first heavily doped region and
The first channel region between third heavily doped region and the second ditch between second heavily doped region and third heavily doped region
Road area；First channel region and the second channel region respectively correspond setting above a shading metal block；
Step 3 forms gate insulating layer on the polysilicon layer and buffer layer, passes through on the gate insulating layer
Physical gas-phase deposite method forms gate metal layer, carries out patterned process to the gate metal layer, obtains corresponding first channel
First grid above area and the second grid above corresponding second channel region and connection first grid and second grid
Controlling grid scan line, while several coupled antistatic convex blocks are formed in the side of the controlling grid scan line；
Step 4 forms interlayer insulating film above first, second grid, controlling grid scan line and gate insulating layer,
Patterned process is carried out to the interlayer insulating film and gate insulating layer, is formed on the interlayer insulating film and gate insulating layer
The first via hole above corresponding first heavily doped region and the second heavily doped region is formed on the interlayer insulating film described in corresponding to
The second via hole above antistatic convex block；
Step 5 forms the source and drain for covering entire interlayer insulating film on interlayer insulating film by physical gas-phase deposite method
Pole metal layer, the source-drain electrode metal layer are in contact by the first via hole with the first heavily doped region and the second heavily doped region, simultaneously
It is in contact by the second via hole with the antistatic convex block of the controlling grid scan line side, due to controlling grid scan line connection first
Grid and second grid, so that the source-drain electrode metal layer is connected with first, second grid, while source-drain electrode gold
Belong to layer to be also connected with polysilicon layer, so that the voltage between polysilicon layer and the first, second grid is zero, avoids source
Static discharge phenomenon occurs between polysilicon layer and the first, second grid in the film forming procedure of drain metal layer；
Step 6 carries out patterned process to the source-drain electrode metal layer using one of lithographic process, obtains source electrode and leakage
Pole, the source electrode, drain electrode are in contact by the first via hole with the first heavily doped region and the second heavily doped region respectively.
In the step 1, the substrate is transparent substrate, and the buffer layer is for silicon oxide layer, silicon nitride layer or by oxygen
SiClx layer is superimposed the composite layer constituted with silicon nitride layer.
In the step 2, first heavily doped region, the second heavily doped region and third heavily doped region are N-type heavy doping
Area or p-type heavily doped region.
The ion mixed in the N-type heavily doped region is phosphonium ion or arsenic ion；Mixed in the p-type heavily doped region from
Son is boron ion or gallium ion.
In the step 3, along the extending direction of the controlling grid scan line, it is arranged one between every three adjacent polysilicon layers
A antistatic convex block.
In the step 3, the material of the gate metal layer is one of molybdenum, titanium, aluminium, copper or a variety of storehouse groups
It closes；It is compound that the gate insulating layer is that silicon oxide layer, silicon nitride layer or be superimposed by silicon oxide layer with silicon nitride layer is constituted
Layer.
In the step 4, the interlayer insulating film is for silicon oxide layer, silicon nitride layer or by silicon oxide layer and silicon nitride
The composite layer that layer superposition is constituted；In the step 5, the material of the source-drain electrode metal layer be one of molybdenum, titanium, aluminium, copper or
A variety of heap stack combinations.
In the step 6, the lithographic process includes light blockage coating, exposure, development, dry ecthing and photoresist removing processing procedure.
In dry etch process, part of the source-drain electrode deposition of metal in the second via hole is etched, thus
To source electrode, drain electrode and controlling grid scan line and the first, second grid between disconnect.
Beneficial effects of the present invention: a kind of production method of TFT substrate provided by the invention, by controlling grid scan line
Side forms antistatic convex block, forms the second via hole above the corresponding antistatic convex block on interlayer insulating film later, from
And after sedimentary origin drain metal layer, the source-drain electrode metal layer by the second via hole and the controlling grid scan line side prevent it is quiet
Electric convex block is in contact, since the controlling grid scan line connects the first, second grid, thus the source-drain electrode metal layer and described the
One, second grid is connected, while the source-drain electrode metal layer is also connected with polysilicon layer, so that polysilicon layer and
One, the voltage between second grid is zero, can not only ensure that electrostatic will not occur in the film forming procedure of source-drain electrode metal layer
Electric discharge phenomena, and can be effectively reduced the incidence of the static discharge phenomenon before the lithographic process of source-drain electrode metal layer is completed；
In addition, since the side of controlling grid scan line is provided with the second via hole of connection antistatic convex block, to occur in controlling grid scan line
When breaking, convenient for being repaired using the method for chemical vapor deposition.
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
Detailed description of the invention
With reference to the accompanying drawing, by the way that detailed description of specific embodiments of the present invention, technical solution of the present invention will be made
And other beneficial effects are apparent.
In attached drawing,
Fig. 1 is the schematic diagram that ESD event occurs in existing TFT substrate manufacturing process；
Fig. 2 is the schematic flow diagram of the production method of TFT substrate of the invention；
Fig. 3 is the schematic diagram of the step 1 of the production method of TFT substrate of the invention；
Fig. 4-5 is the schematic diagram of the step 2 of the production method of TFT substrate of the invention；
Fig. 6-7 is the schematic diagram of the step 3 of the production method of TFT substrate of the invention；
Fig. 8-9 is the schematic diagram of the step 4 of the production method of TFT substrate of the invention；
Figure 10-11 is the schematic diagram of the step 5 of the production method of TFT substrate of the invention；
Figure 12-13 is the schematic diagram of the step 6 of the production method of TFT substrate of the invention.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
Referring to Fig. 2, the present invention provides a kind of production method of TFT substrate, include the following steps:
Step 1, as shown in figure 3, provide a substrate 10, on the substrate 10 formed shading metal layer, to the shading
Metal layer carries out patterned process, obtains several shading metal blocks 20, the shape on several shading metal blocks 20 and substrate 10
At buffer layer 21.
Specifically, the substrate 10 is transparent substrate, preferably glass substrate.
Specifically, the buffer layer 21 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer and nitrogen
The composite layer that the superposition of SiClx layer is constituted.
Step 2, as illustrated in figures 4-5, forms several spaced polysilicon layers 30, Mei Geduo on the buffer layer 21
Crystal silicon layer 30 includes positioned at first heavily doped region 301 at both ends and the second heavily doped region 302, is located in the middle third heavily doped region
303, the first channel region 304 between first heavily doped region 301 and third heavily doped region 303 and it is located at described the
The second channel region 305 between two heavily doped regions 302 and third heavily doped region 303；First channel region 304 and the second channel
Area 305 respectively corresponds to be arranged above a shading metal block 20.
Specifically, first heavily doped region 301, the second heavily doped region 302 and third heavily doped region 303 are N-type weight
Doped region or p-type heavily doped region, the ion mixed in the N-type heavily doped region can be phosphorus (P) ion or arsenic (As) ion；Institute
Stating the ion mixed in p-type heavily doped region can be boron (B) ion or gallium (Ga) ion.
Step 3, as shown in fig. 6-7 forms gate insulating layer 31, in institute on the polysilicon layer 30 and buffer layer 21
It states and gate metal layer is formed by physical gas-phase deposite method on gate insulating layer 31, which is carried out at patterning
Reason, obtain 305 top of first grid 43 and corresponding second channel region of corresponding first channel region, 304 top second grid 44,
And the controlling grid scan line 41 of connection first grid 43 and second grid 44, while being formed in the side of the controlling grid scan line 41
Several coupled antistatic convex blocks 42.
Specifically, along the extending direction of the controlling grid scan line 41, (i.e. every three between every three adjacent polysilicon layers 30
Inside a adjacent pixel region) one antistatic convex block 42 of setting.
Specifically, the material of the gate metal layer can be one of molybdenum (Mo), titanium (Ti), aluminium (Al), copper (Cu)
Or a variety of heap stack combination.
Specifically, the gate insulating layer 31 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Step 4, as Figure 8-9, in first, second grid 43,44, controlling grid scan line 41 and gate insulating layer
31 tops form interlayer insulating film 50, patterned process are carried out to the interlayer insulating film 50 and gate insulating layer 31, described
302 top of corresponding first heavily doped region 301 and the second heavily doped region is formed on interlayer insulating film 50 and gate insulating layer 31
First via hole 51 forms the second via hole 52 above the corresponding antistatic convex block 42 on the interlayer insulating film 50.
Specifically, the interlayer insulating film 50 is silica (SiOx) layer, silicon nitride (SiNx) layer or by silicon oxide layer
The composite layer constituted is superimposed with silicon nitride layer.
Step 5, as shown in figs. 10-11, it is entire on interlayer insulating film 50 by physical gas-phase deposite method to form covering
The source-drain electrode metal layer 60 of interlayer insulating film 50, the source-drain electrode metal layer 60 pass through the first via hole 51 and the first heavily doped region
301 and second heavily doped region 302 be in contact, while by the second via hole 52 and the antistatic of 41 side of controlling grid scan line it is convex
Block 42 is in contact, since the controlling grid scan line 41 connects the first, second grid 43,44, thus the source-drain electrode metal layer 60
It is connected with first, second grid 43,44, while the source-drain electrode metal layer 60 is also connected with polysilicon layer 30, from
And the voltage between polysilicon layer 30 and the first, second grid 43,44 is made to be zero, avoid the film forming of source-drain electrode metal layer 60
Static discharge phenomenon occurs between polysilicon layer 30 and the first, second grid 43,44 in the process.
Specifically, the material of the source-drain electrode metal layer 60 can be molybdenum (Mo), titanium (Ti), aluminium (Al), in copper (Cu)
One or more heap stack combinations.
Step 6, as illustrated by figs. 12-13, carries out at patterning the source-drain electrode metal layer 60 using one of lithographic process
Reason, obtains source electrode 61 and drain electrode 62, the source electrode 61, drain electrode 62 respectively by the first via hole 51 and the first heavily doped region 301 and
Second heavily doped region 302 is in contact.
Specifically, the lithographic process includes light blockage coating, exposure, development, dry ecthing and photoresist removing processing procedure.Dry
In etching process, the part that the source-drain electrode metal layer 60 is deposited in the second via hole 52 is etched, the source electrode obtained from
61, it is disconnected between drain electrode 62 and controlling grid scan line 41 and the first, second grid 43,44.
In conclusion a kind of production method of TFT substrate provided by the invention, is formed by the side in controlling grid scan line
Antistatic convex block forms the second via hole above the corresponding antistatic convex block, thus depositing on interlayer insulating film later
After source-drain electrode metal layer, the source-drain electrode metal layer passes through the antistatic convex block phase of the second via hole and the controlling grid scan line side
Contact, since the controlling grid scan line connects the first, second grid, thus the source-drain electrode metal layer and described first, second
Grid is connected, while the source-drain electrode metal layer is also connected with polysilicon layer, so that polysilicon layer and first, second
Voltage between grid is zero, and it is existing can not only to ensure occur in the film forming procedure of source-drain electrode metal layer static discharge
As, and can be effectively reduced the incidence of the static discharge phenomenon before the lithographic process of source-drain electrode metal layer is completed；In addition, by
The side of controlling grid scan line is provided with the second via hole of connection antistatic convex block, thus when open circuit occurs for controlling grid scan line,
Convenient for being repaired using the method for chemical vapor deposition.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the claims in the present invention
Protection scope.
Claims (8)
1. a kind of production method of TFT substrate, which comprises the steps of:
Step 1 provides a substrate (10), forms shading metal layer on the substrate (10), carries out to the shading metal layer
Patterned process obtains several shading metal blocks (20), is formed on several shading metal blocks (20) and substrate (10) slow
Rush layer (21)；
Step 2 forms several spaced polysilicon layers (30), each polysilicon layer (30) packet on the buffer layer (21)
Include positioned at both ends the first heavily doped region (301) and the second heavily doped region (302), be located in the middle third heavily doped region (303),
The first channel region (304) between first heavily doped region (301) and third heavily doped region (303) and it is located at described
The second channel region (305) between second heavily doped region (302) and third heavily doped region (303)；First channel region (304)
It respectively corresponds with the second channel region (305) and is arranged above a shading metal block (20)；
Step 3 forms gate insulating layer (31) on the polysilicon layer (30) and buffer layer (21), in the gate insulator
Gate metal layer is formed by physical gas-phase deposite method on layer (31), patterned process is carried out to the gate metal layer, is obtained
The second grid above first grid (43) and corresponding second channel region (305) above corresponding first channel region (304)
(44) and the controlling grid scan line (41) of connection first grid (43) and second grid (44), while in the controlling grid scan line
(41) side forms several coupled antistatic convex blocks (42)；
Step 4 is formed above first, second grid (43,44), controlling grid scan line (41) and gate insulating layer (31)
Interlayer insulating film (50) carries out patterned process to the interlayer insulating film (50) and gate insulating layer (31), in the interlayer
It is formed above corresponding first heavily doped region (301) and the second heavily doped region (302) on insulating layer (50) and gate insulating layer (31)
The first via hole (51), the second mistake above the corresponding antistatic convex block (42) is formed on the interlayer insulating film (50)
Hole (52)；
Step 5 passes through the entire interlayer insulating film (50) of physical gas-phase deposite method formation covering on interlayer insulating film (50)
Source-drain electrode metal layer (60), the source-drain electrode metal layer (60) pass through the first via hole (51) and the first heavily doped region (301) and the
Two heavily doped regions (302) are in contact, while convex by the second via hole (52) and the antistatic of the controlling grid scan line (41) side
Block (42) is in contact, due to the controlling grid scan line (41) connection first grid (43) and second grid (44), thus the source
Drain metal layer (60) is connected with first, second grid (43,44), at the same the source-drain electrode metal layer (60) also with it is more
Crystal silicon layer (30) is connected, so that the voltage between polysilicon layer (30) and the first, second grid (43,44) is zero, keeps away
Exempt to occur between polysilicon layer (30) and the first, second grid (43,44) in the film forming procedure of source-drain electrode metal layer (60) quiet
Discharge of electricity phenomenon；
Step 6, using one of lithographic process to the source-drain electrode metal layer (60) carry out patterned process, obtain source electrode (61) with
It drains (62), the source electrode (61), drain electrode (62) pass through the first via hole (51) and the first heavily doped region (301) and the second weight respectively
Doped region (302) is in contact；
In the step 3, extending direction along the controlling grid scan line (41) is set between every three adjacent polysilicon layers (30)
Set an antistatic convex block (42).
2. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 1, the substrate (10)
For transparent substrate, the buffer layer (21) is that silicon oxide layer, silicon nitride layer or be superimposed by silicon oxide layer with silicon nitride layer is constituted
Composite layer.
3. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 2, described first is heavily doped
Miscellaneous area (301), the second heavily doped region (302) and third heavily doped region (303) are N-type heavily doped region or p-type heavily doped region.
4. the production method of TFT substrate as claimed in claim 3, which is characterized in that mixed in the N-type heavily doped region from
Son is phosphonium ion or arsenic ion；The ion mixed in the p-type heavily doped region is boron ion or gallium ion.
5. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 3, the gate metal
The material of layer is one of molybdenum, titanium, aluminium, copper or a variety of heap stack combinations；The gate insulating layer (31) is silicon oxide layer, nitrogen
SiClx layer or the composite layer constituted is superimposed with silicon nitride layer by silicon oxide layer.
6. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 4, the layer insulation
Layer (50) is silicon oxide layer, silicon nitride layer or is superimposed the composite layer constituted with silicon nitride layer by silicon oxide layer；The step 5
In, the material of the source-drain electrode metal layer (60) is one of molybdenum, titanium, aluminium, copper or a variety of heap stack combinations.
7. the production method of TFT substrate as described in claim 1, which is characterized in that in the step 6, the lithographic process
Processing procedure is removed including light blockage coating, exposure, development, dry ecthing and photoresist.
8. the production method of TFT substrate as claimed in claim 7, which is characterized in that in dry etch process, the source-drain electrode
The part that metal layer (60) is deposited in the second via hole (52) is etched, the source electrode obtained from (61), drain electrode (62) and grid
It is disconnected between pole scan line (41) and the first, second grid (43,44).
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441372A (en) * | 2007-11-23 | 2009-05-27 | 上海广电Nec液晶显示器有限公司 | Electrostatic discharge protection device of LCD device and manufacturing method thereof |
| CN102645801A (en) * | 2011-04-07 | 2012-08-22 | 京东方科技集团股份有限公司 | Thin-film transistor array substrate, color film substrate, manufacturing methods and display device |
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| JP4718677B2 (en) * | 2000-12-06 | 2011-07-06 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441372A (en) * | 2007-11-23 | 2009-05-27 | 上海广电Nec液晶显示器有限公司 | Electrostatic discharge protection device of LCD device and manufacturing method thereof |
| CN102645801A (en) * | 2011-04-07 | 2012-08-22 | 京东方科技集团股份有限公司 | Thin-film transistor array substrate, color film substrate, manufacturing methods and display device |
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