CN105655329A

CN105655329A - Semiconductor device with a plurality of transistors

Info

Publication number: CN105655329A
Application number: CN201410725320.3A
Authority: CN
Inventors: 赵劼; 钟汇才
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2014-12-02
Filing date: 2014-12-02
Publication date: 2016-06-08

Abstract

A semiconductor device comprising one or more FinFET inverters, each FinFET inverter comprising at least one PFinFET and at least one NFinFET, each PFinFET and NFinFET comprising: a plurality of fin structures extending in a first direction; a first gate extending along a second direction to span the plurality of fin structures; a second gate parallel to the first gate and spanning the plurality of fin structures; the source region and the drain region are distributed in the plurality of fin structures and are arranged on two sides of the first grid and the second grid; first gates of the PFINFET and the NFINFET are connected to an input node, drain regions of the PFINFET and the NFINFET are connected to an output node, a source region of the PFINFET is connected to a power supply voltage, and a source region of the NFINFET is grounded; wherein the second gates of the PFinFET and NFinFET are connected to a first control voltage and a second control voltage, respectively. According to the semiconductor device, the control gates of the PFinFET and the NFinFET are respectively and independently connected, the threshold voltage of the front gate is changed through the bias voltage of the rear gate, the turn-off current of the device is effectively controlled, and larger gate driving capability and lower leakage current are provided.

Description

Semiconducter device

Technical field

The present invention relates to a kind of semiconducter device, particularly relate to a kind of semiconducter device comprising FinFET technique independent gate phase inverter.

Background technology

The design of cmos digital IC can be divided into Full-custom design and semi-custom designs usually. Full-custom design is a kind of method of design based on transistor level, and all devices of circuit, interconnection and domain all adopt directly design. Such as customize the parameters such as its distinctive long-width ratio for each MOSFET, for every bar critical path by the parasitic distribution parameter regulating the polysilicon doping concentration of wiring or the parameter such as metal material, width and then regulate it concrete. Full-custom design can better improve device performance, but consuming time more, it is difficult to realizes automation design completely. Semi-custom designs can be based on gate array or based on the design in standard cell storehouse.

Standard cell storehouse is the basis of VLSI automation design, refer to some basic logic unit in a circuit layout, such as gating circuit, multi-way switch, triggering device etc., design according to optimum design principle, when carrying out IC and design, only need from standard storehouse, to call required mark unit according to circuit requirement, AUTOMATIC LOGIC SYNTHESIS and autoplacement's wiring can be carried out. The standard storehouse of optimizing application can carry out that logic is comprehensive and laying out pattern connects up automatically, it is to increase design efficiency.

As shown in Figure 1A, its corresponding domain structure designs as shown in Figure 1B the device principle figure of a kind of traditional CMOS inverter based on standard cell storehouse. Wherein, the substrate voltage of PMOS device connects noble potential VDD, and nmos device substrate voltage connects low potential GND.

On the other hand, along with device size equal proportion is reduced to 22nm technology and following, such as the three-dimensional multi-gate device of FinFET (FinFET) and three grid (tri--gate) device becomes one of the most promising new unit technology, and these structures enhance grid control ability, inhibit electric leakage and short-channel effect. FinFET is different from planar CMOS device with tri-gate devices, is three-dimensional (3D) device.Usually, on body substrate or SOI substrate, form semiconductor fin by selectivity dry method or wet etching, then form gate stack across fin sheet. Three-dimensional tri-gate transistors all defines conducting channel on three sides of vertical fin structure, thus provides " fully-depleted " operational mode. Tri-gate transistors can also have the multiple fin sheets connecting and to increase for more high performance total driving force.

But, continuing to reduce due to FinFET, traditional inverter circuit structure as shown in Figure 1A, Figure 1B is difficult to the performance demand of meeting requirements on three-dimensional FinFET. In FinFET technique, due to short-channel effect, it is necessary to bigger grid driving force and lower leakage current. And traditional phase inverter substrate is simply connected to VDD or GND, the regulation and control for threshold voltage of the grid are limited, are difficult to the work function needed for obtaining in little size FinFET structure; In addition, between substrate and Qi Pianzhong source and drain district, voltage difference cannot accurately control, it is easy to cause substrate break-through under some conductive condition and bigger leakage occurs, and affects the performance of device.

Summary of the invention

Described in upper, it is an object of the invention to overcome above-mentioned technical difficulty, improve the layout design method of FinFET, effectively to provide bigger grid driving force and lower leakage current.

For this reason, the present invention provides a kind of semiconducter device, comprises one or more FinFET phase inverter, and each FinFET phase inverter comprises at least one PFinFET and at least one NFinFET, PFinFET and NFinFET includes each: multiple fin structure, along first party to extension; First grid, extends along second direction and crosses over multiple fin structure; Second gate pole, crosses over multiple fin structure with the first gate parallel; Source region and drain region, be distributed in multiple fin structure and in the both sides of the first grid, second gate pole; Wherein, first grid of PFinFET and NFinFET is connected to input node, and the drain region of PFinFET and NFinFET is connected to output node, and the source region of PFinFET is connected to voltage of supply, the source region ground connection of NFinFET; Wherein, the second gate pole of PFinFET and NFinFET is connected to the first control voltage and the 2nd control voltage respectively.

Wherein, the first control voltage is greater than the 2nd control voltage.

Wherein, in multiple FinFET phase inverter, the gate work-function of each PFinFET is mutually equal or inequal, and the gate work-function of each NFinFET is mutually equal or inequal.

Wherein, gate work-function is regulated by controlling doping and/or the metallic substance of each first grid and/or each second gate pole.

Wherein, time of lag is regulated by regulating the distribution link of each the first grid and the doping of source and drain district.

According to the semiconducter device of the present invention, by the control grid of PFinFET and NFinFET separate connection separately, the threshold voltage of grid before being changed by rear grid bias, the cut-off current of effective control device, it is provided that bigger grid driving force and lower leakage current.

Accompanying drawing explanation

The technical scheme of the present invention is described in detail referring to accompanying drawing, wherein:

Figure 1A is the equivalent circuit theory figure of the CMOS inverter according to prior art;

Figure 1B is the domain structure of the CMOS inverter according to prior art;

Fig. 2 A is the equivalent circuit theory figure of the FinFET technique phase inverter according to the present invention; And

Fig. 2 B is the domain structure of the FinFET technique phase inverter according to the present invention.

Embodiment

Referring to accompanying drawing and feature and the technique effect thereof of technical solution of the present invention are described in detail in conjunction with schematic embodiment, disclose the FinFET phase inverter that bigger grid driving force and lower leakage current are provided and the semiconducter device comprising this phase inverter. It is noted that similar Reference numeral represents similar structure, term " first " used in the application, " the 2nd ", " on ", D score etc. can be used for modifying various device architecture or manufacturing process. These modify the space, order or the level relation that not imply institute's modification device architecture or manufacturing process unless stated otherwise.

As shown in Figure 2 A and 2 B, the FinFET technique independent gate phase inverter of the present invention has an input terminus A, an output terminal OUT, the PFinFET being formed in N trap, forming p+ type source and drain district by injecting p+ ion doping to fin structure as PMOS is formed in Fig. 2 B top, and similar being formed in P trap, be formed in Fig. 2 B bottom by the NFinFET injecting n+ ion doping to fin structure and forming n+ type source and drain district as NMOS. Wherein, PFinFET and NFinFET includes multiple fin structure along first party to extension that is parallel to each other, first grid of PFinFET and NFinFET along be perpendicular to first party to second direction and extend and be jointly connected to input terminus node A, source electrode in fin structure (comprise in fin sheet multiple) is connected to VDD and GND respectively, and drain electrode (comprise in fin sheet multiple) is jointly connected to and exports node OUT. It should be noted that, different from traditional CMOS inverter as shown in Figure 1, based on the phase inverter of FinFET technique except the first grid being connected to input node A, also comprising the second gate pole with the first gate parallel, wherein the second gate pole of PFinFET is connected to the first control voltage V_HIGH, and the second gate pole of NFinFET is connected to the 2nd control voltage V_LOW. First control voltage is different from the 2nd control voltage and is different from the input voltage A that the first grid connects, thus by the discrete threshold voltage changing the first grid of the bias voltage of second gate pole, and then can the cut-off current of effective control device.

Emulate, by TCAD doping environment, the gate work function device that PFinFET with NFinFET can be provided different, comprise symmetry gate work function device and asymmetry gate work function device.

In a preferred embodiment of the invention, FinFET phase inverter is symmetry gate work function circuit. Concrete, semi-conductor chip comprises multiple FinFET phase inverter as above, namely wherein regulate the doping in first grid (also before grid) of PFinFET in each FinFET phase inverter or second gate pole (also namely after grid) or metallic substance to make the gate work function of each PFinFET equal, and first grid of similar adjustment NFinFET and/or each second gate extremely in doping or metallic substance make the gate work function of each NFinFET equal. On this basis, it is possible to the first control voltage that further adjustment second gate pole connects and/or the 2nd control voltage, the electric property needed for acquisition.

In another preferred embodiment of the present invention, FinFET phase inverter is asymmetry gate work function circuit. Concrete, semi-conductor chip comprises multiple FinFET phase inverter as above, wherein, regulate gate work-function that the doping in each transistor first grid or metallic substance make each PFinFET mutually not etc., and the gate work-function of NFinFET is mutually not etc. yet, precipitous sub-threshold slope, ultralow cut-off current and very high working current thus can be provided.

Although it is symmetrical different with the concrete processing parameter of asymmetric gate work function circuit, but all can complete design by identical domain structure as shown in Figure 2, so be conducive to carrying out device transplanting, it is possible to compatible to be applied to VLSI Design with other FinFET or CMOS technology. In addition, although it is not very strict non-critical path that this kind of circuit structure is mainly used in for timing requirements, but can change the distribution link of the first grid in single PFinFET or NFinFET further on the basis of the application and corresponding Qi Pianzhong source and drain district doping proportioning obtain needed for distribution of impedance, thus in adjustment criteria storehouse unit separately time of lag to obtain and the total delay time of corresponding critical path coupling.

Although the present invention being described with reference to one or more exemplary embodiment, those skilled in the art can know, without the need to departing from the scope of the invention, device architecture made various suitable change and equivalents. In addition, can make by disclosed instruction and many may be suitable for the amendment of particular condition or material and do not depart from the scope of the invention. Therefore, the object of the present invention is not to be limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacture method thereof will comprise all embodiments falling in the scope of the invention.

Claims

1. a semiconducter device, comprises one or more FinFET phase inverter, and each FinFET phase inverter comprises at least one PFinFET and at least one NFinFET, PFinFET and NFinFET, and each includes:

Multiple fin structure, along first party to extension;

First grid, extends along second direction and crosses over multiple fin structure;

Second gate pole, crosses over multiple fin structure with the first gate parallel;

Source region and drain region, be distributed in multiple fin structure and in the both sides of the first grid, second gate pole;

Wherein, first grid of PFinFET and NFinFET is connected to input node, and the drain region of PFinFET and NFinFET is connected to output node, and the source region of PFinFET is connected to voltage of supply, the source region ground connection of NFinFET;

Wherein, the second gate pole of PFinFET and NFinFET is connected to the first control voltage and the 2nd control voltage respectively.

2. semiconducter device as claimed in claim 1, wherein, the first control voltage is greater than the 2nd control voltage.

3. semiconducter device as claimed in claim 1, wherein, in multiple FinFET phase inverter, the gate work-function of each PFinFET is mutually equal or inequal, and the gate work-function of each NFinFET is mutually equal or inequal.

4. semiconducter device as claimed in claim 3, wherein, regulates gate work-function by controlling doping and/or the metallic substance of each first grid and/or each second gate pole.

5. semiconducter device as claimed in claim 1, wherein, is adulterated by the distribution link and source and drain district regulating each the first grid and is regulated time of lag.