CN105653495A - Dual-processor electronic device and rapid power boot method thereof - Google Patents
Dual-processor electronic device and rapid power boot method thereof Download PDFInfo
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- CN105653495A CN105653495A CN201410642426.7A CN201410642426A CN105653495A CN 105653495 A CN105653495 A CN 105653495A CN 201410642426 A CN201410642426 A CN 201410642426A CN 105653495 A CN105653495 A CN 105653495A
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- electronic installation
- dynamic ram
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Abstract
A dual-processor electronic device includes a first processor, a second processor and a dynamic random access memory; the first processor is used for executing local initialization of the first processor and then sending a wake-up command to the second processor to wake up the second processor; the second processor is used for executing local initialization of the second processor, copying a mirror image file to the dynamic random access memory and performing uncompressing, and then sending ready information to the first processor after uncompressing; and the first processor is also used for delaying start, and jumping to the copied mirror image file to start a process after the first processor receives the ready information and a delayed start time arrives. The invention also provides a rapid power boot method of the dual-processor electronic device. The dual-processor electronic device and the rapid power boot method thereof can achieve rapid power boot and can save running-up time.
Description
Technical field
The present invention relates to computer processor, particularly relate to a kind of dual processor electronic installation and the method for quick turn-on startup thereof.
Background technology
At present, two-processor system is widely used in communication electronic equipment. Along with communication electronic equipment is more and more higher to the requirement of reaction rate, the operation rate of dual processor also requires that more and more higher, The faster the better to be so necessarily required to the start-up course of dual processor, but when processor starts, the Booting sequence relying solely on each processor self carries out electrifying startup, so certainly will causing that the time restriction started is at some bottleneck, how utilizing the communication having in the electronic installation of dual processor between processor to reach to improve mutually the electrifying startup time each other is a problem being worth research.
Summary of the invention
In view of this, a kind of dual processor electronic installation need to be provided, can start by fast powering-up, save the startup time.
Additionally, also need a kind of method providing dual processor electronic installation quick turn-on to start, can start by fast powering-up, save the startup time.
A kind of two-processor system that embodiment of the present invention provides includes first processor, second processor and dynamic RAM, first processor is used for performing to send wake command to the second processor to wake the second processor up after first processor this locality initializes. Second processor initializes for performing second processor this locality after being waken up by first processor, replicates image file and and decompresses in dynamic RAM, and after having decompressed the ready information of transmission to first processor. First processor is additionally operable to delay start, and after the time receiving ready information and delay start arrives, jumps to the image file after duplication and start process initiation.
Preferably, first processor is additionally operable to, before performing delay start, perform peripheral hardware initialization procedure.
Preferably, time delay is five minutes.
Preferably, dynamic RAM is Double Data Rate synchronous DRAM.
The method that a kind of two-processor system that embodiment of the present invention provides quickly starts includes: first processor performs to send wake command to the second processor to wake the second processor up after first processor this locality initializes;Second processor performs second processor this locality after being waken up by first processor and initializes, and replicates image file and and decompresses in dynamic RAM, and after has decompressed the ready information of transmission to first processor; First processor delay start, and after receiving ready information and arriving time delay, jump to the image file after duplication and start process initiation.
Preferably, first processor, before performing delay start, performs peripheral hardware initialization procedure.
Preferably, time delay is five minutes.
Preferably, dynamic RAM is Double Data Rate synchronous DRAM.
The method that the above-mentioned electronic installation with dual processor and quick turn-on thereof start can utilize the second processor by duplication image file decompression and to be sent to first processor before first processor carries out peripheral hardware initialization, thus allowing first processor eliminate the step replicating image file and decompressing, thus saving the electrifying startup time, it is achieved quickly start.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of dual processor electronic installation of the present invention.
The second processor that Fig. 2 is dual processor electronic installation of the present invention assists first processor fast powering-up to start the functional block diagram of an embodiment.
Fig. 3 is the flow chart of method one embodiment of the second processor assistance first processor fast powering-up startup of dual processor electronic installation of the present invention.
The second processor that Fig. 4 is dual processor electronic installation of the present invention assists the startup of first processor fast powering-up and first processor to start the comparison diagram of an embodiment voluntarily.
Main element symbol description
Dual processor electronic installation 100
First processor 10
Second processor 20
Dynamic RAM 30
Detailed description of the invention
Consult Fig. 1, it is shown that for the structured flowchart of dual processor electronic installation 100 of the present invention. In the present embodiment, dual processor electronic installation 100 includes first processor the 10, second processor 20 and dynamic RAM 30. First processor 10 is connected by communications connector with the second processor 20, is also communicatively coupled with dynamic RAM 30 simultaneously. First processor 10 and the second processor 20 all include double-mirror file (image) and other equipment needed therebies, and being all connected with various peripheral hardware (not shown), dynamic RAM 30 can be Double Data Rate synchronous DRAM.
Consult Fig. 2, it is shown that the second processor 20 for dual processor electronic installation 100 of the present invention assists first processor 10 fast powering-up to start the functional block diagram of an embodiment. In the present embodiment, the second processor 20 can assist in first processor 10 fast powering-up and starts, and in other embodiments, first processor 10 also is able to assist the second processor 20 to realize fast powering-up and starts.
In the present embodiment, when first processor 10 needs to carry out electrifying startup, first processor 10 is first carried out initialization and Double Data Rate synchronous DRAM (DDR) calibration of first processor (CPU), treat DDR calibration complete after and before needs carry out peripheral hardware initialization, first processor wake-up mechanism can send wake command to the second processor and wake the second processor 20 up. Second processor 20 is after being woken, perform the initialization of the second processor (CPU) and replicate image file (image) and and decompress this image in Double Data Rate synchronous DRAM (DDR), after waiting to decompress, second processor 20 sends this image to first processor 10, sends ready information to first processor simultaneously.
While the second processor 20 processes image, first processor 10 can perform the initialized operation of peripheral hardware, and automatically starts after arranging time delay after receiving the image that the second processor 20 sends over, and such as time delay is 5 seconds. If after the time arrival receiving after the ready information that the second processor 20 sends and postpone, jumping to image and start process, complete electrifying startup. If it addition, be not received by, after arriving time delay, the ready information that the second processor 20 sends, the second processor will reset time delay, and waits the ready information from first processor.
So, originally needing the transition of operation removing and decompressing this image in image to DDR that replicates performed to assist to the second processor 20 at first processor 10, saving the electrifying startup step of first processor 10, thus saving the startup time.
Consult Fig. 3, it is shown that assist the flow chart of method one embodiment that first processor 10 fast powering-up starts for the second processor 20 of dual processor electronic installation 100 of the present invention. In the present embodiment, this method is used in the dual processor electronic installation 100 of Fig. 1, and is jointly completed by first processor 10 and the second processor 20. In other embodiments, first processor 10 also is able to assist the second processor 20 to realize fast powering-up startup.
In step S300, when first processor needs to carry out electrifying startup, initialization and Double Data Rate synchronous DRAM (DDR) calibration of first processor (CPU) is first carried out. Treat DDR calibration complete after and before needs carry out peripheral hardware initialization, perform step S302.
In step S302, first processor sends wake command to the second processor, after second processor receives this wake command, perform the initialization of the 2nd CPU, replicate in image to DDR and remove and decompress this image, after waiting to decompress, and send this image to first processor, send ready information to first processor simultaneously. And while the second processor processes image, after first processor can perform the initialized operation of peripheral hardware, perform S304.
In step S304, first processor starts after arranging time delay after receiving the image that the second processor 20 sends over automatically, and such as time delay is 5 seconds.
In step S306, first processor is waiting receive the ready information that the second processor sends after and time delay to after jump to image startup process, it is achieved the electrifying startup of first processor.
So, originally needing the transition of operation removing and decompressing this image in image to DDR that replicates performed to assist to the second processor at first processor, saving the electrifying startup step of first processor, thus saving the startup time.
Consult Fig. 4, it is shown that the second processor 20 for dual processor electronic installation 100 of the present invention assists the startup of first processor 10 fast powering-up and first processor 10 to start the comparison diagram of an embodiment voluntarily. In other embodiments, first processor 10 also is able to assist the second processor 20 to realize fast powering-up startup.
In the present embodiment, what upper figure represented is fate map (illustrating with upper figure below) that first processor starts voluntarily, what figure below represented is fate map (illustrating with figure below below) that the second processor assists that first processor fast powering-up starts. What represent in the oval frame in upper figure and figure below is the operation of first processor execution, what represent in square box is the operation of the second processor execution, the time shaft of the electrifying startup represented from left to right of arrow in upper figure and figure below, and the Dose times that S represents second.
Contrast from upper figure below, the final electrifying startup time of upper figure first processor is 12 seconds, and the final electrifying startup time of figure below first processor is 7 seconds, it is clear that, after the assistance of the second processor, the required electrifying startup time of first processor shortens. The operation removing and decompressing this image in image to DDR is replicated owing to utilizing the second processor to carry out before carrying out peripheral hardware initialization at first processor, so it is in time delay at first processor and still carries out the operation that originally needs just can carry out after waiting, it is greatly saved operating procedure, thus saving the power-on time of first processor.
Be can be seen that by above-described embodiment, in dual processor electronic installation, when some processor needs to carry out electrifying startup, can perform to replicate the operation removing and decompressing this image in image to DDR by means of another processor, thus can decrease the drawbacks to be operated such as single-processor needs, improve the efficiency of electrifying startup, save the time of electrifying startup.
The method being above dual processor electronic installation provided by the present invention and quick turn-on thereof are started is described in detail, principles of the invention and embodiment are set forth by the specific embodiment that arrived used herein, and the explanation of above example is only intended to help to understand inventive method and the core concept thereof of the present invention; Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, all can by changing part in detailed description of the invention and range of application, in sum, present invention should not be construed as limitation of the present invention.
Claims (8)
1. a dual processor electronic installation, it is characterised in that including:
Dynamic RAM;
First processor, is used for performing to send wake command to described second processor to wake described second processor up after described first processor this locality initializes; And
Second processor, initializes for performing described second processor this locality after being waken up by described first processor, replicates image file and and decompresses in described dynamic RAM, and sends ready information extremely described first processor after having decompressed;
Wherein, described first processor is additionally operable to delay start, and after the time receiving described ready information and described delay start arrives, jumps to the image file after described duplication and start process initiation.
2. dual processor electronic installation as claimed in claim 1, it is characterised in that described first processor is additionally operable to, before performing delay start, perform peripheral hardware initialization procedure.
3. dual processor electronic installation as claimed in claim 1, it is characterised in that the time of described delay start is five seconds.
4. dual processor electronic installation as claimed in claim 1, it is characterised in that described dynamic RAM is Double Data Rate synchronous DRAM.
5. the method that dual processor electronic installation quick turn-on starts, described dual processor electronic installation includes first processor, the second processor and dynamic RAM, and described method includes:
First processor performs to send wake command to described second processor to wake described second processor up after described first processor this locality initializes;
Second processor performs described second processor this locality after being waken up by first processor and initializes, and replicates image file and and decompresses in described dynamic RAM, and sends ready information extremely described first processor after having decompressed; And
First processor delay start, and after the time receiving described ready information and described delay start arrives, jump to the image file after described duplication and start process initiation.
6. there is method that the electronic installation quick turn-on of dual processor starts as claimed in claim 5, it is characterised in that: described first processor, before performing delay start, performs peripheral hardware initialization procedure.
7. there is method that the electronic installation quick turn-on of dual processor starts as claimed in claim 5, it is characterised in that: the time of described delay start is five seconds.
8. there is method that the electronic installation quick turn-on of dual processor starts as claimed in claim 5, it is characterised in that described dynamic RAM is Double Data Rate synchronous DRAM.
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| CN201410642426.7A CN105653495B (en) | 2014-11-13 | 2014-11-13 | Dual processor electronic device and its method of quick turn-on starting |
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| CN201410642426.7A CN105653495B (en) | 2014-11-13 | 2014-11-13 | Dual processor electronic device and its method of quick turn-on starting |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109683968A (en) * | 2018-12-18 | 2019-04-26 | 北京东土军悦科技有限公司 | Interchanger quick start method, interchanger and storage medium |
| CN112214425A (en) * | 2020-08-24 | 2021-01-12 | Oppo广东移动通信有限公司 | Data transmission method, data transmission device, computer equipment and storage medium |
| CN114967890A (en) * | 2021-02-24 | 2022-08-30 | 慧与发展有限责任合伙企业 | Managing transitions of a computing system from a standby power state to a powered-on state |
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| CN102193839A (en) * | 2010-03-12 | 2011-09-21 | 鸿富锦精密工业（深圳）有限公司 | Electronic device and startup method thereof |
| CN102253844A (en) * | 2010-05-18 | 2011-11-23 | 大唐移动通信设备有限公司 | Method and device for starting processor |
| US20130151813A1 (en) * | 2011-12-13 | 2013-06-13 | Hon Hai Precision Industry Co., Ltd. | Switch system for dual central processing units |
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| CN1963759A (en) * | 2006-12-01 | 2007-05-16 | 北京中星微电子有限公司 | Guide method and system of coprocessor |
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| CN102253844A (en) * | 2010-05-18 | 2011-11-23 | 大唐移动通信设备有限公司 | Method and device for starting processor |
| US20130151813A1 (en) * | 2011-12-13 | 2013-06-13 | Hon Hai Precision Industry Co., Ltd. | Switch system for dual central processing units |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109683968A (en) * | 2018-12-18 | 2019-04-26 | 北京东土军悦科技有限公司 | Interchanger quick start method, interchanger and storage medium |
| CN112214425A (en) * | 2020-08-24 | 2021-01-12 | Oppo广东移动通信有限公司 | Data transmission method, data transmission device, computer equipment and storage medium |
| CN114967890A (en) * | 2021-02-24 | 2022-08-30 | 慧与发展有限责任合伙企业 | Managing transitions of a computing system from a standby power state to a powered-on state |
| CN114967890B (en) * | 2021-02-24 | 2024-03-29 | 慧与发展有限责任合伙企业 | Method, manageability controller, and machine-readable medium for managing computing system |
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| CN105653495B (en) | 2019-01-18 |
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