CN105653477A - Double-port RAM-based method for communication of hard core and soft core in FPGA - Google Patents
Double-port RAM-based method for communication of hard core and soft core in FPGA Download PDFInfo
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- CN105653477A CN105653477A CN201510974101.3A CN201510974101A CN105653477A CN 105653477 A CN105653477 A CN 105653477A CN 201510974101 A CN201510974101 A CN 201510974101A CN 105653477 A CN105653477 A CN 105653477A
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- ram
- state
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- stone
- soft core
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/16—Memory access
Abstract
The invention discloses a double-port RAM-based method for the communication of a hard core and a soft core in an FPGA. The method comprises a step of opening up a data state area RAM#1, a data state area RAM#2, a data state area RAM#3, a data state area RAM#4, a data state area RAM#5 and a data state area RAM#6 in a double-port RAM. According to the method, the characteristics of the double-port RAM are utilized, so that the communication between the hard core and the soft core of the FPGA is realized through an efficient and asynchronous manner with few resources occupied.
Description
Technical field
The present invention relates to the method that the inner stone of a kind of FPGA based on dual port RAM communicates with soft core.
Background technology
Stone and soft exchange data in the FPGA of current power electronic applications, the general method using bus address to map transmits data certain limitation; So adopting two more and more being used of mouth ram signalling methods, but lack a kind of reasonably communication protocol; Existing signalling methods, owing to storage process is synchronous, consequently, it is desirable to real-time interruption processes the information received, CPU is that rate of utilization is too high, requires also high to hardware.
Summary of the invention
The technical problem to be solved in the present invention is existing pair of mouth ram signalling methods, it is necessary to real-time interruption processes the information received, and CPU is that rate of utilization is too high, requires also high to hardware, causes with high costs.
For solving the problems of the technologies described above, the technical solution used in the present invention is: the method that the inner stone of a kind of FPGA based on dual port RAM communicates with soft core, opens up data state region RAM#1, data state region RAM#2, data state region RAM#3, data state region RAM#4, data state region RAM#5 and data state region RAM#6 in dual port RAM; Described RAM#1 is for describing the read-write state of electric parameters, parameter, order data; Stone, soft core control the exchange of both data by reading these read-write states alternately; The data that described RAM#2 collects for writing stone in RAM#1, when stone writes data in relevant RAM#2, and after mark state in set RAM#1, soft core reads the data in RAM#2 according to the state in RAM#1, and processes this data; Described RAM#3 is for writing the order of soft core, and the mark state in set RAM#1; Stone reads the order in RAM#3 according to the state in RAM#1, and performs; Described RAM#4, for the amendment of soft core stone information; 1) soft core is in parameter read-in RAM#4, and the mark state in set RAM#1; Stone reads the parameter in RAM#4 according to the state in RAM#1, and revises parameter; 2) stone is in parameter read-in RAM#4, and the mark state in set RAM#1; Soft core reads the parameter in RAM#4 according to the state in RAM#1, checks that whether this parameter is correct, reliably; Described RAM#5, for writing the failure message of stone, and the mark state in set RAM#1; Soft core reads the fault code in RAM#5 according to the state in RAM#1 and stores display; Described RAM#6, for writing waveform information when stone fault occurs, and the mark state in set RAM#1;Soft core reads the fault code in RAM#6 according to the state in RAM#1 and stores display.
It is an advantage of the invention that: the characteristic utilizing two mouth ram, with a kind of efficient between the soft core stone of FPGA, asynchronous, take the few signalling methods of resource to realize, provide a kind of reliable and efficient communication protocol, the soft core of stone only needs often to read several zone bits little inside RAM#1, so that it may to know the situation of whole communication. Whole storage process is an asynchronous process, it is not necessary to as other signalling methods, it is necessary to real-time interruption processes the information received. Greatly reducing CPU is rate of utilization, saves the hardware resource of more preciousnesses.
Embodiment
The method that the inner stone of a kind of FPGA based on dual port RAM of the present invention communicates with soft core, concrete steps are as follows:
Dual port RAM opens the region RAM#1 of a blocks of data state, is used for describing electric parameters, parameter, the read-write state of the data such as order; Stone, no these states that read easily of soft nuclear energy are to control the exchange of both data;
The address definition of RAM#1
1.1.1RAM2_state (stone read/write, soft core read/write)
RAM2_state: be divided into three states 0,1,2,3. 0: soft core is idle; 1: stone is writing RAM#2; 2: stone writes RAM#2; 3: soft core is reading RAM#2;
When stone 200ms send cycle time to time, RAM2_state unequal to 3 detected, so that it may to write in RAM2
Data, are set to 1 RAM2_state before writing; RAM2_state value 2 after all writing;
RAM2_state is read in the circulation of soft core, if RAM2_state is 2; Then start to read the data in RAM#2; Before reading, RAM2_state is set to 3; After all having read, RAM2_state is set to 0;
Soft core can by judging whether RAM2_state state can become 2 from state 0, and whether the communication of judging is interrupted;
Stone can by judging whether RAM2_state state can become 0 from state 2, and whether the communication of judging is interrupted;
1.1.2RAM2_ID (stone is read, and soft core is write)
It it is certain value from module I D inside RAM2_ID;
Need, before stone writes data in RAM#2, the value judging RAM2_ID;
1.1.3RAM3_W_ord (stone is read, soft core read/write) and RAM3_R_ord (stone read/write, soft core is read) RAM3_W_ord, RAM3_R_ord scope is exactly RAM#3 buffer size (0��31);
RAM3_W_ord: order write pointer;
RAM3_R_ord: order read pointer; Skew amount: 0x300;
Embody rule (RAM3_W_ord, RAM3_R_ord):
1. note can when display issue one order time
Whether 2. judge that the scope of RAM3_W_ord is between (0��31), if not being, RAM3_W_ord=0; RAM3_R_ord=0;
3., in order write RAM3_W_ord+0x300 address, allowing RAM3_W_ord point to next region;
�� reads order:
(1) RAM3_W_ord, RAM3_R_ord are read in stone circulation;
(2) if their scope is not between (0��31), RAM3_W_ord=0; RAM3_R_ord=0;
(3) if RAM3_W_ord is unequal to RAM3_R_ord; Then read the order in RAM3_R_ord+0x300, and perform; RAM3_R_ord is allowed to point to next region;
1.1.4RAM4_ord, RAM4_ID, RAM4_addr, RAM4_ENOB,
RAM4_ord is respectively three states 0,1,2,3; 0: idle; 1: soft core application mainboard parameter; 2: mainboard parameter is uploaded complete, soft core can read;3: soft core amendment parameter, waits mainboard amendment;
RAM4_ID: the ID (according to practical situation definition) of module
RAM4_addr: the address of the data of transmission, refers to parameter list
RAM4_ENOB: valid data position (000000000)2��(111111111)2; The number that soft core is caught, when only the valid data position of data is 1, stone could revise this parameter;
�� reads parameter:
(1) soft core needs to read certain page of data;
(2) soft core is RAM4_ID writing module ID;
(3) soft core transmits RAM4_addr write the data address of page;
(4) RAM4_ord=1;
(5) represent that soft core needs read module ID to be RAM4_ID; Data address is the data of RAM4_addr;
(6) stone gets out data and is written to 0x340��0x342 region; And RAM4_ord=0x02;
(7) if RAM4_ord RAM4_ord==0x02 is read in the circulation of soft core; Then start to read the content in 0x340��0x342 region, it is shown to interface; After reading, RAM4_ord==0;
�� write parameters:
(1) when man-machine interface sends amendment parameter order;
(2) soft core value is put into 0x343��0x345 region (nine data altogether: parameter 1��parameter 9) the data needing amendment,
(3) (parameter 3 is such as only revised needing to revise the corresponding position 1 in RAM4_ENOB of parameter; So RAM4_ENOB=(000000100) 2; If parameter is all revised, so RAM4_ENOB=(111111111) 2
(4) RAM4_ID and RAM4_addr puts into equipment I D and the data-addresses of data respectively
(5) RAM4_ord=0x03; Represent that write parameters sends
(6) RAM4_ord is read in stone circulation, if RAM4_ord==0x03, situation according to RAM4_ENOB set, so the parameter read-in in 0x343��0x345 region to the storage space of oneself corresponding to RAM4_ID and RAM4_addr, last RAM4_ord=0;
And RAM5_R_err 1.1.5RAM5_W_err
RAM5_W_err, RAM5_R_err: scope is exactly RAM#5 buffer size (0��31);
RAM5_W_err: write fault pointer; RAM5_R_err: Read fault pointer; Skew amount: 0x3e0;
Embody rule:
�� writes fault:
(1) when a fault occurs stone
(2) stone judges that the scope of RAM5_W_err is between (0��31), if not being, and RAM5_W_err=0; RAM5_R_err=0;
(3) failure message is write in the address of RAM5_W_err+0x3e0 and (also need to write the data in record ripple region); RAM5_W_err points to next address;
�� Read fault
(1) RAM5_W_err, RAM5_R_err are read in the circulation of soft core
(2) if their scope is RAM5_W_err=0 between (0��31); RAM5_R_err=0;
(3) if RAM5_W_err is unequal to RAM5_R_err, then read the fault code in RAM5_R_err and preserve record (also needing to have read the data in record ripple region); RAM5_R_err is allowed to point to next region;
1.1.6RAM6_re
RAM6_re has three states 0,1 respectively;
0: there is no new recorder data; 1: have new recorder data
Write record ripple: when master control generation fault, in RAM#5 after Write fault information, if there being fault waveform to need record, it is necessary to fault waveform is recorded to RAM#6 region;
After fault waveform writes, RAM6_re state is put 1; Then pointer RAM5_W_err is upgraded;
Read record ripple: soft core reads fault pointer RAM5_W_err, RAM5_R_err and finds that master control has new fault, then read fault according to pointer, then reading RAM6_re, if being 1, then starting to read the recorder data in RAM#6;After having read, RAM6_re resets, and then upgrades pointer RAM5_R_err;
If there is the same moment, many faults occur, after soft core reads first fault and fault waveform, RAM6_re can be reset; Follow-up fault is defaulted as does not have failure wave-recording, if needing to check waveform, with reference to the waveform of first fault;
(fault can be judged by the fault-time on display screen simultaneously)
1. opening the region RAM#2 of a blocks of data state in dual port RAM, mainly stone gathers the data to be transmitted, and is written in relevant RAM#2, and the mark state in set RAM#1; Soft core reads the data in RAM#2 according to the state in RAM#1, and processes this data;
The address definition of RAM#2
2. opening the region RAM#3 of a blocks of data state in dual port RAM, mainly soft core writes order in RAM#3, and the mark state in set RAM#1; Stone reads the order in RAM#3 according to the state in RAM#1, and performs;
RAM#3 data define
3. in dual port RAM, open the region RAM#4,1 of a blocks of data state) mainly soft core is in parameter read-in RAM#4, and the mark state in set RAM#1; Stone reads the parameter in RAM#4 according to the state in RAM#1, and revises parameter; 2) mainly stone in parameter read-in RAM#4, and the mark state in set RAM#1; Soft core reads the parameter in RAM#4 according to the state in RAM#1, checks that whether this parameter is correct, reliably;
RAM#4 data define
4. opening the region RAM#5 of a blocks of data state in dual port RAM, mainly stone writes failure message in RAM#5, and the mark state in set RAM#1; Soft core reads the fault code in RAM#5 according to the state in RAM#1 and stores display;
RAM#5 data define
5. in dual port RAM, open the region RAM#6 of a blocks of data state, in waveform information write RAM#6 when mainly fault occurs stone, and the mark state in set RAM#1; Soft core reads the fault code in RAM#6 according to the state in RAM#1 and stores display;
RAM#6 data define
Claims (1)
1. the method communicated with soft core based on the inner stone of FPGA of dual port RAM, is characterized in that: open up data state region RAM#1, data state region RAM#2, data state region RAM#3, data state region RAM#4, data state region RAM#5 and data state region RAM#6 in dual port RAM;
Described RAM#1 is for describing the read-write state of electric parameters, parameter, order data; Stone, soft core control the exchange of both data by reading these read-write states alternately;
The data that described RAM#2 collects for writing stone in RAM#1, when stone writes data in relevant RAM#2, and after mark state in set RAM#1, soft core reads the data in RAM#2 according to the state in RAM#1, and processes this data;
Described RAM#3 is for writing the order of soft core, and the mark state in set RAM#1; Stone reads the order in RAM#3 according to the state in RAM#1, and performs;
Described RAM#4, for the amendment of soft core stone information; 1) soft core is in parameter read-in RAM#4, and the mark state in set RAM#1; Stone reads the parameter in RAM#4 according to the state in RAM#1, and revises parameter; 2) stone is in parameter read-in RAM#4, and the mark state in set RAM#1; Soft core reads the parameter in RAM#4 according to the state in RAM#1, checks that whether this parameter is correct, reliably;
Described RAM#5, for writing the failure message of stone, and the mark state in set RAM#1; Soft core reads the fault code in RAM#5 according to the state in RAM#1 and stores display;
Described RAM#6, for writing waveform information when stone fault occurs, and the mark state in set RAM#1; Soft core reads the fault code in RAM#6 according to the state in RAM#1 and stores display.
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| CN201510974101.3A CN105653477A (en) | 2015-12-21 | 2015-12-21 | Double-port RAM-based method for communication of hard core and soft core in FPGA |
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| CN201510974101.3A CN105653477A (en) | 2015-12-21 | 2015-12-21 | Double-port RAM-based method for communication of hard core and soft core in FPGA |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022001063A1 (en) * | 2020-07-01 | 2022-01-06 | 无锡中微亿芯有限公司 | Fpga apparatus for realizing function of extending transmission bandwidth of network-on-chip |
| US11750510B2 (en) | 2020-07-01 | 2023-09-05 | Wuxi Esiontech Co., Ltd. | FPGA device for implementing expansion of transmission bandwidth of network-on-chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201075248Y (en) * | 2007-08-27 | 2008-06-18 | 中国石油天然气集团公司 | USB interface real-time data acquisition controller |
| CN101655824A (en) * | 2009-08-25 | 2010-02-24 | 北京广利核系统工程有限公司 | Implementation method of double-port RAM mutual exclusion access |
-
2015
- 2015-12-21 CN CN201510974101.3A patent/CN105653477A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201075248Y (en) * | 2007-08-27 | 2008-06-18 | 中国石油天然气集团公司 | USB interface real-time data acquisition controller |
| CN101655824A (en) * | 2009-08-25 | 2010-02-24 | 北京广利核系统工程有限公司 | Implementation method of double-port RAM mutual exclusion access |
Non-Patent Citations (1)
| Title |
|---|
| 曹玉华等: "基于FPGA的双口RAM在PC104与DSP通信中的研究与应用", 《PLC&FA》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022001063A1 (en) * | 2020-07-01 | 2022-01-06 | 无锡中微亿芯有限公司 | Fpga apparatus for realizing function of extending transmission bandwidth of network-on-chip |
| US11750510B2 (en) | 2020-07-01 | 2023-09-05 | Wuxi Esiontech Co., Ltd. | FPGA device for implementing expansion of transmission bandwidth of network-on-chip |
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Application publication date: 20160608 |