CN105653240A - Multiplying unit used for RFID (Radio Frequency Identification) security chip, and implementation method - Google Patents
Multiplying unit used for RFID (Radio Frequency Identification) security chip, and implementation method Download PDFInfo
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- CN105653240A CN105653240A CN201511019257.2A CN201511019257A CN105653240A CN 105653240 A CN105653240 A CN 105653240A CN 201511019257 A CN201511019257 A CN 201511019257A CN 105653240 A CN105653240 A CN 105653240A
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- partial product
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
- G06F7/5045—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other for multiple operands
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
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- General Physics & Mathematics (AREA)
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- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The embodiment of the invention discloses a multiplying unit used for a RFID (Radio Frequency Identification) security chip, and an implementation method. The multiplying unit comprises a partial product generation circuit, a compression circuit and a carry-propagate adder, wherein the partial product generation circuit is used for generating a partial product and inputting the partial product into the compression circuit; the compression circuit is used for receiving the partial product generated by the partial product generation circuit, carrying out compression processing on the partial product to obtain a compressed temporary variable and inputting the temporary variable into the carry-propagate adder; and the carry-propagate adder carries out the compression processing on the temporary variable and obtaining a multiplication result. In the embodiment of the invention, a compact tree is mixed to reduce a summation series in a tree structure, a multiplying unit compact tree key path can be reduced, circuit time delay is shortened, the operation speed of the security chip is improved, the multiplying unit is suitable to be integrated into the RSA (Rivest, Shamir and Adleman) or ECC (Elliptic Curves Cryptography) coprocessor of an intelligent card chip to improve the working speed of the coprocessor.
Description
Technical field
The present invention relates to digital signal processing technique field, particularly relate to a kind of multiplier for RFID security chip and realize method.
Background technology
Public-key cryptosystem solves the safety problem such as key updating and cipher key delivery in DSE arithmetic, is therefore able to be widely used at information security field, with the confidentiality of guarantee information transmission, integrity and to the signature between communicating pair and checking. RSA Algorithm and elliptic curve cryptosystem ECC are widely used in confidence security industry due to the safety of algorithm and the stability of realization. The mode of RSA and the most hardware co-processor of ECC algorithm realizes, and is integrated in the safety chip such as smart card, U-shield. Hardware realizes RSA and ECC to be needed to solve quickly to realize this key issue of large module multiplication. Complicated modular multiplication is converted to simple home textile and shift operation by Montgomery algorithm, thus is particularly suitable for hardware and realizes. And the core of montgomery modulo multiplication is in that high-speed parallel Multiplier Design.
Parallel multiplier is mainly made up of three parts: (1) partial product produces circuit; (2) Partial product compression tree; (3) final carry propagation adder. The Partial products compressor adopting Wallace tree structure adopts the mode of Carry save array to compress, and partial product produces partial product Fast Compression produced by circuit and becomes 2 partial products. Traditional Wallace's compressed tree is made up of 3-2 compressor or 4-2 compressor, when partial product quantity is more, the advantage of such compressed tree framework is restricted, there is the problem that combination logic critical path is longer and time delay is bigger, thus the safety chip operating rate caused is difficult to continue to lift up.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, the invention provides a kind of for RF identification (RadioFrequencyIdentification, RFID) multiplier of safety chip and realize method, multiplier compressed tree critical path and time delay can be reduced, improve the speed of service of safety chip.
In order to solve the problems referred to above, the present invention proposes a kind of multiplier for RFID security chip, and described multiplier includes:
Partial product produces circuit, amasss for generating section, and described partial product is input to compressor circuit;
Compressor circuit, is used for receiving partial product and produces partial product produced by circuit, Partial product compression is processed the temporary variable after obtaining compression, and temporary variable is input to carry propagation adder;
Carry propagation adder, for being compressed described temporary variable processing, and obtains multiplication result.
Preferably, described compressor circuit includes:
First order compressor circuit, is used for receiving described partial product and produces partial product produced by circuit, and be compressed described partial product processing, it is thus achieved that the first temporary variable, and described first temporary variable is input to second level compressor circuit;
Second level compressor circuit; For receiving described first temporary variable, and it is compressed described first temporary variable processing, it is thus achieved that the second temporary variable, and described second temporary variable is input to third level compressor circuit;
Third level compressor circuit, is used for receiving described second temporary variable, and is compressed described second temporary variable processing, it is thus achieved that the 3rd temporary variable, and described 3rd temporary variable is input to fourth stage compressor circuit;
Fourth stage compressor circuit, is used for receiving described 3rd temporary variable, and is compressed described 3rd temporary variable processing, it is thus achieved that intermediate data, and described intermediate data is input to described carry propagation adder.
Preferably, described partial product produces circuit and is used for producing 36 item parts and amasss.
Preferably, described first order compressor circuit is made up of 9 4-2 compressoies, shortens 18 temporary variables into for described 36 item parts being overstock, and 18 temporary variables are input to second level compressor circuit.
Preferably, described second level compressor circuit is made up of 4 4-2 compressoies, it is compressed into 8 temporary variables for 16 temporary variables in 18 temporary variables being compressed into by described first order compressor circuit, and 8 temporary variables are input to third level compressor circuit.
Preferably, described third level compressor circuit is made up of 2 5-2 compressoies, it is compressed into 4 temporary variables for 2 temporary variables remaining in 18 temporary variables that 8 temporary variables being compressed into by described second level compressor circuit and described first order compressor circuit are compressed into, and 4 temporary variables are input to fourth stage compressor circuit.
Preferably, described fourth stage compressor circuit is made up of 1 4-2 compressor, is compressed into 2 intermediate data for 4 temporary variables being compressed into by described third level compressor circuit, and 2 intermediate data are input to described carry propagation adder.
Correspondingly, the present invention also provides for a kind of method that realizes of multiplier for RFID security chip, and described method includes:
Generating section is amassed, and described partial product is input to compressor circuit;
Described compressor circuit receives partial product and produces partial product produced by circuit, Partial product compression is processed the temporary variable after obtaining compression, and temporary variable is input to carry propagation adder;
Described temporary variable is compressed processing by described carry propagation adder, and obtains multiplication result.
Preferably, described compressor circuit receives partial product and produces partial product produced by circuit, and Partial product compression is processed the temporary variable after obtaining compression, and the step that temporary variable is input to carry propagation adder includes:
First order compressor circuit receives described partial product and produces partial product produced by circuit, and is compressed described partial product processing, it is thus achieved that the first temporary variable, and described first temporary variable is input to second level compressor circuit;
Described second level compressor circuit receives described first temporary variable, and is compressed described first temporary variable processing, it is thus achieved that the second temporary variable, and described second temporary variable is input to third level compressor circuit;
Described third level compressor circuit receives described second temporary variable, and is compressed described second temporary variable processing, it is thus achieved that the 3rd temporary variable, and described 3rd temporary variable is input to fourth stage compressor circuit;
Described fourth stage compressor circuit receives described 3rd temporary variable, and is compressed described 3rd temporary variable processing, it is thus achieved that intermediate data, and described intermediate data is input to described carry propagation adder.
In embodiments of the present invention, the summation progression in tree is reduced by mixing compressed tree, multiplier compressed tree critical path can be reduced, reduce circuit delay, improve the speed of service of safety chip, it is suitable for being integrated in RSA or the ECC coprocessor of intelligent card chip, to improve the operating rate of coprocessor.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structure composition schematic diagram of the multiplier for RFID security chip of the embodiment of the present invention;
Fig. 2 is the structure composition schematic diagram of another embodiment of the multiplier for RFID security chip of the present invention;
Fig. 3 is the configuration diagram of the mixed type compressed tree of multiplier in the embodiment of the present invention;
Fig. 4 is the configuration diagram of the multiplier of embedded compressed tree in the embodiment of the present invention;
Fig. 5 is the schematic flow sheet realizing method of the multiplier for RFID security chip of the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments. Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
Fig. 1 is the structure composition schematic diagram of the multiplier for RFID security chip of the embodiment of the present invention, as it is shown in figure 1, this multiplier includes:
Partial product produces circuit 1, amasss for generating section, and partial product is input to compressor circuit;
Compressor circuit 2, is used for receiving partial product and produces partial product produced by circuit 1, Partial product compression is processed the temporary variable after obtaining compression, and temporary variable is input to carry propagation adder 3;
Carry propagation adder 3, for being compressed temporary variable processing, and obtains multiplication result.
Fig. 2 illustrates the structure composition of another embodiment of the multiplier of the present invention, as in figure 2 it is shown, compressor circuit 2 farther includes:
First order compressor circuit 20, is used for receiving partial product and produces partial product produced by circuit, and be compressed partial product processing, it is thus achieved that the first temporary variable, and the first temporary variable is input to second level compressor circuit 21;
Second level compressor circuit 21;For receiving the first temporary variable, and it is compressed the first temporary variable processing, it is thus achieved that the second temporary variable, and the second temporary variable is input to third level compressor circuit 22;
Third level compressor circuit 22, is used for receiving the second temporary variable, and is compressed the second temporary variable processing, it is thus achieved that the 3rd temporary variable, and the 3rd temporary variable is input to fourth stage compressor circuit 23;
Fourth stage compressor circuit 23, is used for receiving the 3rd temporary variable, and is compressed the 3rd temporary variable processing, it is thus achieved that intermediate data, and intermediate data is input to carry propagation adder 3.
Below in conjunction with Fig. 3, Fig. 4, the multiplier of the embodiment of the present invention is further described.
The framework of the mixed type compressed tree in multiplier is as shown in Figure 2, this compressed tree is made up of the mixing of 4-2 and 5-2 compressor, one has 4 grades of compressor circuits, 1st, 2,4 grades of compressor circuits are made up of 4-2 compressor, and 3rd level compressor circuit is then made up of 5-2 compressor, and the main purpose of this mixed design is in that to reduce the critical path of compressed tree. 4-2 compressor has 2 grades of full adder time delays, and its function is to overstock 4 item parts to shorten 2 temporary variables into. And 5-2 compressor has 3 grades of full adder time delays, its function is to say that 5 item parts overstock to shorten 3 temporary variables into. Its input of compressed tree is produced 36 item parts by the partial product generation circuit coming from parallel multiplier and is amassed, and outfan is 2 result C and S after compression, and exports in the carry propagation adder of next stage.
In being embodied as, first order compressor circuit 20 is made up of 9 4-2 compressoies, shortens 18 temporary variables into for 36 item parts being overstock, and 18 temporary variables are input to second level compressor circuit 21.
Second level compressor circuit 21 is made up of 4 4-2 compressoies, and 16 temporary variables being used in 18 temporary variables being compressed into by first order compressor circuit 20 are compressed into 8 temporary variables, and 8 temporary variables are input to third level compressor circuit 22.
Third level compressor circuit 22 is made up of 2 5-2 compressoies, it is compressed into 4 temporary variables for 2 temporary variables remaining in 18 temporary variables that 8 temporary variables being compressed into by second level compressor circuit 21 and first order compressor circuit are compressed into, and 4 temporary variables are input to fourth stage compressor circuit 23.
Fourth stage compressor circuit 23 is made up of 1 4-2 compressor, is compressed into 2 intermediate data for 4 temporary variables being compressed into by third level compressor circuit 22, and 2 intermediate data are input to carry propagation adder 3.
Multiplier is broadly divided into serial and concurrent multiplier computing mode. The generation of serial multiplier partial product and cumulative be all perform in order, it is less to consume resource, is suitable for chip area is required higher occasion. Parallel arithmetic mode exchanges speed for area, adopts a large amount of arithmetic unit to produce partial product and add up to carry out simultaneously, and this mode is generally used in the design of high-performance multiplier architecture. The method improving multiplier computation speed is to utilize tree to reduce summation progression, and wherein Wallace tree is wherein foremost one, and it is particularly suitable in the Multiplier Design of more than 16.
Present invention is mainly used for being integrated in high speed multiplier, generally as shown in Figure 4. The major function of this multiplier is carried out multiplying: P=X*Y. It is mainly by booth encoder, Booth decoder, mixed type compression and final carry propagation adder composition.
The basic functional principle of parallel multiplier can describe as follows.First multiplier X is carried out Booth coding according to Booth encryption algorithm by booth encoder, and then Booth selector will select Booth to encode according to multiplicand Y and produce the long-pending output of 36 item parts. 36 item parts are then overstock two intermediate data C and S in contracting by mixed type compressed tree proposed by the invention, and the compressed tree of the present invention reduces critical path time delay thus improve the overall operation speed of multiplier. Intermediate data C and S produced by compressor is then compressed into final multiplication result output P by last carry propagation adder. The partial product of this structure multiplier produces circuit and have employed Booth coding structure, the half that partial product number is conventional multiplier of its generation. Have employed mixed type Wallace's compressed tree structure in the Partial product compression stage, produced partial product is carried out fast parallel compression process, effectively improves the speed of Partial product compression. On circuit structure, partial product produces and Partial product compression adopts structure of rehearsing parallel, greatly improves the speed that partial product produces.
Correspondingly, what the embodiment of the present invention also provided for a kind of multiplier for RFID security chip realizes method, as it is shown in figure 5, the method includes:
S51, generating section is amassed, and partial product is input to compressor circuit;
S52, compressor circuit receives partial product and produces partial product produced by circuit, Partial product compression is processed the temporary variable after obtaining compression, and temporary variable is input to carry propagation adder;
S53, temporary variable is compressed processing by carry propagation adder, and obtains multiplication result.
Further, S52 includes:
First order compressor circuit receives partial product and produces partial product produced by circuit, and is compressed partial product processing, it is thus achieved that the first temporary variable, and the first temporary variable is input to second level compressor circuit;
Second level compressor circuit receives the first temporary variable, and is compressed the first temporary variable processing, it is thus achieved that the second temporary variable, and the second temporary variable is input to third level compressor circuit;
Third level compressor circuit receives the second temporary variable, and is compressed the second temporary variable processing, it is thus achieved that the 3rd temporary variable, and the 3rd temporary variable is input to fourth stage compressor circuit;
Fourth stage compressor circuit receives the 3rd temporary variable, and is compressed the 3rd temporary variable processing, it is thus achieved that intermediate data, and intermediate data is input to carry propagation adder.
First order compressor circuit is made up of 9 4-2 compressoies, partial product produces 36 item parts produced by circuit and overstocks and shorten 18 temporary variables into, and 18 temporary variables are input to second level compressor circuit.
Second level compressor circuit is made up of 4 4-2 compressoies, and 16 temporary variables in 18 temporary variables being compressed into by first order compressor circuit are compressed into 8 temporary variables, and 8 temporary variables are input to third level compressor circuit.
Third level compressor circuit is made up of 2 5-2 compressoies, in 18 temporary variables that 8 temporary variables being compressed into by second level compressor circuit and first order compressor circuit are compressed into, remaining 2 temporary variables are compressed into 4 temporary variables, and 4 temporary variables are input to fourth stage compressor circuit.
Fourth stage compressor circuit is made up of 1 4-2 compressor, and 4 temporary variables being compressed into by third level compressor circuit are compressed into 2 intermediate data, and 2 intermediate data are input to carry propagation adder 3.
Flow processing in the inventive method embodiment referring to the function of functional module each in embodiments of the invention, can repeat no more here.
In embodiments of the present invention, the summation progression in tree is reduced by mixing compressed tree, multiplier compressed tree critical path can be reduced, reduce circuit delay, improve the speed of service of safety chip, it is suitable for being integrated in RSA or the ECC coprocessor of intelligent card chip, to improve the operating rate of coprocessor.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment can be by the hardware that program carrys out instruction relevant and completes, this program can be stored in a computer-readable recording medium, storage medium may include that read only memory (ROM, ReadOnlyMemory), random access memory (RAM, RandomAccessMemory), disk or CD etc.
Additionally, the multiplier for RFID security chip and the method that realizes that above the embodiment of the present invention are provided are described in detail, principles of the invention and embodiment are set forth by specific case used herein, and the explanation of above example is only intended to help to understand method and the core concept thereof of the present invention; Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, all will change in specific embodiments and applications, in sum, this specification content should not be construed as limitation of the present invention.
Claims (9)
1. the multiplier for RFID security chip, it is characterised in that described multiplier includes:
Partial product produces circuit, amasss for generating section, and described partial product is input to compressor circuit;
Compressor circuit, is used for receiving partial product and produces partial product produced by circuit, Partial product compression is processed the temporary variable after obtaining compression, and temporary variable is input to carry propagation adder;
Carry propagation adder, for being compressed described temporary variable processing, and obtains multiplication result.
2. the multiplier for RFID security chip as claimed in claim 1, it is characterised in that described compressor circuit includes:
First order compressor circuit, is used for receiving described partial product and produces partial product produced by circuit, and be compressed described partial product processing, it is thus achieved that the first temporary variable, and described first temporary variable is input to second level compressor circuit;
Second level compressor circuit; For receiving described first temporary variable, and it is compressed described first temporary variable processing, it is thus achieved that the second temporary variable, and described second temporary variable is input to third level compressor circuit;
Third level compressor circuit, is used for receiving described second temporary variable, and is compressed described second temporary variable processing, it is thus achieved that the 3rd temporary variable, and described 3rd temporary variable is input to fourth stage compressor circuit;
Fourth stage compressor circuit, is used for receiving described 3rd temporary variable, and is compressed described 3rd temporary variable processing, it is thus achieved that intermediate data, and described intermediate data is input to described carry propagation adder.
3. the multiplier for RFID security chip as claimed in claim 1 or 2, it is characterised in that described partial product generation circuit is used for producing 36 item parts and amasss.
4. the multiplier for RFID security chip as claimed in claim 3, it is characterized in that, described first order compressor circuit is made up of 9 4-2 compressoies, shortens 18 temporary variables into for described 36 item parts being overstock, and 18 temporary variables are input to second level compressor circuit.
5. the multiplier for RFID security chip as claimed in claim 4, it is characterized in that, described second level compressor circuit is made up of 4 4-2 compressoies, it is compressed into 8 temporary variables for 16 temporary variables in 18 temporary variables being compressed into by described first order compressor circuit, and 8 temporary variables are input to third level compressor circuit.
6. the multiplier for RFID security chip as claimed in claim 5, it is characterized in that, described third level compressor circuit is made up of 2 5-2 compressoies, it is compressed into 4 temporary variables for 2 temporary variables remaining in 18 temporary variables that 8 temporary variables being compressed into by described second level compressor circuit and described first order compressor circuit are compressed into, and 4 temporary variables are input to fourth stage compressor circuit.
7. the multiplier for RFID security chip as claimed in claim 6, it is characterized in that, described fourth stage compressor circuit is made up of 1 4-2 compressor, 4 temporary variables for being compressed into by described third level compressor circuit are compressed into 2 intermediate data, and 2 intermediate data are input to described carry propagation adder.
8. one kind for RFID security chip multiplier realize method, it is characterised in that described method includes:
Generating section is amassed, and described partial product is input to compressor circuit;
Described compressor circuit receives partial product and produces partial product produced by circuit, Partial product compression is processed the temporary variable after obtaining compression, and temporary variable is input to carry propagation adder;
Described temporary variable is compressed processing by described carry propagation adder, and obtains multiplication result.
9. what be used for RFID security chip as claimed in claim 8 realizes method, it is characterized in that, described compressor circuit receives partial product and produces partial product produced by circuit, Partial product compression is processed the temporary variable after obtaining compression, and the step that temporary variable is input to carry propagation adder includes:
First order compressor circuit receives described partial product and produces partial product produced by circuit, and is compressed described partial product processing, it is thus achieved that the first temporary variable, and described first temporary variable is input to second level compressor circuit;
Described second level compressor circuit receives described first temporary variable, and is compressed described first temporary variable processing, it is thus achieved that the second temporary variable, and described second temporary variable is input to third level compressor circuit;
Described third level compressor circuit receives described second temporary variable, and is compressed described second temporary variable processing, it is thus achieved that the 3rd temporary variable, and described 3rd temporary variable is input to fourth stage compressor circuit;
Described fourth stage compressor circuit receives described 3rd temporary variable, and is compressed described 3rd temporary variable processing, it is thus achieved that intermediate data, and described intermediate data is input to described carry propagation adder.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511019257.2A CN105653240A (en) | 2015-12-30 | 2015-12-30 | Multiplying unit used for RFID (Radio Frequency Identification) security chip, and implementation method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511019257.2A CN105653240A (en) | 2015-12-30 | 2015-12-30 | Multiplying unit used for RFID (Radio Frequency Identification) security chip, and implementation method |
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| CN105653240A true CN105653240A (en) | 2016-06-08 |
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| CN1556467A (en) * | 2004-01-09 | 2004-12-22 | 上海汉芯半导体科技有限公司 | Digital signal processor using mixed compression two stage flow multiplicaton addition unit |
| US7958180B2 (en) * | 2007-07-05 | 2011-06-07 | International Business Machines Corporation | Multiplier engine |
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| CN102722352A (en) * | 2012-05-21 | 2012-10-10 | 华南理工大学 | Booth multiplier |
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Application publication date: 20160608 |