CN105634892B - A kind of axial flow blower communication data packets accuracy control method - Google Patents
A kind of axial flow blower communication data packets accuracy control method Download PDFInfo
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Abstract
The invention belongs to axial flow blower control technologies, are related to a kind of axial flow blower communication data packets accuracy control method.The scheme that the present invention takes is：Microprocessor first makes bus communication chip be in the state for sending enabled and reception and forbidding by control bus communication chip；Then the establishment of transmission data packet is completed, and writes the data to transmission array, then the transmission buffer register completion transmission of microprocessor is written；Microprocessor makes bus communication chip be in the state for sending and forbidding and receive and enabling；Microprocessor receive host computer send data to microprocessor reception buffer register and be stored in reception array, if packet header and check code are all correct, then it is assumed that data packet is correct, otherwise just loses data packet.The present invention efficiently solve axial flow blower control system data packet send and receive between collision problem, and realize reliable reception and the transmission of microprocessor data packet, improve the reliability of system control.
Description
Technical field
The invention belongs to axial flow blower control technologies, are related to a kind of axial flow blower communication data packets accuracy control method.
Background technique
Axial flow blower is widely used in power system industry, in high-power transformer, have more axial flow blowers be transformer into
Row wind-cooling heat dissipating carries out instruction control to blower by bus using host computer and real time monitoring has a very important role,
Loss caused by when failure occurs can be reduced to the maximum extent in this way, while operator can be allowed far from the severe of strong noise again
Industrial environment, conventional axial flow blower mostly uses 485 buses of two-wire system to be controlled, and sending and receiving all is by two radicals
It is carried out according to transmission line, therefore often because the conflict between sending and receiving leads to data transmission fails, in some instances it may even be possible to go out
The instruction of existing mistake leads to system malfunction, causes serious accident.Therefore, the present invention communicates number using a kind of axial flow blower
According to packet accuracy control method, the real-time Transmission of data is realized, while avoiding the conflict sent and received in same bus,
When environment interferes communication signal and signal is caused deviation occur during transmission link, mistake can be effectively removed
Data packet accidentally, improves the safety of system.
Summary of the invention
The purpose of the present invention is：It is proposed a kind of axial flow blower communication data packets accuracy control method.
The technical scheme is that：A kind of axial flow blower communication data packets accuracy control method, which is characterized in that the party
Method takes following steps in the environment of axial flow blower and its corresponding controllers, the hardware fault-free of host computer：
Step 1: microprocessor sends high level to reception/transmission control signal of bus communication chip, so that bus is logical
News chip is in the state that enabled and reception is forbidden that sends；
Step 2: the packet header 0x7E of data packet write-in is sent the 1st byte of array by microprocessor, then by data packet
0x7E write-in in packet header sends the 2nd byte of array；
Step 3: microprocessor by the valid data that axial flow blower host computer needs be respectively written into send array the 3rd, 4,
5,6 bytes；
Step 4: the number -4 of valid data byte is assigned to the 7th byte for sending array by microprocessor；
Step 5: microprocessor will send the 3rd, 4,5, the 6 byte summation of array, and by a minimum word for resulting value
Section is assigned to the 8th byte for sending array；
Step 6: the 1st byte for sending array is assigned to the transmission buffer register of microprocessor by microprocessor；
Step 7: whether the transmission buffer register of microprocessor inquiry microprocessor is completed to send, carried out if completing
In next step, it if not completing, waits always；
Step 8: the 2nd byte for sending array is assigned to the transmission buffer register of microprocessor by microprocessor, so
After execute step 7；And by same step successively the 3rd to the 8th byte of assignment to microprocessor transmission buffer register, directly
It is sent to all bytes；
Step 9: microprocessor sends low level to reception/transmission control signal of bus communication chip, so that bus is logical
News chip, which is in send, forbids and receives enabled state；
Step 10: microprocessor receives the data of host computer transmission to the reception buffer register of microprocessor, then will
Its assignment is in the 1st byte for receiving array；
Step 11：Microprocessor judges whether the 1st byte for receiving array is equal to packet header as defined in communications protocol
0x7E comes back for step 10 if unequal, if equal, carries out step 12；
Step 12：Microprocessor receive host computer send data to microprocessor reception buffer register, then
By its assignment in the 2nd byte for receiving array；
Step 13：Microprocessor judges whether the 2nd byte for receiving array is equal to packet header as defined in communications protocol
0x7E comes back for step 10 if unequal, if equal, same steps is taken successively to receive host computer transmission
Data to microprocessor reception buffer register, and by its assignment in receive array the 3rd to the 7th byte；
Step 14：Microprocessor judges whether the value for receiving the 6th byte of array is equal to the word for receiving valid data
Save number -3；If equal, step 15 is carried out, ten are returned to step if unequal；
Step 15：Microprocessor will receive the 3rd byte, the 4th byte, the 5th byte summation of array, and judge
Whether a minimum byte for resulting value is equal with the 7th byte of array is received, if equal, step 10 six is carried out, if not
It is equal, return to step ten；
Step 10 six：Microprocessor will receive the 3rd byte of array, the 4th byte, the 5th byte difference assignment in
Corresponding control instruction；
Step 10 seven：Return to step one.
2, axial flow blower communication data packets accuracy control method as described in claim 1, which is characterized in that step 10 six
The control instruction is starting/stopping order, forward/reverse order, closed loop/open loop order, respectively with receive the of array
3, the 4th, the 5th byte is corresponding.
It is an advantage of the invention that：The present invention uses a kind of axial flow blower communication data packets accuracy control method, realizes number
According to real-time Transmission, while the conflict sent and received in same bus is avoided, when environment interferes communication signal
And when signal being caused deviation occur during transmission link, the data packet of mistake can be effectively removed, the peace of system is improved
Quan Xing.
Detailed description of the invention
Fig. 1 is a kind of axial flow blower communication data packets accuracy control method flow chart.
Specific embodiment
It elaborates below to the present invention, a kind of axial flow blower communication data packets accuracy control method, this method
In the environment of axial flow blower and its corresponding controllers, the hardware fault-free of host computer, referring to Fig. 1, following steps are specifically taken：
Step 1: digital signal processor TMS320F2812 to bus communication electrical level transferring chip ISO3082 reception/
It sends selection port and sends high level, transmission is enabled and reception is forbidden so that bus communication electrical level transferring chip ISO3082 is in
State；
Step 2: the packet header 0x7E write-in of data packet is sent the 1st of array by digital signal processor TMS320F2812
Byte, then the packet header 0x7E of data packet is written to the 2nd byte for sending array；
Step 3: digital signal processor TMS320F2812 writes the valid data that axial flow blower host computer needs respectively
Enter to send the 3rd, 4,5,6 byte of array, wherein the 3rd byte represents the high byte of the real-time tachometer value of motor, be worth for 0xCE,
4th byte represents the low byte of the real-time tachometer value of motor, is worth for 0x1F, and the 5th byte represents the height of motor bus current value
Byte, is worth for 0xA1, and the 6th byte represents the low byte of motor bus current value, be worth for 0x9D；
Step 4: the valid data byte that digital signal processor TMS320F2812 needs axial flow blower host computer
Number -4 is assigned to the 7th byte for sending array；
Step 5: digital signal processor TMS320F2812 sums the 3rd, 4,5,6 byte for sending array, i.e., will
0xCE, 0x1F, 0xA1,0x9D summation, and a minimum byte 0x22 of resulting value 0x022B is assigned to and sends the 8th of array
A byte；
Step 6: the 1st byte for sending array is assigned at digital signal by digital signal processor TMS320F2812
Manage the transmission buffer register of device TMS320F2812；
Step 7: the transmission of digital signal processor TMS320F2812 enquiring digital signal processor TMS320F2812 is slow
It rushes whether register is completed to send, carries out in next step, if not completing, waiting always if completing；
Step 8: the 2nd byte for sending array is assigned at digital signal by digital signal processor TMS320F2812
The transmission buffer register for managing device TMS320F2812, then executes step 7；And press same step successively assignment the 3rd to the 8th
Byte to digital signal processor TMS320F2812 transmission buffer register, until all bytes are sent；
Step 9: digital signal processor TMS320F2812 to bus communication electrical level transferring chip ISO3082 reception/
It sends selection port and sends low level, enabled so that bus communication electrical level transferring chip ISO3082 is in send to forbid and receive
State；
Step 10: digital signal processor TMS320F2812 receives data that host computer is sent to digital signal processor
The reception buffer register of TMS320F2812, then by its assignment in the 1st byte for receiving array；
Step 11：Digital signal processor TMS320F2812 judges whether the 1st byte for receiving array is equal to communication
Packet header 0x7E as defined in agreement comes back for step 10 if unequal, if equal, carries out step 12；
Step 12：Digital signal processor TMS320F2812 receives data that host computer is sent to Digital Signal Processing
The reception buffer register of device TMS320F2812, then by its assignment in the 2nd byte for receiving array；
Step 13：Digital signal processor TMS320F2812 judges whether the 2nd byte for receiving array is equal to communication
Packet header 0x7E as defined in agreement comes back for step 10 if unequal, if equal, same steps is taken successively to connect
The reception buffer register of data that host computer is sent to digital signal processor TMS320F2812 is received, and by its assignment in connecing
Receive the 3rd to the 7th byte of array；
Step 14：Digital signal processor TMS320F2812 judges whether the value for receiving the 6th byte of array is equal to
Receive the byte number -3 of valid data；If equal, step 15 is carried out, ten are returned to step if unequal；
Step 15：Digital signal processor TMS320F2812 will receive the 3rd byte 0x01 of array, the 4th byte
0x00, the 5th byte 0x01 summation, and judge resulting value 0x02 a minimum byte 0x02 whether with receive the 7th of array
A byte is equal, if equal, carries out step 10 six, ten are returned to step if unequal；
Step 10 six：Digital signal processor TMS320F2812 will receive the 3rd byte 0x01 of array, the 4th byte
0x00, the 5th byte 0x01 difference assignment in corresponding starting/stopping order, forward/reverse order, closed loop/open loop order,
Motor is in start, invert, operation with closed ring state；
Step 10 seven：Return to step one.
Embodiment
Step 1: digital signal processor TMS320F2812 to bus communication electrical level transferring chip ISO3082 reception/
It sends selection port and sends high level, transmission is enabled and reception is forbidden so that bus communication electrical level transferring chip ISO3082 is in
State；
Step 2: the packet header 0x7E write-in of data packet is sent the 1st of array by digital signal processor TMS320F2812
Byte, then the packet header 0x7E of data packet is written to the 2nd byte for sending array；
Step 3: digital signal processor TMS320F2812 writes the valid data that axial flow blower host computer needs respectively
Enter to send the 3rd, 4,5,6 byte of array, wherein the 3rd byte represents the high byte of the real-time tachometer value of motor, be worth for 0xCE,
4th byte represents the low byte of the real-time tachometer value of motor, is worth for 0x1F, and the 5th byte represents the height of motor bus current value
Byte, is worth for 0xA1, and the 6th byte represents the low byte of motor bus current value, be worth for 0x9D；
Step 4: the valid data byte that digital signal processor TMS320F2812 needs axial flow blower host computer
Number -4 is assigned to the 7th byte for sending array；
Step 5: digital signal processor TMS320F2812 sums the 3rd, 4,5,6 byte for sending array, i.e., will
0xCE, 0x1F, 0xA1,0x9D summation, and a minimum byte 0x22 of resulting value 0x022B is assigned to and sends the 8th of array
A byte；
Step 6: the 1st byte for sending array is assigned at digital signal by digital signal processor TMS320F2812
Manage the transmission buffer register of device TMS320F2812；
Step 7: the transmission of digital signal processor TMS320F2812 enquiring digital signal processor TMS320F2812 is slow
It rushes whether register is completed to send, carries out in next step, if not completing, waiting always if completing；
Step 8: the 2nd byte for sending array is assigned at digital signal by digital signal processor TMS320F2812
The transmission buffer register for managing device TMS320F2812, then executes step 7；And press same step successively assignment the 3rd to the 8th
Byte to digital signal processor TMS320F2812 transmission buffer register, until all bytes are sent；
Step 9: digital signal processor TMS320F2812 to bus communication electrical level transferring chip ISO3082 reception/
It sends selection port and sends low level, enabled so that bus communication electrical level transferring chip ISO3082 is in send to forbid and receive
State；
Step 10: digital signal processor TMS320F2812 receives data that host computer is sent to digital signal processor
The reception buffer register of TMS320F2812, then by its assignment in the 1st byte for receiving array；
Step 11：Digital signal processor TMS320F2812 judges whether the 1st byte for receiving array is equal to communication
Packet header 0x7E as defined in agreement comes back for step 10 if unequal, if equal, carries out step 12；
Step 12：Digital signal processor TMS320F2812 receives data that host computer is sent to Digital Signal Processing
The reception buffer register of device TMS320F2812, then by its assignment in the 2nd byte for receiving array；
Step 13：Digital signal processor TMS320F2812 judges whether the 2nd byte for receiving array is equal to communication
Packet header 0x7E as defined in agreement comes back for step 10 if unequal, if equal, same steps is taken successively to connect
The reception buffer register of data that host computer is sent to digital signal processor TMS320F2812 is received, and by its assignment in connecing
Receive the 3rd to the 7th byte of array；
Step 14：Digital signal processor TMS320F2812 judges whether the value for receiving the 6th byte of array is equal to
Receive the byte number -3 of valid data；If equal, step 15 is carried out, ten are returned to step if unequal；
Step 15：Digital signal processor TMS320F2812 will receive the 3rd byte 0x01 of array, the 4th byte
0x00, the 5th byte 0x01 summation, and judge resulting value 0x02 a minimum byte 0x02 whether with receive the 7th of array
A byte is equal, if equal, carries out step 10 six, ten are returned to step if unequal；
Step 10 six：Digital signal processor TMS320F2812 will receive the 3rd byte 0x01 of array, the 4th byte
0x00, the 5th byte 0x01 difference assignment in corresponding starting/stopping order, forward/reverse order, closed loop/open loop order,
Motor is in start, invert, operation with closed ring state；
Step 10 seven：Return to step one.
Claims (2)
1. a kind of axial flow blower communication data packets accuracy control method, which is characterized in that this method is in axial flow blower and its accordingly
In the environment of the hardware fault-free of controller and host computer, following steps are taken：
Step 1: microprocessor sends high level to reception/transmission control signal of bus communication electrical level transferring chip, so that always
Line communication electrical level transferring chip is in the state that enabled and reception is forbidden that sends；
Step 2: the packet header 0x7E of data packet write-in is sent the 1st byte of array by microprocessor, then by the packet header of data packet
0x7E write-in sends the 2nd byte of array；
Step 3: the valid data that axial flow blower host computer needs are respectively written into the send array the 3rd, 4,5,6 by microprocessor
A byte；
Step 4: the number -4 of valid data byte is assigned to the 7th byte for sending array by microprocessor；
Step 5: microprocessor sums the 3rd, 4,5,6 byte for sending array, and a minimum byte for resulting value is assigned
It is worth to the 8th byte for sending array；
Step 6: the 1st byte for sending array is assigned to the transmission buffer register of microprocessor by microprocessor；
Step 7: whether the transmission buffer register of microprocessor inquiry microprocessor is completed to send, carried out if completing next
Step, if not completing, waits always；
Step 8: the 2nd byte for sending array is assigned to the transmission buffer register of microprocessor by microprocessor, then hold
Row step 7；And by same step successively the 3rd to the 8th byte of assignment to microprocessor transmission buffer register, until institute
There is byte to be sent；
Step 9: microprocessor sends low level to reception/transmission control signal of bus communication electrical level transferring chip, so that always
Line communication electrical level transferring chip, which is in send, forbids and receives enabled state；
Step 10: microprocessor receives the data of host computer transmission to the reception buffer register of microprocessor, then assigned
It is worth in the 1st byte for receiving array；
Step 11：Microprocessor judges whether the 1st byte for receiving array is equal to packet header 0x7E as defined in communications protocol, such as
Fruit is unequal, then comes back for step 10, if equal, carries out step 12；
Step 12：Microprocessor receives the data of host computer transmission to the reception buffer register of microprocessor, then by it
Assignment is in the 2nd byte for receiving array；
Step 13：Microprocessor judges whether the 2nd byte for receiving array is equal to packet header 0x7E as defined in communications protocol, such as
Fruit is unequal, then comes back for step 10, if equal, same steps is taken successively to receive the data of host computer transmission to micro-
The reception buffer register of processor, and by its assignment in the 3rd to the 7th byte for receiving array；
Step 14：Microprocessor judges whether the value for receiving the 6th byte of array is equal to the byte for receiving valid data
Number -3；If equal, step 15 is carried out, ten are returned to step if unequal；
Step 15：Microprocessor will receive the 3rd byte, the 4th byte, the 5th byte summation of array, and judge gained
Whether a minimum byte for value is equal with the 7th byte of array is received, if equal, step 10 six is carried out, if unequal
Then return to step ten；
Step 10 six：Microprocessor will receive the 3rd byte, the 4th byte, the 5th byte difference assignment of array in correspondence
Control instruction；
Step 10 seven：Return to step one.
2. axial flow blower communication data packets accuracy control method as described in claim 1, which is characterized in that described in step 10 six
Control instruction be starting/stopping order, forward/reverse order, closed loop/open loop order, respectively with receive the 3rd, the of array
4, the 5th byte is corresponding.
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| JP2007114918A (en) * | 2005-10-19 | 2007-05-10 | Kyocera Mita Corp | Bus arbitration system |
| CN202598769U (en) * | 2012-03-31 | 2012-12-12 | 上海市电力公司 | Venting control device for 10kV power distribution station |
| CN103746890A (en) * | 2013-06-09 | 2014-04-23 | 国家电网公司 | Competition model RS-485 bus multimaster communication system and working method thereof |
| CN103873598A (en) * | 2012-12-12 | 2014-06-18 | 深圳航天东方红海特卫星有限公司 | Standardized interface device suitable for satellite-borne electronic equipment |
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2014
- 2014-11-14 CN CN201410649520.5A patent/CN105634892B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007114918A (en) * | 2005-10-19 | 2007-05-10 | Kyocera Mita Corp | Bus arbitration system |
| CN202598769U (en) * | 2012-03-31 | 2012-12-12 | 上海市电力公司 | Venting control device for 10kV power distribution station |
| CN103873598A (en) * | 2012-12-12 | 2014-06-18 | 深圳航天东方红海特卫星有限公司 | Standardized interface device suitable for satellite-borne electronic equipment |
| CN103746890A (en) * | 2013-06-09 | 2014-04-23 | 国家电网公司 | Competition model RS-485 bus multimaster communication system and working method thereof |
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