CN105632910A - Gate conductor layer and manufacturing method thereof - Google Patents

Gate conductor layer and manufacturing method thereof Download PDF

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Publication number
CN105632910A
CN105632910A CN201510147801.5A CN201510147801A CN105632910A CN 105632910 A CN105632910 A CN 105632910A CN 201510147801 A CN201510147801 A CN 201510147801A CN 105632910 A CN105632910 A CN 105632910A
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conductive material
groove
material powder
layer
conductor layer
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CN201510147801.5A
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CN105632910B (en
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钟汇才
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a gate conductor layer and a manufacturing method thereof. A sample method can comprise the following steps: filling a groove defined by gate side walls with conductive material powder; and carrying out laser annealing on the filled conductive material powder to form a conducting material layer; and the conducting material layer forms the gate conductor layer.

Description

Grid conductor layer and manufacture method thereof
Technical field
The application relates to semiconductor fabrication process, more particularly, to a kind of grid conductor layer and manufacture method thereof.
Background technology
Along with constantly reducing of semiconductor device, start to widely use rear grid technique. In rear grid technique, it is initially formed sacrificial gate stacking, and is stacked as basis to carry out device manufacture with sacrificial gate, such as source drain implant etc. Then, remove sacrificial gate stacking, and stacking filling real grid in the groove that the inner side of grid side wall stays due to the stacking removal of sacrificial gate, as stacking in high K/ metal gate. But, along with the size of semiconductor device reduces further, it is difficult to be filled with in increasingly less groove.
Summary of the invention
In view of the above problems, present disclose provides a kind of method manufacturing grid conductor layer.
According to an aspect of this disclosure, it is provided that a kind of method manufacturing grid conductor layer, including: filled conductive material powder in the groove limited by grid side wall; And the conducting material powder filled is carried out laser annealing, to form conductive material layer, described conductive material layer forms described grid conductor layer.
According to another aspect of the present disclosure, it is provided that a kind of grid conductor layer, including the conductive material substantially without cavity and pore. Such as, conductive material can include the conductive material of melted rear recrystallization.
According to embodiment of the disclosure, it is possible to by filled conductive material powder and carry out laser annealing and form grid conductor layer. Owing to the filling of powder is easier than the filling of metal film, such that it is able to be easily manufactured grid conductor layer. It is furthermore possible to also provide more closely, there is no the filling effect of cavity and pore.
Accompanying drawing explanation
By referring to the accompanying drawing description to disclosure embodiment, above-mentioned and other purposes of the disclosure, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1-6 shows according to the schematic diagram in some stages in the flow process manufacturing grid conductor layer of disclosure embodiment.
Detailed description of the invention
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure. However, it should be understood that these descriptions are illustrative of, and it is not intended to limit the scope of the present disclosure. Additionally, in the following description, eliminate the description to known features and technology, to avoid unnecessarily obscuring the concept of the disclosure.
Various structural representations according to disclosure embodiment shown in the drawings. These figure are not drawn to scale, wherein in order to know the purpose of expression, are exaggerated some details, and are likely to eliminate some details. Various regions shown in figure, the shape of layer and relative size, the position relationship between them are merely illustrative of, reality is likely to be due to manufacturing tolerance or technical limitations and deviation to some extent, and those skilled in the art can additionally design the regions/layers with difformity, size, relative position according to actually required.
In the context of the disclosure, when one layer/element is called be positioned at another layer/element " on " time, this layer/element can be located immediately on this another layer/element, or can there is intermediate layer/element between them. If it addition, one towards in one layer/element be positioned at another layer/element " on ", then when turn towards time, this layer/element may be located at this another layer/element D score.
According to embodiment of the disclosure, it is provided that a kind of method manufacturing grid conductor layer. The method can include filled conductive material powder in the groove limited by grid side wall, and the conducting material powder filled is carried out laser annealing. Laser can make powder smelting/thawing, and forms fine and close conductive material layer, and the conductive material layer obtained can form grid conductor layer. Smaller due to powder, such that it is able to be relatively easily filled in groove. It is furthermore possible to also provide more closely, there is no the filling effect of cavity and pore.
Groove can be obtained by rear grid technique. Specifically, it is possible on substrate formed sacrificial gate stacking, and on the sidewall that sacrificial gate is stacking formed grid side wall. Based on sacrificial gate stacking (and grid side wall), device manufacture can be carried out, for instance, source drain implant etc. It is then possible to be formed with on the substrate that sacrificial gate is stacking formation dielectric layer, and dielectric layer is carried out planarization process such as chemically mechanical polishing (CMP), stacking to expose sacrificial gate. The sacrificial gate exposed can be removed stacking, thus leaving groove to be filled inside grid side wall.
Can successively form such conductive material layer. For example, it is possible to several times to filled conductive material powder in groove, and carry out laser annealing after filling every time, until the conductive material layer formed fills up groove. The conducting material powder every time filled can be substantially evenly distributed in groove, thus forming the substantially uniform conductive material layer of thickness after annealing. Each conductive material layer is continuous and integral each other, thus constituting grid conductor layer. Additionally, the conducting material powder filled can include different compositions every time.
When filled conductive material powder, it is possible to make conducting material powder only exist in groove. Such as, when filling, it is possible to remove the conducting material powder being positioned at outside groove. This removal can be realized by adhesive tape.
When annealing, laser can apply on pattern-free ground. Owing to conducting material powder can only exist in groove, thus only groove is interior forms conductive material layer. Or, laser can be confined to the region at groove place. For example, it is possible to the formation pattern according to groove, apply laser. Then, the conductive material layer formed can be confined in groove.
The technology of the disclosure can present in many ways, some of them example explained below.
With reference to Fig. 1, it is provided that substrate 102. Substrate 102 can be various forms of suitable substrate, such as body Semiconductor substrate such as Si, Ge etc., compound semiconductor substrate is SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb etc. such as, semiconductor-on-insulator substrate (SOI) etc. At this, it is described for body silicon substrate and silicon based material. It should be noted however that the disclosure is not limited to this.
On the substrate 102, it is possible to form sacrificial gate stacking. Sacrificial gate is stacking can include sacrificial gate dielectric layer 104 and sacrificial gate conductor layer 106. Sacrificial gate dielectric layer 104 can include oxide (e.g., silicon oxide), and thickness is about 3-20nm; Sacrificial gate conductor layer 106 can include polysilicon, and thickness is about 30-100nm. This sacrificial gate is stacking such as can pass through on the substrate 102 deposited oxide layer and polysilicon layer successively, and is obtained for such as bar shaped by they compositions such as reactive ion etching (RIE).
On the sidewall that sacrificial gate is stacking, it is possible to form grid side wall 108. Grid side wall 108 can include nitride (e.g., silicon nitride), and thickness is about 1-20nm. Grid side wall 108 such as can pass through be formed on the substrate that sacrificial gate is stacking and substantially conformally depositing one layer of nitride, then it is carried out anisotropic etching such as RIE and obtain.
Device manufacture can be carried out, for instance carry out source drain implant etc. based on sacrificial gate stacking (and grid side wall). Those skilled in the art will know that various ways is to carry out these techniques, does not repeat them here.
On the substrate 102, it is possible to by such as depositing, dielectric layer 110 is formed. Dielectric layer 110 can include oxide, it is possible to is completely covered that sacrificial gate is stacking and grid side wall. Dielectric layer 110 can be carried out planarization such as chemically mechanical polishing (CMP). CMP can stop at grid side wall 108, thus it is stacking to expose sacrificial gate.
Then, as shown in Figure 2, it is possible to by selective etch, sacrificial gate is removed stacking. For example, it is possible to by TMAH solution, selective removal sacrificial gate conductor layer 106. Furthermore it is possible to by such as RIE, selective removal sacrificial gate dielectric layer 104. Then, inside grid side wall 108, groove 112 is left. Afterwards, it is possible in groove 112, fill real grid stacking, for instance high K/ metal gate is stacking.
Then, as shown in Figure 3, it is possible to by such as depositing, the structure shown in Fig. 2 forms gate dielectric layer 114. Gate dielectric layer 114 can include high-K gate dielectric such as HfO2, thickness is about 2-4nm. Furthermore it is also possible to by such as depositing, gate dielectric layer 114 forms work function regulating course 116. Work function regulating course 116 can include TiN, and thickness is about 3-10nm.
Subsequently, as shown in Figure 4, it is possible to by such as depositing, filled conductive material powder 118 in the groove 112 after being filled with gate dielectric layer 114 and work function regulating course 116. Conducting material powder 118 can include metal, in TiN, W, Al and Cu at least one. In the filling process, it is possible to make conducting material powder 118 be confined in groove 112. For example, it is possible to by methods such as adhesive tapes, remove the outer powder that may be present of groove 112.
Then, as shown in Figure 5, it is possible to the conducting material powder 118 filled is carried out laser annealing so that it is fusing/melt, then cooling recrystallization thus forming the conductive material layer 120 of densification in groove. This conductive material layer 120 is used as grid conductor layer.
Laser can patternless applying in the structure shown in Fig. 4, for instance scan through the whole surface of structure shown in Fig. 4. Owing to conducting material powder 118 is only located in groove, so also being located in groove by the conductive material layer 120 formed of annealing.
Or, laser can according to groove be patterned to apply, thus annealing is confined to the region at groove place. In this case, it might even be possible to after laser annealing, remove the conducting material powder outside groove again.
In the above examples, a padding just deposited enough powder in groove. But, the disclosure is not limited to this. For example, it is possible to repeatedly powder filler, the powder every time filled is relatively thin one layer. This helps avoid and would be likely to occur the defects such as hole owing to once filling too much powder in the trench. The conducting material powder every time filled can be generally uniform. Laser annealing can be carried out after filling, so that the conducting material powder of filling is converted into conductive material layer every time. Such operation can be repeated up to be formed the conductive material layer of required size, for instance substantially fills up groove. These conductive material layers are continuous and integral each other, thus forming grid conductor.
In this respect it is to be noted that the composition of the conducting material powder filled for each time need not be identical.
After forming grid conductor layer 120, it is possible to technique carries out routinely. Such as, as shown in Figure 6, it is possible to the structure shown in Fig. 5 is carried out planarization and processes such as CMP. CMP can stop at grid side wall, with the part removing gate dielectric layer 114 and work function regulating course 116 is positioned at outside groove. So, in groove, define final real grid stacking, including gate dielectric layer 116 ', work function regulating course 116 ' and grid conductor layer 120.
In the above description, the ins and outs such as the composition of each layer, etching are not described in detail. It should be appreciated to those skilled in the art that by various technological means, the layer of required form, region etc. can be formed. It addition, in order to form same structure, those skilled in the art can be devised by method not identical with process as described above. Although it addition, respectively describing each embodiment above, but it is not intended that the measure in each embodiment can not be advantageously combined use.
Embodiment of this disclosure is described above. But, the purpose that these embodiments are merely to illustrate that, and it is not intended to restriction the scope of the present disclosure. The scope of the present disclosure is limited by claims and equivalent thereof. Without departing from the scope of the present disclosure, those skilled in the art can make multiple replacement and amendment, and these substitute and amendment all should fall within the scope of the present disclosure.

Claims (12)

1. the method manufacturing grid conductor layer, including:
Filled conductive material powder in the groove limited by grid side wall; And
The conducting material powder filled is carried out laser annealing, and to form conductive material layer, described conductive material layer forms described grid conductor layer.
2. method according to claim 1, wherein, several times to filled conductive material powder in groove, and carries out laser annealing every time after filling.
3. method according to claim 2, wherein, the conducting material powder every time filled includes heterogeneity.
4. method according to claim 1, wherein, before filled conductive material powder, the method also includes:
Gate dielectric layer is filled in groove.
5. method according to claim 4, also includes:
Filling work function regulating course in groove, wherein work function regulating course is located on gate dielectric layer.
6. method according to claim 5, wherein, after forming grid conductor layer, the method also includes:
Carry out planarization process, to remove the gate dielectric layer part and work function regulating course part existed outside groove.
7. method according to claim 1, wherein, conducting material powder includes at least one in TiN, W, Al and Cu.
8. method according to claim 1, also includes: remove the conducting material powder existed outside groove.
9. method according to claim 8, wherein, utilizes adhesive tape to be removed.
10. method according to claim 1, wherein, laser annealing is confined to the region at groove place.
11. a grid conductor layer, including the conductive material substantially without cavity and pore.
12. grid conductor layer according to claim 11, wherein, described conductive material includes the conductive material of melted rear recrystallization.
CN201510147801.5A 2015-03-31 2015-03-31 Gate conductor layer and manufacturing method thereof Active CN105632910B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108723389A (en) * 2017-04-18 2018-11-02 台湾积体电路制造股份有限公司 The method for forming conductive powder

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0138673A2 (en) * 1983-09-21 1985-04-24 Allied Corporation Method of making a printed circuit board
CN1959531A (en) * 2005-10-31 2007-05-09 飞思卡尔半导体公司 Method for forming multi-layer bumps on a substrate
KR20110137158A (en) * 2010-06-16 2011-12-22 한국생산기술연구원 Anisotropic conductive film having containing groove of conductive material, joining method of flip chip using epoxy resin having containing groove of conductive material and flip chip package using the same
CN102339752A (en) * 2010-07-14 2012-02-01 中国科学院微电子研究所 Method for manufacturing semiconductor device based on gate replacement technique
CN102915949A (en) * 2011-08-01 2013-02-06 中国科学院微电子研究所 Method for embedding metal material in substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0138673A2 (en) * 1983-09-21 1985-04-24 Allied Corporation Method of making a printed circuit board
CN1959531A (en) * 2005-10-31 2007-05-09 飞思卡尔半导体公司 Method for forming multi-layer bumps on a substrate
KR20110137158A (en) * 2010-06-16 2011-12-22 한국생산기술연구원 Anisotropic conductive film having containing groove of conductive material, joining method of flip chip using epoxy resin having containing groove of conductive material and flip chip package using the same
CN102339752A (en) * 2010-07-14 2012-02-01 中国科学院微电子研究所 Method for manufacturing semiconductor device based on gate replacement technique
CN102915949A (en) * 2011-08-01 2013-02-06 中国科学院微电子研究所 Method for embedding metal material in substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108723389A (en) * 2017-04-18 2018-11-02 台湾积体电路制造股份有限公司 The method for forming conductive powder
US11819923B2 (en) 2017-04-18 2023-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive powder formation method and device for forming conductive powder

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