CN105630479A - Processing method and apparatus for exception in program running process - Google Patents
Processing method and apparatus for exception in program running process Download PDFInfo
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- CN105630479A CN105630479A CN201410714733.1A CN201410714733A CN105630479A CN 105630479 A CN105630479 A CN 105630479A CN 201410714733 A CN201410714733 A CN 201410714733A CN 105630479 A CN105630479 A CN 105630479A
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Abstract
The invention discloses a processing method and apparatus for an exception in a program running process. The method comprises the steps of analyzing a currently running code segment to determine a first instruction and/or a second instruction, wherein the first instruction is used for enabling register information to be lost, and the second instruction is used for enabling the stack content to be covered; in a code segment running process, storing the lost register information when the first instruction is run; and/or, storing the covered stack content when the second instruction is run. According to the technical scheme provided by the invention, CPU running process data that cannot be obtained in a general program running process can be obtained in time, thereby providing technical support for reversely deducing CPU exception reasons.
Description
Technical field
The present invention relates to the communications field, in particular to the abnormality eliminating method in a kind of program operation process and device.
Background technology
At present, often occurring all kinds abnormal in the program operation process of embedded system, its common exception has illegal address access, illegal instruction etc. After abnormal generation, system can report abnormal information, and wherein, this information can comprise the field conditions such as register information when mistake occurs and stack information. Developer needs according to the anti-source pushing away mistake of these field datas. But the anti-journey that pushes through would generally be failed, developer it is frequently necessary to be pinpointed the problems by Walkthrough code, thus brings great difficulty to fault location. The anti-most critical reason pushing away failure is to occur to a lot of information of CPU exception pilot process from mistake to lose. The analysis found that, the main cause of the information of loss mainly includes following 4 kinds:
If reason one function A first calls function B, then call function C, then the stack information of the storehouse meeting coverage function B of function C, if so that mistake occurs in function B, then the stack information of function B cannot be utilized to find mistake.
Some particular register (such as: the R9 in the PowerPC system of gcc compiling) is moved to right or mask operation by reason two, intermediate computations, if and source register separately has it to use after operation terminates, then being operated by end value cannot source register value before anti-push operation.
Reason three, source register is performed the result after AND-operation put back to source register, therefore, counter can not push away source register value after operation terminates.
Reason four, the cause effect relation fixed because of memory address and the data deficiency of place, address, therefore, in the address intermediate computations of memory read-write operation, if the depositor preserving memory address separately has its use after operation terminates, also will be unable to counter push away source address by the content-data read and write.
In other words, there is moment central processing unit (CPU) and stacked field information is counter pushes away abnormal cause if necessary by abnormal, it is necessary to CPU is abnormal occur before will grab above 4 category informations. But, common programming side cannot capture above 4 category informations, and its reason is in that:
(1) common program is inherently present in function body and is forever unable to reach function end position.
(2) action itself preserving storehouse influences whether the storehouse of function.
(3) if removing to set up another a function to preserve the storehouse of certain function, then new function can be brought to exit problem and form an Infinite Cyclic contradiction.
(4) when coding be each function increase preserve storehouse action be unpractical.
(5) common program is not aware that when CPU runs, oneself, performing what kind of instruction, therefore cannot accurately judge whether what depositor certain moment preserves.
(6) common program is not aware that when writing which bar statement can perform what type instruction and operate which depositor by corresponding CPU.
(7) CPU will necessarily perform extra instruction for save register, can produce again the possibility of new loss information simultaneously, so can bring an Infinite Cyclic contradiction.
(8) statement increasing substantial amounts of save register when coding is unpractical.
In sum, owing in program time of running, usual program cannot obtain function stack information and be likely to the register information lost in correlation technique, thus CPU occur abnormal after, it is impossible to search the abnormal reason occurred.
Summary of the invention
Embodiments provide the abnormality eliminating method in a kind of program operation process and device, at least to solve the problem that the program in correlation technique cannot obtain the CPU running data before extremely occurring after CPU generation is abnormal.
According to an aspect of the invention, it is provided the abnormality eliminating method in a kind of program operation process.
The abnormality eliminating method in program operation process according to embodiments of the present invention includes: currently running code segment is analyzed, determine the first instruction and/or the second instruction, wherein, first instruction is the instruction causing register information to lose, and the second instruction is the instruction causing stack content capped; In code segment running, whenever running to the first instruction, the register information lost is stored; And/or, whenever running to the second instruction, capped stack content is stored.
Preferably, code segment is analyzed, it is determined that the first instruction and/or the second instruction include: obtain currently employed compiler type and central processor CPU type of architecture; Determine that depositor uses rule according to compiler type and CPU type of architecture; After the binary code being compiled into by code segment by compiler under CPU architecture, the instruction format of rule and CPU architecture is used to search the first instruction and/or the second instruction from the binary code after compiling according to depositor.
Preferably, whenever running to the first instruction, the register information lost is carried out storage to include: the first global data district of application free time and the second global data district, wherein, first global data district for according to the instruction rule construct of CPU architecture can the register information of memory loss and the binary code that code segment continues to run with can be jumped back to from the first instruction, the second global data district is for the register information of memory loss; Being the 3rd instruction by the first instruction modification, wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to first location of instruction; Whenever running to the first instruction, pass through to operate in the binary code of structure in the first global data district stored by the register information of loss to the second global data district.
Preferably, whenever running to the second instruction, capped stack content is carried out storage to include: the first global data district of application free time and the 3rd global data district, wherein, first global data district is for storing capped stack content according to the instruction rule construct of CPU architecture and can jump back to the binary code that code segment continues to run with from the second instruction, and the second global data district is for storing capped stack content; Being the 3rd instruction by the second instruction modification, wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to second location of instruction; Whenever running to the second instruction, pass through to operate in the binary code of structure in the first global data district store capped stack content to the 3rd global data district.
Preferably, in the first global data district the binary code of structure to be instruction address by running in code segment with the difference of the address of the binary code of the storage configuration hewed out in the first global data district piece together draws.
According to a further aspect in the invention, it is provided that the exception handling device in a kind of program operation process.
The exception handling device in program operation process according to embodiments of the present invention comprises determining that module, for currently running code segment is analyzed, determine the first instruction and/or the second instruction, wherein, first instruction is the instruction causing register information to lose, and the second instruction is the instruction causing stack content capped; Processing module, for, in code segment running, storing the register information lost whenever running to the first instruction; And/or, whenever running to the second instruction, capped stack content is stored.
Preferably, it is determined that module includes: acquiring unit, for obtaining currently employed compiler type and central processor CPU type of architecture; Determine unit, for determining that depositor uses rule according to compiler type and CPU type of architecture; Search unit, be used for after binary code code segment being compiled under CPU architecture by compiler, use according to depositor the instruction format of rule and CPU architecture to search the first instruction and/or the second instruction from the binary code after compiling.
Preferably, processing module includes: the first application unit, for applying for the first global data district and the second global data district of free time, wherein, first global data district for according to the instruction rule construct of CPU architecture can the register information of memory loss and the binary code that code segment continues to run with can be jumped back to from the first instruction, the second global data district is for the register information of memory loss; First amendment unit, for being the 3rd instruction by the first instruction modification, wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to first location of instruction; First memory element, stores the register information of loss to the second global data district for passing through to operate in the binary code of structure in the first global data district whenever running to the first instruction.
Preferably, processing module includes: the second application unit, for applying for the first global data district and the 3rd global data district of free time, wherein, first global data district is for storing capped stack content according to the instruction rule construct of CPU architecture and can jump back to the binary code that code segment continues to run with from the second instruction, and the second global data district is for storing capped stack content; Second amendment unit, is the 3rd instruction by the second instruction modification, and wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to second location of instruction; Second memory element, stores capped stack content to the 3rd global data district for passing through to operate in the binary code of structure in the first global data district whenever running to the second instruction.
Preferably, in the first global data district the binary code of structure to be instruction address by running in code segment with the difference of the address of the binary code of the storage configuration hewed out in the first global data district piece together draws.
By the embodiment of the present invention, adopting and currently running code segment is analyzed, it is determined that the first instruction and/or the second instruction, wherein, the first instruction is the instruction causing register information to lose, and the second instruction is the instruction causing stack content capped; In code segment running, whenever running to the first instruction, the register information lost is stored; And/or, whenever running to the second instruction, capped stack content is stored, the program in correlation technique that solves is in the CPU problem that the CPU running data before cannot obtaining abnormal generation after extremely occur, it is thus possible to obtain the CPU running data that cannot obtain when usual program is run in time, provide technical support for the anti-CPU of pushing away abnormal cause.
Accompanying drawing explanation
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, and the schematic description and description of the present invention is used for explaining the present invention, is not intended that inappropriate limitation of the present invention. In the accompanying drawings:
Fig. 1 is the flow chart of the abnormality eliminating method in program operation process according to embodiments of the present invention;
Fig. 2 is the flow chart of the abnormality eliminating method in program operation process according to the preferred embodiment of the invention;
Fig. 3 be according to the preferred embodiment of the invention code segment, data segment, stack segment schematic diagram of transformation results in internal memory;
Fig. 4 is the binary code structural representation of neotectonics according to the preferred embodiment of the invention;
Fig. 5 is the structured flowchart of the exception handling device in program operation process according to embodiments of the present invention;
Fig. 6 is the structured flowchart of the exception handling device in program operation process according to the preferred embodiment of the invention.
Detailed description of the invention
Below with reference to accompanying drawing and describe the present invention in detail in conjunction with the embodiments. It should be noted that when not conflicting, the embodiment in the application and the feature in embodiment can be mutually combined.
Fig. 1 is the flow chart of the abnormality eliminating method in program operation process according to embodiments of the present invention. As it is shown in figure 1, the method can include following process step:
Step S102: currently running code segment is analyzed, it is determined that the first instruction and/or the second instruction, wherein, the first instruction is the instruction causing register information to lose, and the second instruction is the instruction causing stack content capped;
Step S104: in code segment running, stores the register information lost whenever running to the first instruction; And/or, whenever running to the second instruction, capped stack content is stored.
There are the CPU running data before cannot obtaining abnormal generation after extremely in the program in correlation technique at CPU. Adopt method as shown in Figure 1, it is possible to the register information that can lose can store according to the precedence of instruction operation, and/or, it is possible to capped stack content can store by the precedence of function operation. Once CPU occurs abnormal, the exception on-the-spot CPU depositor and the stack information that are provided by system coordinate above-mentioned stored information again, developer just complete can obtain the anti-all running processes pushing away the CPU past and data, finally derives the reason of abnormal generation.
It should be noted that technical scheme provided by the present invention is applicable to the CPU architecture of all fixed length instructions collection, for instance: PowerPC, MIPS, ARM.
Preferably, in step s 102, code segment is analyzed, it is determined that the first instruction and/or the second instruction can include following operation:
Step S1: obtain currently employed compiler type and central processor CPU type of architecture;
Step S2: determine that depositor uses rule according to compiler type and CPU type of architecture;
Step S3: after the binary code being compiled into by code segment by compiler under CPU architecture, uses the instruction format of rule and CPU architecture to search the first instruction and/or the second instruction from the binary code after compiling according to depositor.
Such as: function return instructions is blr under PowerPC architecture, and binary code is fixed as 01001110100000000000000000100000.
Particular CPU architecture is had fixing depositor to use rule by specific compiler, for instance: in the gcc tools chain binary code for compiling PowerPC architecture CPU out, r9 is often used as the pilot process depositor of computing and uses. Such as: generally the middle ephemeral data of memory read-write operation can leave in r9 depositor. Instruction lwzr0,0 (r9) are an indirect addressing instructions and point to reads to r0 from r9 register value, and after this instruction is finished, r9 generally will separately have it to use and be capped. Lwzr0, the binary code of 0 (r9) is 10000000000010010000000000000000, bit0-5 is 100000 is the coding of lwz, bit11-15 is 01001, its value is 9 refer to for r9, in other words, what meet bit0-5=100000 and bit11-15=01001 is an instruction possible loss information. Other the instruction being likely to loss register information and function return instructions can also be judged according to instruction format, repeat no more herein.
Preferably, in step S104, whenever running to the first instruction, the register information lost is carried out storage and may comprise steps of:
Step S4: the first global data district of application free time and the second global data district, wherein, first global data district for according to the instruction rule construct of CPU architecture can the register information of memory loss and the binary code that code segment continues to run with can be jumped back to from the first instruction, the second global data district is for the register information of memory loss;
Step S5: be the 3rd instruction by the first instruction modification, wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to first location of instruction;
Step S6: pass through to operate in the binary code of structure in the first global data district whenever running to the first instruction and the register information of loss is stored to the second global data district.
Preferably, in step S104, whenever running to the second instruction, capped stack content is carried out storage and can include following operation:
Step S7: the first global data district of application free time and the 3rd global data district, wherein, first global data district is for storing capped stack content according to the instruction rule construct of CPU architecture and can jump back to the binary code that code segment continues to run with from the second instruction, and the second global data district is for storing capped stack content;
Step S8: be the 3rd instruction by the second instruction modification, wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to second location of instruction;
Step S9: pass through to operate in the binary code of structure in the first global data district whenever running to the second instruction and capped stack content is stored to the 3rd global data district.
In a preferred embodiment, it is possible to apply for global data district D1 (being equivalent to above-mentioned first global data district), D2 (being equivalent to above-mentioned second global data district) and D3 (being equivalent to above-mentioned 3rd global data district) three pieces idle. D1 is used for creating new binary code, and D2 is used for preserving the register information of loss, and D3 is used for preserving stack information.
Process runs the instruction that may lose information in start time first code analysis section, these instruction modifications are become jump instruction, the target redirected be one section of loss information that can preserve gone out according to cpu instruction rule construct and can the binary code of rebound original program flow process.
Process will be run with the new binary code being modified after having performed the function that the present invention describes, program will jump to, whenever the location of instruction going to originally may lose register information, the register information going preservation to lose in the binary code Cn of corresponding neotectonics, then performs the instruction the former flow process of rebound that were originally replaced again. If running to function return instructions place will jump to the C of neotectonics, preserving relevant position in current function stack frame D3, then in rebound, layer functions continues executing with. The register information so may lost sequentially can be saved in D2 according to the precedence that instruction performs, it is possible to capped stack content can be saved in D3 by the precedence that function performs. Once CPU occurs abnormal, the on-the-spot CPU depositor of exception and the stack information that are provided by system coordinate the information in D2 and D3 again, and developer just complete can obtain the anti-all execution sequences pushing away the CPU past and data, finally derives the reason of abnormal generation.
Preferably, in above-mentioned first global data district the binary code of structure to be instruction address by running in code segment with the difference of the address of the binary code of the storage configuration hewed out in the first global data district piece together draws.
It is further elaborated for jump instruction how creating binary code. under normal conditions, CPU has relative jump instruction, only it is to be understood that it can be pieced together by the difference of this instruction and target instruction address. such as: certain instruction lwzr9 under original program PowerPC architecture, 0 (r9) address is 0x1000000, and the Cn regional address hewed out is 0x1100000, then the difference of address is 0x100000, in order to make CPU jump to 0x1100000 from 0x1000000, can piece together out a jump instruction is bl0x1100000, the binary code of its correspondence is 01001000000100000000000000000001, wherein, bit0-5 is the binary code 010010 of jump instruction b, bit6-29 is the 1/4 of the relative address redirected, (relative address is the distance redirected, here for 000001000000000000000000=1/4*0x100000, bit31 is that the lower bar instruction address of this instruction is stored to lr depositor for returning by 1 expression). the binary code of this instruction is placed on the location of instruction at original program place, thus will can automatic jump to 0x1100000 address when original program goes to this address of 0x1000000 and go to perform new binary code. under particular CPU architecture, every binary code in C and Cn can construct according to similar approach.
Below the above-mentioned process that is preferable to carry out is further described by the preferred implementation shown in Fig. 2.
Fig. 2 is the flow chart of the abnormality eliminating method in program operation process according to the preferred embodiment of the invention. As in figure 2 it is shown, the method can include following process step:
Step S202: after process initiation, applies for global data district D1, D2 and D3 three pieces idle. Fig. 3 be according to the preferred embodiment of the invention code segment, data segment, stack segment schematic diagram of transformation results in internal memory. As it is shown on figure 3, according to D1, D2, D3 present position in program is run, D1 is used for creating new binary code, D2 is used for preserving the register information of loss, and D3 is used for preserving stack information.
Step S204: the binary code C that one section of CPU of structure can run in the D1 district of application, this block binary code C serves as the effect of code in the form of data, and its content mainly may include that
(1) pile stack top from original program and expand Zone R as new stack frame;
(2) the binary code C depositor used is preserved to Zone R;
(3) D3 district free time address pointer is obtained;
(4) original program function stack top and stack frame length are obtained;
(5) jump to memcpy preservation stack frame information to locate to the D3 free time;
(6) depositor used is recovered from Zone R;
(7) rollback Zone R recovers original function stack top;
(8) function return instructions.
Fig. 4 is the binary code structural representation of neotectonics according to the preferred embodiment of the invention. As shown in Figure 4, its depositor R3, R4 and R5 being used in C, Cn and the C of PowerPC architecture CPU is that the function that compiler is specified passes ginseng depositor, and Ra, Rb, Rc and Rd are the general register being arbitrarily different from R3, R4 and R5.
Step S206: analyze next binary code of current process;
Step S208: judge whether the lower bar instruction (can bring into operation from the Article 1 instruction of this process code section when first entering into) of process code section has reached code segment ending. If it is, flow process terminates; Otherwise, step S210 is entered.
Step S210: judge whether this instruction is positioned at place function. If it is, forward step S206 to; Otherwise, step S212 is entered.
Step S212: judge whether this instruction is the indirect addressing instructions possible lose intermediate operations register information. If it is, enter step S216; Otherwise, step S214 is entered.
Step S214: judge that whether this instruction moves to right or mask operational order for being likely to lose intermediate operations depositor. If it is, enter step S216, otherwise, step S220 is entered.
Step S216: create a new binary code section Cn (n=0,1,2,3,4 ...) in D1 district, then be the new jump instruction relatively branching to Cn by this instruction modification. The content of Cn may include that
(1) pile stack top from original program and expand Zone R as new stack frame;
(2) depositor used of Cn is preserved to Zone R;
(3) D2 district free time address pointer is obtained;
(4) preserve the register value being likely to loss information in the instruction of original program to locate to the D2 district free time;
(5) D2 district free time address pointer is preserved;
(6) the Cn depositor used is recovered from Zone R;
(7) rollback Zone R recovers original function stack top;
(8) instruction of original program this operation original;
(9) the lower bar location of instruction of the former instruction that rebound is modified.
For the detailed construction of the Cn of PowerPC architecture CPU as shown in Figure 4.
Step S218: revising this instruction is the instruction jumping to the last Cn created in previous step. Forward step S206 to.
Step S220: judge whether this instruction is function return instructions. If it is, enter step S222; Otherwise, step S206 is forwarded to.
Step S222: revising this instruction is the instruction jumping to the C created in step S204. Enter step S206.
Fig. 5 is the structured flowchart of the exception handling device in program operation process according to embodiments of the present invention. As shown in Figure 5, exception handling device in this program operation process may include that determines module 10, for currently running code segment is analyzed, determine the first instruction and/or the second instruction, wherein, first instruction is the instruction causing register information to lose, and the second instruction is the instruction causing stack content capped; Processing module 20, for, in code segment running, storing the register information lost whenever running to the first instruction; And/or, whenever running to the second instruction, capped stack content is stored.
Adopt device as shown in Figure 5, the program in correlation technique that solves is in the CPU problem that the CPU running data before cannot obtaining abnormal generation after extremely occur, it is thus possible to obtain the CPU running data that cannot obtain when usual program is run in time, provide technical support for the anti-CPU of pushing away abnormal cause.
Preferably, as shown in Figure 6, it is determined that module 10 may include that acquiring unit 100, for obtaining currently employed compiler type and central processor CPU type of architecture; Determine unit 102, for determining that depositor uses rule according to compiler type and CPU type of architecture; Search unit 104, for, after the binary code being compiled into by code segment by compiler under CPU architecture, using the instruction format of rule and CPU architecture to search the first instruction and/or the second instruction from the binary code after compiling according to depositor.
Preferably, as shown in Figure 6, processing module 20 may include that the first application unit 200, for applying for the first global data district and the second global data district of free time, wherein, first global data district for according to the instruction rule construct of CPU architecture can the register information of memory loss and the binary code that code segment continues to run with can be jumped back to from the first instruction, the second global data district is for the register information of memory loss; First amendment unit 202, for being the 3rd instruction by the first instruction modification, wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to first location of instruction; First memory element 204, stores the register information of loss to the second global data district for passing through to operate in the binary code of structure in the first global data district whenever running to the first instruction.
Preferably, as shown in Figure 6, processing module 20 may include that the second application unit 206, for applying for the first global data district and the 3rd global data district of free time, wherein, first global data district is for storing capped stack content according to the instruction rule construct of CPU architecture and can jump back to the binary code that code segment continues to run with from the second instruction, and the second global data district is for storing capped stack content; Second amendment unit 208, is the 3rd instruction by the second instruction modification, and wherein, the 3rd instruction runs the binary code of structure for jumping to the first global data district when each run to second location of instruction; Second memory element 210, stores capped stack content to the 3rd global data district for passing through to operate in the binary code of structure in the first global data district whenever running to the second instruction.
Preferably, in above-mentioned first global data district the binary code of structure to be instruction address by running in code segment with the difference of the address of the binary code of the storage configuration hewed out in the first global data district piece together draws.
In from the description above, can be seen that, above embodiments enable following technique effect (it should be noted that these effects are the effects that some preferred embodiment can reach): adopt the technical scheme that the embodiment of the present invention provides, the instruction type being likely to loss information when first CPU program being run makes screening, and adopt the binary code of neotectonics to replace these instructions being likely to loss information, it is achieved thereby that obtain the function of the CPU running data that cannot obtain when usual program is run, provide technical support for the anti-abnormal cause that pushes away.
Obviously, those skilled in the art should be understood that, each module of the above-mentioned present invention or each step can realize with general calculation element, they can concentrate on single calculation element, or it is distributed on the network that multiple calculation element forms, alternatively, they can realize with the executable program code of calculation element, thus, can be stored in storage device is performed by calculation element, and in some cases, shown or described step can be performed with the order being different from herein, or they are fabricated to respectively each integrated circuit modules, or the multiple modules in them or step are fabricated to single integrated circuit module realize. so, the present invention is not restricted to the combination of any specific hardware and software.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations. All within the spirit and principles in the present invention, any amendment of making, equivalent replacement, improvement etc., should be included within protection scope of the present invention.
Claims (10)
1. the abnormality eliminating method in a program operation process, it is characterised in that including:
Currently running code segment being analyzed, it is determined that the first instruction and/or the second instruction, wherein, described first instruction is the instruction causing register information to lose, and described second instruction is the instruction causing stack content capped;
In described code segment running, whenever running to described first instruction, the register information lost is stored; And/or, whenever running to described second instruction, capped stack content is stored.
2. method according to claim 1, it is characterised in that described code segment is analyzed, it is determined that described first instruction and/or described second instruction include:
Obtain currently employed compiler type and central processor CPU type of architecture;
Determine that depositor uses rule according to described compiler type and described CPU type of architecture;
After described code segment being compiled into the binary code under CPU architecture by compiler, the instruction format of regular and described CPU architecture is used to search described first instruction and/or described second instruction from the binary code after compiling according to described depositor.
3. method according to claim 2, it is characterised in that whenever running to described first instruction, the register information lost is carried out storage and include:
The first global data district of application free time and the second global data district, wherein, described first global data district is for storing the register information of described loss according to the instruction rule construct of described CPU architecture and can jump back to the binary code that described code segment continues to run with from described first instruction, and described second global data district is for storing the register information of described loss;
Being the 3rd instruction by described first instruction modification, wherein, described 3rd instruction runs the binary code of structure for jumping to described first global data district when each run to described first location of instruction;
Whenever running to described first instruction, pass through to operate in the binary code of structure in described first global data district stored by the register information of described loss to described second global data district.
4. method according to claim 2, it is characterised in that whenever running to described second instruction, described capped stack content is carried out storage and include:
The first global data district of application free time and the 3rd global data district, wherein, described first global data district is for storing described capped stack content according to the instruction rule construct of described CPU architecture and can jump back to the binary code that described code segment continues to run with from described second instruction, and described second global data district is for storing described capped stack content;
Being the 3rd instruction by described second instruction modification, wherein, described 3rd instruction runs the binary code of structure for jumping to described first global data district when each run to described second location of instruction;
Whenever running to described second instruction, pass through to operate in the binary code of structure in described first global data district store described capped stack content to described 3rd global data district.
5. the method according to claim 3 or 4, it is characterized in that, in described first global data district, to be instruction address by running in described code segment with the difference of the address of the binary code depositing described structure hewed out in described first global data district piece together the binary code of structure draws.
6. the exception handling device in a program operation process, it is characterised in that including:
Determining module, for currently running code segment is analyzed, it is determined that the first instruction and/or the second instruction, wherein, described first instruction is the instruction causing register information to lose, and described second instruction is the instruction causing stack content capped;
Processing module, for, in described code segment running, storing the register information lost whenever running to described first instruction; And/or, whenever running to described second instruction, capped stack content is stored.
7. device according to claim 6, it is characterised in that described determine that module includes:
Acquiring unit, for obtaining currently employed compiler type and central processor CPU type of architecture;
Determine unit, for determining that depositor uses rule according to described compiler type and described CPU type of architecture;
Search unit, for, after described code segment being compiled into the binary code under CPU architecture by compiler, using the instruction format of regular and described CPU architecture to search described first instruction and/or described second instruction from the binary code after compiling according to described depositor.
8. device according to claim 7, it is characterised in that described processing module includes:
First application unit, for applying for the first global data district and the second global data district of free time, wherein, described first global data district is for storing the register information of described loss according to the instruction rule construct of described CPU architecture and can jump back to the binary code that described code segment continues to run with from described first instruction, and described second global data district is for storing the register information of described loss;
First amendment unit, for being the 3rd instruction by described first instruction modification, wherein, described 3rd instruction runs the binary code of structure for jumping to described first global data district when each run to described first location of instruction;
First memory element, stores the register information of described loss to described second global data district for passing through to operate in the binary code of structure in described first global data district whenever running to described first instruction.
9. device according to claim 7, it is characterised in that described processing module includes:
Second application unit, for applying for the first global data district and the 3rd global data district of free time, wherein, described first global data district is for storing described capped stack content according to the instruction rule construct of described CPU architecture and can jump back to the binary code that described code segment continues to run with from described second instruction, and described second global data district is for storing described capped stack content;
Second amendment unit, is the 3rd instruction by described second instruction modification, and wherein, described 3rd instruction runs the binary code of structure for jumping to described first global data district when each run to described second location of instruction;
Second memory element, stores described capped stack content to described 3rd global data district for passing through to operate in the binary code of structure in described first global data district whenever running to described second instruction.
10. device according to claim 8 or claim 9, it is characterized in that, in described first global data district, to be instruction address by running in described code segment with the difference of the address of the binary code depositing described structure hewed out in described first global data district piece together the binary code of structure draws.
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| CN201410714733.1A CN105630479A (en) | 2014-11-28 | 2014-11-28 | Processing method and apparatus for exception in program running process |
| PCT/CN2015/089284 WO2016082601A1 (en) | 2014-11-28 | 2015-09-09 | Method and apparatus for anomaly processing in running process of program |
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| CN201410714733.1A CN105630479A (en) | 2014-11-28 | 2014-11-28 | Processing method and apparatus for exception in program running process |
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Cited By (2)
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| CN114003291A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Application program running method and device, computing equipment and storage medium |
| CN116820568A (en) * | 2023-06-09 | 2023-09-29 | 北京市合芯数字科技有限公司 | Instruction translation method and device, storage medium and terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108664250B (en) * | 2018-03-27 | 2022-02-01 | 北京奇艺世纪科技有限公司 | Code processing method and device |
| CN113190459A (en) * | 2021-05-24 | 2021-07-30 | 曙光信息产业(北京)有限公司 | Program operation detection method and device, heterogeneous electronic equipment and readable storage medium |
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