CN105629803B - FPGA logic cell with feedback path - Google Patents
FPGA logic cell with feedback path Download PDFInfo
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- CN105629803B CN105629803B CN201410582452.5A CN201410582452A CN105629803B CN 105629803 B CN105629803 B CN 105629803B CN 201410582452 A CN201410582452 A CN 201410582452A CN 105629803 B CN105629803 B CN 105629803B
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Abstract
The present invention provides a kind of logic units with feedback path.The logic unit increases higher level's cascade structure to the feedback path of subordinate's cascade structure, increased by a little area, it can be under the premise of without using input multiple selector, " lookup table register look-up table " and " Register Lookup table register " structure is realized inside logic unit, critical path delay is reduced, the flexibility ratio of eda tool mapping, vanning is increased.
Description
Technical field
The present invention relates to integrated circuit industry programmable gate array (FPGA) technical field more particularly to a kind of band are anti-
The FPGA logic cell of feeder diameter.
Background technology
Field programmable gate array is developed after years development, is become in electronic circuit system, IC design
Important component.The basic logic unit module of field programmable gate array (FPGA), is related to FPGA performances, face
Long-pending optimization and the foundation of electric design automation (EDA) tool synthesis mapping model.FPGA on the market is patrolled substantially at present
It collects unit module and mostly uses isolated island formula structure, is i.e. logical resource presses array distribution, and interconnection resource is connected with each other.
The nuclear structure for " isolated island " that traditional logical resource is constituted is as shown in Figure 1, unit 11 is known as logic array in figure
Block (Logic Array Block, abbreviation LAB) shares m input terminal.Include n logic unit (Logic in LAB
Element, abbreviation LE) 12-1,12-2 ... 12-n and left and the one-to-one n groups of LE input multiple selector
(Input Multiplexer, abbreviation Input Mux) 16-1,16-2 ... 16-n.Every group of Input Mux includes k (m+n)
1 multiple selector, k output of generation is selected to give in the corresponding LE in the right；The output end of n LE is right by backfeed loop 17
The m input terminal for being sent to Input Mux16-1, the input terminal of 16-2 ... 16-n and LAB answered is gated.LE is by a k
Input look-up table (Look Up Table, abbreviation LUT) 13-1,13-2 ... the 13-n singly exported and a register
(Register, abbreviation REG) 14-1,14-2 ... 14-n cascade compositions.Pass through output multi-channel selector (Output
Multiplexer, abbreviation Out Mux) 15-1,15-2 ... 15-n selection is the output of look-up table 13 or the output of trigger 14
It is sent to LE output ends.
As integrated circuit technology is constantly progressive, line delay proportion in critical path delay gradually increases, because
This eda tool is always packed into more resources inside LAB as far as possible in the comprehensive mapping and placement-and-routing for carrying out FPGA,
Reduce the use of interconnecting channels.To meet such demand, the scale of LAB constantly expands, and shows look-up table LUT input terminal numbers
K increases common till now 6 less than 4 from initial stage, is adjusted accordingly so as to cause LAB inputs number m and LE number n.According to
Elias Ahmed and Jonathan Rose are in article " The Effect of LUT and Cluster Size on Deep-
Submicron FPGA Performance and Density,”Very Large Scale Integration(VLSI)
Studies conducted in Systems, abbreviation IEEE Transactions on, vol.12, no.3, pp.288-298,2004, m's
Best value is：
And the best value that the best value of k is 4 to 6, n is 4 to 10.K=4, n=10 are taken, then m=22；Take k=6, n
=8, then m=27.It can thus be appreciated that Input Mux are fan-in Mux one group big, no matter using which kind of structure realization or multiplexing unit
Divide input terminal, delay all considerable.Therefore designer it is desirable also to which more logical resources are put into inside LE, as far as possible around
Cross the influence of Input Mux.
If Fig. 2 is a kind of common cascaded solution (bibliography 1) of the prior art, it is omitted in LAB in figure
Input Mux 16-1,16-2 ... 16-n and feedback path 17-1,17-2 ... 17-n, only draw the parts LE of core.Figure
Middle 21-1,21-2 ... 21-n is the single output look-up table of k inputs, and 2 input multiple selector 23a-1,23a- are added in front
2……23a-n.K-1 in k input terminal are normally input in LUT, and the last one input terminal passes through 23a-1,23a-
It is input to this grade of LUT again after 2 ... 23a-n, with feedback signal 24-1,24-2 ... the 24-n gatings of upper level LUT output ends
In.For example, for LUT21-2, an input signal of the feedback signal 24-1 and LUT21-2 of LUT21-1 pass through multi-path choice
It is input in LUT21-2 after device 23a-2 selections.Similarly, 22-1,22-2 ... 22-n are register, 22-1,22-2 ...
The input terminal of 22-n is there are 2 input multiple selector 23b-1,23b-2 ... 23b-n, these multiple selector are to LUT output ends
With the data terminal for inputting this grade of REG after the output end selection of upper level REG.It is more that the output end of LUT and REG also passes through 2 inputs
Road selector selection is input to outside LE.It is such design enable to 24-n, 25-n constitute two independent LUT chains and
REG chains can be realized easily inside LE when needing combinational logic to cascade or shift register, avoid detouring
Input Mux。
Fig. 3 is the prior art being further improved (bibliography 2) to LE structures shown in Fig. 2.Keeping institute mentioned above
Under the premise of structured, feedback path 36-1,36-2 ... 36-n of REG to this grade LUT input terminal is added.Correspondingly, it searches
Multiple selector 23a-1,23a-2 ... 23a-n in front of table LUT21-1,21-2 ... 21-n increases to 3 inputs by 2 inputs,
Respectively certain of look-up table inputs all the way, register output is fed back in upper level look-up table input feedback and this cascade structure.
The structure ensure that when register to be realized is in the posterior cascade structure of preceding, look-up table, can easily pass through control multichannel
Selector is realized.Concrete methods of realizing is：By taking 21-2 and 22-2 as an example, 23a-2 selects register in this cascade structure to feed back
36-2,23b-2 select upper level be coupled structure in register 22-1 output end as in this cascade structure register 22-2 it is defeated
Enter, 23c-2 selects the output end of look-up table 21-2 as last output.
By mentioned earlier, the influence of line delay is more and more significant, and eda tool is always as far as possible put into more logics
In single logic unit, and reduce the use of channel line and Input Mux.It is illustrated in figure 7 common when several mappings, vanning
Situation：(a) look-up table is followed by register；(b) register is followed by look-up table；(c) look-up table cascade chain；(d) register cascade chain；
(e) all connect look-up table before and after register；(f) all connect register before and after look-up table.
In several structures described previously, the situation during the basic structure of Fig. 1 can only be realized such as Fig. 7 inside LE shown in (a),
And other situations must all be realized by feedback path 17 and Input Mux 16.Fig. 2 structures are due to introducing look-up table and posting
The cascade chain of storage can realize (a) (c) (d) three kinds of situations in Fig. 7 inside LE；Fig. 3 structures introduce register to this grade
The feedback path 36 of look-up table can further realize situation shown in (b) in Fig. 7.But in Fig. 7 (e) (f), three of the above
Structure can not be realized inside LE, at least through an Input Mux.
Reference paper：
1、F.Erich Goetting,Stephen M.Trimberger,Xilinx,Inc,Logic cell for
field programmable gate array having optional internal feedback and optional
cascade,US5500608A,1996.3.19；
2、Bruce Pedersen,Altera Corporation,Logic circuitry with shared
lookup table,US7317330B2,2008.1.8；
Invention content
(1) technical problems to be solved
In view of above-mentioned technical problem, the present invention provides a kind of FPGA logic cells with feedback path, with as more as possible
Realization logic function.
(2) technical solution
The present invention provides a kind of logic units with feedback path.The logic unit includes：N grades of cascade structure, often
The cascade structure of level-one includes：The single output look-up table of k inputs and register；Wherein, in n grades of the cascade structure, upper one
Grade cascade structure between the cascade structure of next stage have feedback path, n >=2.
(3) advantageous effect
It can be seen from the above technical proposal that logic unit of the present invention with feedback path has the advantages that：
(1) on the basis of existing structure, higher level's cascade structure is increased to the feedback path of subordinate's cascade structure, is passed through
A little area increases, and can realize that " look-up table-is posted inside logic unit under the premise of without using input multiple selector
Storage-look-up table " and " register-look-up table-register " structure reduce critical path delay, increase eda tool and reflect
The flexibility ratio penetrate, cased.
(2) two kinds of alternative structure Fig. 5 and Fig. 6 of equal value are in addition proposed, advantage is identical with Fig. 4, area
Change slightly different, can flexibly be accepted or rejected in three kinds of structures according to actual conditions.
Description of the drawings
Fig. 1 is the nuclear structure schematic diagram of prior art FPGA basic logic unit modules；
Fig. 2 is schematic diagram of the prior art to the module-cascade solutions of FPGA basic logic units shown in Fig. 1；
Fig. 3 is showing for the FPGA basic logic unit modules after the prior art is further improved solution shown in Fig. 2
It is intended to；
Fig. 4 is to input list with k in register to subordinate's cascade structure in higher level's cascade structure according to the embodiment of the present invention one
Export the structural schematic diagram of the FPGA logic cell of look-up table feedback path；
Fig. 5 is according to the embodiment of the present invention two with the single output look-up table of k inputs in higher level's cascade structure to subordinate's level link
The structural schematic diagram of the FPGA logic cell of register feedback path in structure；
Fig. 6 is to be output to the single output of k inputs in subordinate's cascade structure with higher level's cascade structure according to the embodiment of the present invention three
The structural schematic diagram of the FPGA logic cell of look-up table feedback path；
Fig. 7 is several frequently seen mapping, vanning situation schematic diagram.
Specific implementation mode
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.It should be noted that in attached drawing or specification description, similar or identical portion
Divide and all uses identical figure number.The realization method for not being painted or describing in attached drawing is those of ordinary skill in technical field
Known form.In addition, though the demonstration of the parameter comprising particular value can be provided herein, it is to be understood that parameter is without definite etc.
In corresponding value, but can be similar to be worth accordingly in acceptable error margin or design constraint.
The present invention is on the basis of existing structure, by increasing between the neighbouring cascade structure inside FPGA logic cell
Feedback path, so as under the premise of without using input multiple selector, with the increased cost of a little area, be patrolled in FPGA
Collect " look-up table-register-look-up table " and " register-for realizing that existing FPGA logic cell cannot achieve inside unit
Look-up table-register " structure.
One, embodiment one
In first exemplary embodiment of the present invention, provides one kind and taking register in cascade structure and looked into subordinate
Look for the logic unit of table feedback path.Fig. 4 is according to the embodiment of the present invention one with register in higher level's cascade structure to subordinate's grade
It is coupled the structural schematic diagram of the FPGA logic cell of look-up table feedback path in structure.As shown in figure 4, the FPGA logic cell packet
It includes：N grades of cascade structure.Wherein, the cascade structure per level-one includes：Four select a multiple selector, the single output of k inputs to search
Table, the first alternative multiple selector, register and the second alternative multiple selector, wherein n >=2.
In i-stage cascade structure (1≤i≤n), the connection relation of each component is as follows：Four select a multiple selector, and four
A input terminal is respectively connected to output end, the (i-1)-th grade of cascade structure of the single output look-up table of k inputs in (i-1)-th grade of cascade structure
The k input terminal [0 of the output end of register and this grade of cascade structure in the output end of middle register, this grade of cascade structure:k-
1] input terminal 0 in；The single output look-up table of k inputs, k input terminal are respectively connected to k input terminal of this grade of cascade structure
[0:K-1] in 1~k-1 of input terminal and above-mentioned four select the output end of a multiple selector；First alternative multiple selector,
It is single defeated that its two input terminal is respectively connected to the output end of register and k inputs in this grade of cascade structure in (i-1)-th grade of cascade structure
Go out the output end of look-up table；Register, input terminal are connected to the output end of the first alternative multiple selector；Second alternative
Multiple selector, two input terminals are respectively connected to the output end of the output end and register of the single output look-up table of k inputs, defeated
Output end of the outlet as this grade of cascade structure.
For the 1st grade of cascade structure, four select two input terminals in four input terminals of a multiple selector to be separately connected
The last one input terminal in this grade of cascade structure in k input terminal of the output end of register and this grade of cascade structure, in addition
Two input terminals will be connected to another FPGA logic cell.One of first two input terminals of alternative multiple selector are even
It is connected to the output end of the single output look-up table of k inputs in this grade of cascade structure, another input terminal will be connected to another fpga logic list
Member.
Specific to please refer to Fig. 4, wherein 21-1,21-2 ... 21-n is the single output look-up table of k inputs, and front selects one for four
Multiple selector 23a-1,23a-2 ... 23a-n.K-1 in k input terminal of this grade of cascade structure normal, and to be input to k defeated
Enter in single output look-up table, and the last one input terminal selects multiple selector 23a-1,23a-2 a ... 23a-n by four, with
It is input to again in this grade of LUT after feedback signal 24-1,24-2 ... the 24-n gatings of upper level LUT output ends.For example, for
An input signal of the feedback signal 24-1 and LUT21-2 of LUT21-2, LUT21-1 select it by multiple selector 23a-2
After be input in LUT21-2.Similarly, 22-1,22-2 ... 22-n are register, and register 22-1,22-2 ... 22-n's is defeated
Entering end, there are multiple selector 23b-1,23b-2 ... 23b-n, these multiple selector are to LUT output ends and upper level REG
The data terminal of this grade of REG is inputted after output end selection.The output end of LUT and REG also passes through the selection of alternative multiple selector
It is input to outside LE.Such design enables to 24-n, 25-n to constitute two independent LUT chains and REG chains, when needing group
When logical cascade or shift register, it can easily be realized inside LE, avoid the Input Mux that detour.
The feedback path of REG to this grade LUT input terminal is 36-1,36-2 ... 36-n, which, which ensure that, works as and to realize
Register can easily pass through control multiple selector to realize in the posterior cascade structure of preceding, look-up table.Specific implementation
Method is：By taking 21-2 and 22-2 as an example, 23a-2 selects register in this cascade structure to feed back 36-2, and 23b-2 selects upper level connection
Input of the output end of register 22-1 as register 22-2 in this cascade structure in structure, 23c-2 select look-up table 21-2
Output end as last output.
The feedback path that register is output to the input of next stage look-up table is 47-1,47-2 ... 47-n.The structure can be into
One step realizes function shown in (e) (f) in Fig. 7 inside LE..
Specifically, the connection relation when needing to realize each function shown in Fig. 7 is as follows：
(a) when realizing " look-up table-register " structure shown in (a) in Fig. 7, single concatenation structure can be realized, with
In Fig. 4 for i-stage, the one or two input multiple selector 23b-i selects the second input terminal (this grade of look-up table 21-i output end),
Second alternative multiple selector 23c-i selects the second input terminal (register 22-i output ends in this cascade structure), the function
Select the strobe case of a multiple selector 23a-i unrelated with four.
(b) when realizing " register-look-up table " structure shown in (b) in Fig. 7, single cascade structure can be realized, with
In Fig. 4 for i-stage, four select a multiple selector 23a-i selection third input terminal (register 22-i in this grade of cascade structure
Output end, that is, feedback path 36-i), the one or two input multiple selector 23b-i selections first input end ((i-1)-th grade of cascade
Register 22- (i-1) output end 25- (i-1) in structure), the second alternative multiple selector 23c-i selects first input end
(this grade of look-up table 21-i output end).
(c) when realizing " look-up table-look-up table " structure shown in (c) in Fig. 7, with look-up table 21- (i-1) in Fig. 4 and
For 21-i, the four of i-stage cascade structure selects a multiple selector 23a-i to select the second input terminal (in (i-1)-th grade of cascade structure
The output end of the single output look-up table 21- (i-1) of k inputs), the two or two input multiple selector 23c-i choosings of i-stage cascade structure
First input end (output end of i-stage look-up table 21-i) is selected, the function is unrelated with the strobe case of other multiple selector.
(d) when realizing " register-register " structure shown in (d) in Fig. 7, with register 22- (i-1) in Fig. 4 and
For 22-i, the one or two input multiple selector 23b-i of i-stage cascade structure selects first input end ((i-1)-th grade of level link
Register 22- (i-1) output end 25- (i-1) in structure), the two or two input multiple selector 23c-i of i-stage cascade structure
Select the second input terminal (register 22-i output ends in i-stage cascade structure), the gating of the function and other multiple selector
Situation is unrelated.
(e) it when realizing " look-up table-register-look-up table " structure shown in (e) in Fig. 7, needs in n grades of cascade structures
Two-stage be arranged in the following way to realize, by taking look-up table 21- (i-1), 21-i in Fig. 4 and register 22- (i-1) as an example：
For (i-1)-th cascade structure：Described four select the strobe case of a multiple selector 23a- (i-1) and this function without
It closes；The first alternative multiple selector 23b- (i-1) selects the second input terminal, i.e. k in this grade ((i-1)-th grade) cascade structure
The output end of the single output look-up table 21- (i-1) of input；The strobe case of the second alternative multiple selector 23c- (i-1)
It is unrelated with this function；
For the cascade structure of i-stage：Described four select a multiple selector 23a-i to select the second input terminal, i.e., (i-1)-th grade
The output end 47- (i-1) of register 22- (i-1) in cascade structure；The gating feelings of the first alternative multiple selector 23-i
Condition is unrelated with this function；The second alternative multiple selector 23c-i selects first input end, i.e. k in this grade of cascade structure
The output end of the single output look-up table 21-i of input.
(f) it when realizing " register-look-up table-register " structure shown in (f) in Fig. 7, needs in n grades of cascade structures
Two-stage be arranged in the following way to realize, by taking look-up table 21- (i-1), 21-i in Fig. 4 and register 22- (i-1) as an example：
For (i-1)-th grade of cascade structure：Each multiple selector 23a- (i-1), 23b- (i-1) and 23c- (i-1)
Strobe case it is unrelated with this function；
For the cascade structure of i-stage：Described four select a multiple selector 23a-i to select the second input terminal, i.e., (i-1)-th grade
The output end 47- (i-1) of register 22- (i-1) in cascade structure；First alternative multiple selector 23b-i selection the
Two input terminals, the i.e. output end of the single output look-up table 21-i of k inputs in this grade of cascade structure；The second alternative multi-path choice
Device 23c-i selects the second input terminal, i.e. the output end of register 22-i in this grade of cascade structure.
As it can be seen that by adjusting the output of four multiple selector, common mapping vanning situation shown in Fig. 7 can be by this reality
The circuit structure covering for applying example proposition, avoids the delay loss caused by Input Mux and interconnection architecture that detours.
Two, embodiment two
In second exemplary embodiment of the present invention, provides and posted in a kind of band higher level look-up table to lower cascade structure
The logic unit of storage feedback path.Fig. 5 is to be searched with the single output of k inputs in higher level's cascade structure according to the embodiment of the present invention two
The structural schematic diagram of the FPGA logic cell of register feedback path in table to subordinate's cascade structure.As shown in figure 5, the FPGA is patrolled
Collecting unit includes：N grades of cascade structure, wherein n >=2.
The structure equally retains all structures of Fig. 3, and addition look-up table, which is output in next cascade structure, on this basis posts
Storage input channel (58-1,58-2 ..., 58-n), the change cause register (22-1,22-2 ..., 22-n) defeated simultaneously
Enter the multiple selector (23b-1,23b-2 ..., 23b-n) at end by 2 inputs to be increased as 3 inputs, caused advantageous effect with
Fig. 4 is of equal value.
Wherein, the cascade structure per level-one includes：First one-out-three multiple selector, the single output look-up table of k inputs, second
One-out-three multiple selector, register and alternative multiple selector.
Wherein, in i-stage cascade structure (1≤i≤n)：First one-out-three multiple selector, three of them input terminal difference
It is connected to the output of register in the output end of the single output look-up table of k inputs, this grade of cascade structure in (i-1)-th grade of cascade structure
The k input terminal [0 at end and this grade of cascade structure:K-1] in input terminal 0；The single output look-up table of k inputs, k input terminal
It is respectively connected to the k input terminal [0 of this grade of cascade structure:K-1] in 1~k-1 of input terminal and above-mentioned first one-out-three multichannel
The output end of selector；Second one-out-three multiple selector, thirdly input terminal is respectively connected to deposit in (i-1)-th grade of cascade structure
It is single to input k inputs in single output end for exporting look-up table and this grade of cascade structure by k in the output end of device, (i-1)-th grade of cascade structure
Export the output end of look-up table；Register, input terminal are connected to the output end of above-mentioned second one-out-three multiple selector；Two choosings
One multiple selector, two input terminals are respectively connected to the output end of the output end and register of the single output look-up table of k inputs,
Output end of the output end as this grade of cascade structure.
For the 1st grade of cascade structure, two input terminals in three input terminals of the first one-out-three multiple selector are distinguished
The last one input terminal in k input terminal of the output end of register and this grade of cascade structure in this grade of cascade structure is connected,
In addition a input terminal will be connected to other external FPGA logic cells.Three inputs of the second one-out-three multiple selector
An input terminal in end is connected to the output of this grade of single output look-up table of cascade structure k inputs, and another two input terminal will connect
To other external FPGA logic cells.
Specifically, the connection relation when needing to realize each function shown in Fig. 7 is as follows：
(a) when realizing " look-up table-register " structure shown in (a) in Fig. 7, single cascade structure can be realized, with
In Fig. 5 for i-stage, the second one-out-three multiple selector 23b-i selection third input terminals (this grade of look-up table 21-i output end),
Alternative multiple selector 23c-i selects the second input terminal (register 22-i output ends in this cascade structure), the function and the
The strobe case of one one-out-three multiple selector 23a-i is unrelated.
(b) when realizing " register-look-up table " structure shown in (b) in Fig. 7, single cascade structure can be realized, with
In Fig. 5 for i-stage, the first one-out-three multiple selector 23a-i selects the second input terminal (register in this grade of cascade structure
The output end of 22-i, that is, feedback path 36-i), the second one-out-three multiple selector 23b-i selects first input end ((i-1)-th
The output end of register 22- (i-1) in grade cascade structure) or (the single output of k inputs in (i-1)-th grade of cascade structure of the second input terminal
The output end of look-up table 21- (i-1)), alternative multiple selector 23c-i selections first input end (look by this grade of single output of k inputs
Look for the output end of table 21-i).
(c) when realizing " look-up table-look-up table " structure shown in (c) in Fig. 7, with look-up table 21- (i-1) in Fig. 5 and
For 21-i, the first one-out-three multiple selector 23a-i of i-stage cascade structure selects first input end ((i-1)-th grade of level link
The output end of the single output look-up table 21- (i-1) of k inputs in structure), the alternative multiple selector 23c-i choosings of i-stage cascade structure
Select first input end (output end of the single output look-up table of i-stage k inputs), the strobe case of the function and other multiple selector
It is unrelated.
(d) when realizing " register-register " structure shown in (d) in Fig. 7, with register 22- (i-1) in Fig. 5 and
For 22-i, the second one-out-three multiple selector 23b-i of i-stage cascade structure selects first input end ((i-1)-th grade of level link
The output end of register 22- (i-1) in structure), alternative multiple selector 23c-i the second inputs of selection of i-stage cascade structure
It holds (output end of register 22-i in i-stage cascade structure), the function is unrelated with the strobe case of other multiple selector.
(e) it when realizing " look-up table-register-look-up table " structure shown in (e) in Fig. 7, needs in n grades of cascade structures
Two-stage be arranged in the following way to realize, by taking look-up table 21- (i-1), 21-i in Fig. 5 and register 22- (i-1) as an example：
For (i-1)-th grade of cascade structure：Each multiple selector 23a- (i-1), 23b- (i-1) and 23c- (i-1)
Strobe case it is unrelated with this function；
For the cascade structure of i-stage：The first one-out-three multiple selector 23a-i selects the second input terminal, i.e., originally
The output end of register 22-i in grade cascade structure；The second one-out-three multiple selector 23b-i selects the second input terminal, i.e.,
The output end 58- (i-1) of the single output look-up table 21- (i-1) of k inputs in (i-1)-th grade of cascade structure；The alternative multi-path choice
Device 23c-i selects first input end, i.e. the output end of the single output look-up table 21-i of k inputs in this grade of cascade structure.
(f) it when realizing " register-look-up table-register " structure shown in Fig. 7 (f), needs in n grades of cascade structures
Two-stage is arranged in the following way to realize, by taking register 22- (i-1), 22-i in Fig. 5 and look-up table 21- (i-1) as an example：
For (i-1)-th grade of cascade structure：First one-out-three multiple selector 23a- (i-1) selection, second input
End, i.e., the output end of register 22- (i-1) in this grade ((i-1)-th grade) cascade structure；To avoid circuit cyclic, the described 2nd 3
Select a multiple selector 23b- (i-1) that third input terminal cannot be selected, i.e., k inputs are single defeated in this grade ((i-1)-th grade) cascade structure
Go out the output end of look-up table 21- (i-1), and first input end can only be selected, i.e. register 22- (i- in the i-th -2 grades cascade structures
2) output end or the second input terminal, the i.e. output end of the single output look-up table 21- (i-2) of k inputs in the i-th -2 grades cascade structures；
The strobe case of the alternative multiple selector 23c- (i-1) is unrelated with this function.
For the cascade structure of i-stage：The strobe case of the first one-out-three multiple selector 23a-i and this function without
It closes；The second one-out-three multiple selector 23b-i selects the second input terminal, i.e. the single output of k inputs in (i-1)-th grade of cascade structure
The output end 58- (i-1) of look-up table 21- (i-1)；The alternative multiple selector 23c-i selects the second input terminal, i.e. this grade
The output end of register in cascade structure.
Three, embodiment three
In second exemplary embodiment of the present invention, provides a kind of band higher level cascade structure and be output to subordinate's cascade
The logic unit of the single output look-up table feedback path of k inputs in structure.Fig. 6 is according to the embodiment of the present invention three with higher level's level link
Structure is output to the structural schematic diagram of the FPGA logic cell of the single output look-up table feedback path of k inputs in subordinate's cascade structure.Such as
Shown in Fig. 6, which includes：N grades of cascade structure, wherein n >=2.
As shown in fig. 6, the structure retains most of structure in Fig. 3, only eliminates look-up table and be output to next stage lookup
Feedback path 24-1,24-2 ... the 24-n of table input, instead total output end (23c-1,23c-2 ... from LE
23c-n output ends) arrive feedback path 69-1,69-2 ... 69-n that next stage look-up table inputs.Since the total output ends of LE are logical
Crossing multiple selector 23c-1,23c-2 ..., 23c-n selects the output of look-up table and register, therefore feedback path 69-1,69-
2 ... 69-n can be regarded as the merging of 24-n and 47-n in Fig. 4.The change will not change the input terminal of each multiple selector
Number, caused advantageous effect is of equal value with Fig. 4, but the feedback path of register to subordinate's look-up table can pass through level-one multichannel more and select
Device 23c-1,23c-2 ... 23c-n is selected, compared with Fig. 4, a line, reduction 23a-1,23a-2 ... 23a-n are big reducing
While small, delay can increased.
Wherein, include per level-one cascade structure：One-out-three multiple selector, the single output look-up table of k inputs, the first alternative
Multiple selector, register and the second alternative multiple selector.
Wherein, in i-stage cascade structure (1≤i≤n)：One-out-three multiple selector, three of them input terminal are separately connected
It is a defeated to the output end of register in the output end, this grade of cascade structure of (i-1)-th grade of cascade structure and the k of this grade of cascade structure
Enter end [0:K-1] in input terminal 0；The single output look-up table of k inputs, k input terminal are respectively connected to the k of this grade of cascade structure
A input terminal [0:K-1] in 1~k-1 of input terminal and above-mentioned one-out-three multiple selector output end；First alternative multichannel
Selector, it is defeated that two input terminals are respectively connected to the output end of register and k in this grade of cascade structure in (i-1)-th grade of cascade structure
Enter the output end of single output look-up table；Register, input terminal are connected to the output end of above-mentioned first alternative multiple selector；
Second alternative multiple selector, two input terminals are respectively connected to k and input the output end and register for singly exporting look-up table
Output end, output end of the output end as this grade of cascade structure.
For the 1st grade of cascade structure, two input terminals in three input terminals of one-out-three multiple selector are separately connected
Input terminal k in this grade of cascade structure in k input terminal of the output end of register and this grade of cascade structure, one in addition are defeated
Enter to hold vacant, other external logic array blocks will be connected to.One in two input terminals of the first alternative multiple selector
A to be connected to this grade of single output look-up table of cascade structure k inputs, another input terminal is vacant, will be connected to other external logic arrays
Row block.
Specifically, the connection relation when needing to realize each function shown in Fig. 7 is as follows：
(a) when realizing " look-up table-register " structure shown in (a) in Fig. 7, single cascade structure can be realized, with
In Fig. 6 for i-stage, the first alternative multiple selector 23b-i selects the second input terminal, and (k inputs are single in this grade of cascade structure
Export the output end of look-up table 21-i), the second alternative multiple selector 23c-i selects the second input terminal (in this cascade structure
The output end of register 22-i), the function is unrelated with the strobe case of one-out-three multiple selector 23a-i.
(b) when realizing " register-look-up table " structure shown in (b) in Fig. 7, single concatenation structure can be realized, with
In Fig. 6 for i-stage, one-out-three multiple selector 23a-i selects the second input terminal (register 22-i in this grade of cascade structure
Output end), the first alternative multiple selector 23b-i selection first input end (register 22- (i- in (i-1)-th grade of cascade structure
1) output end), the second alternative multiple selector 23c-i selections first input end (this grade of single output look-up table 21-i of k inputs
Output end).
(c) when realizing " look-up table-look-up table " structure shown in (c) in Fig. 7, with look-up table 21- (i-1) in Fig. 6,
For 21-i, the one-out-three multiple selector 23a-i selection first input end of i-stage cascade structure be ((i-1)-th grade of cascade structure
Output end, that is, feedback path 69- (i-1)), the second alternative multiple selector 23c- (i-1) choosings of (i-1)-th grade of cascade structure
Select first input end (output end of the single output look-up table 21- (i-1) of (i-1)-th grade of k input), the 2nd 2 of i-stage cascade structure the
Select a multiple selector 23c-i selections first input end (output end of the single output look-up table 21-i of i-stage k inputs), the function
It is unrelated with the strobe case of other multiple selector.
(d) when realizing " register-register " structure shown in (d) in Fig. 7, with register 22- (i-1) in Fig. 6,
For 22-i, the first alternative multiple selector 23b-i of i-stage cascade structure selects first input end ((i-1)-th grade of level link
The output end of register 22- (i-1) in structure), the second alternative multiple selector 23c-i selections second of i-stage cascade structure
Input terminal (output end of register 22-i in i-stage cascade structure), the strobe cases of the function and other multiple selector without
It closes.
(e) when realizing " look-up table-register-look-up table " structure shown in (e) in Fig. 7, n grades of cascades in Fig. 6 are needed
The cascade structure of (i-1)-th grade in structure and i-stage is arranged in the following way：
For (i-1)-th grade of cascade structure：The strobe case of one-out-three multiple selector 23a- (i-1) and this function without
It closes；First alternative multiple selector 23b- (i-1) selects the second input terminal, i.e., k is inputted in this grade ((i-1)-th grade) cascade structure
The output end of single output look-up table 21- (i-1)；Second alternative multichannel 23c- (i-1) the second input terminals of selection, i.e. this grade (the
I-1 grades) output end of register 22- (i-1) in cascade structure.
For the cascade structure of i-stage：One-out-three multiple selector 23a-i selects first input end, i.e., (i-1)-th grade cascade
The output end 69- (i-1) of structure；The strobe case of first alternative multiple selector 23b-i is unrelated with this function；Two or two choosing
One multiple selector 23c-i selects first input end, i.e., the output end of this grade single output look-up table 21-i of k inputs.
(f) when realizing " register-look-up table-register " structure shown in (e) in Fig. 7, n grades of cascades in Fig. 6 are needed
The cascade structure of (i-1)-th grade in structure and i-stage is arranged in the following way：
For (i-1)-th grade of cascade structure：The strobe case of one-out-three multiple selector 23a- (i-1) and this function without
It closes；The strobe case of first alternative multiple selector 23b- (i-1) is unrelated with this function；Second alternative multiple selector
23c- (i-1) selects the second input terminal, i.e., the output end of register 22- (i-1) in this grade ((i-1)-th grade) cascade structure.
For i-stage cascade structure：One-out-three multiple selector 23a-i selects first input end, i.e. (i-1)-th grade of level link
The output end 69- (i-1) of structure；First alternative multiple selector 23b-i selects the second input terminal, i.e. k in this grade of cascade structure
The output end of the single output look-up table 21-i of input；Second alternative multiple selector 23c-i selects the second input terminal, i.e. this grade of grade
It is coupled the output end of register 22-i in structure.
So far, attached drawing is had been combined three embodiments of the invention are described in detail.According to above description, this field skill
Art personnel should have clear understanding to FPGA logic cell of the present invention with feedback path.
In addition, the above-mentioned definition to each element and method is not limited in the various concrete structures mentioned in embodiment, shape
Shape or mode, those of ordinary skill in the art simply can be changed or replaced to it, such as：The present invention not by LE number n,
The limitation of look-up table output end number k and LAB input terminal number m.
In conclusion the present invention on the basis of existing structure, increases higher level's cascade structure to subordinate's cascade structure
Feedback path is increased by a little area, can be real inside logic unit under the premise of without using input multiple selector
Existing various logic function reduces critical path delay, increases the flexibility ratio of eda tool mapping, vanning, has high answer
With value.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical solution and advantageous effect
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in the guarantor of the present invention
Within the scope of shield.
Claims (12)
1. a kind of FPGA logic cell with feedback path, which is characterized in that including：N grades of cascade structure, the cascade per level-one
Structure includes：The single output look-up table of k inputs and register；
Wherein, in n grades of the cascade structure, the cascade structure of upper level is to having feedback road between the cascade structure of next stage
Diameter, n >=2；
Wherein, the i-stage cascade structure of n grades of the cascade structure includes：Four select a multiple selector, the single output of k inputs to look into
Look for table, the first alternative multiple selector, register and the second alternative multiple selector：
Described four select a multiple selector, and two input terminals in four input terminals are respectively connected to post in this grade of cascade structure
The k input terminal [0 of the output end of storage and this grade of cascade structure:K-1] in input terminal 0；
The single output look-up table of k inputs, k input terminal are respectively connected to the k input terminal [0 of this grade of cascade structure:k-1]
In 1~k-1 of input terminal and described four select the output end of a multiple selector；
The first alternative multiple selector, an input terminal in two input terminals are connected to the single output of k inputs and look into
Look for the output end of table；
The register, input terminal are connected to the output end of the first alternative multiple selector；
The second alternative multiple selector, two input terminals are respectively connected to the output of the single output look-up table of k inputs
The output end at end and the register, output end of the output end as this grade of cascade structure；
Wherein, 1≤i≤n, the feedback path are that k inputs are single defeated in register to subordinate's cascade structure in higher level's cascade structure
Go out the feedback path of look-up table.
2. FPGA logic cell according to claim 1, which is characterized in that as i ≠ 1：
Described four select the another two input terminal in a multiple selector in addition to described two input terminals to be respectively connected to (i-1)-th grade
K inputs list exports the output end of register in the output end of look-up table, (i-1)-th grade of cascade structure in cascade structure；
Another input terminal in the first alternative multiple selector in addition to one input terminal is connected to (i-1)-th grade
The output end of register in cascade structure.
3. FPGA logic cell according to claim 2, which is characterized in that (i-1)-th grade in the n grades of cascade structure and
The cascade structure of i-stage is arranged in the following way, realizes " look-up table-register-look-up table " structure：
For (i-1)-th cascade structure：The first alternative multiple selector selects the single output of k inputs in this grade of cascade structure
The output end of look-up table；
For the cascade structure of i-stage：Described four select the output of register in a multiple selector (i-1)-th grade of cascade structure of selection
End；The second alternative multiple selector selects the output end of the single output look-up table of k inputs in this grade of cascade structure.
4. FPGA logic cell according to claim 2, which is characterized in that (i-1)-th grade and in the n grades of cascade structure
I grades of cascade structure is arranged in the following way, realizes " register-look-up table-register " structure：
For the cascade structure of i-stage：Described four select the output of register in a multiple selector (i-1)-th grade of cascade structure of selection
End；The first alternative multiple selector selects the output end of the single output look-up table of k inputs in this grade of cascade structure；Described
Two alternative multiple selector select the output end of register in this grade of cascade structure.
5. a kind of FPGA logic cell with feedback path, which is characterized in that including：N grades of cascade structure, the cascade per level-one
Structure includes：The single output look-up table of k inputs and register；
Wherein, in n grades of the cascade structure, the cascade structure of upper level is to having feedback road between the cascade structure of next stage
Diameter, n >=2；
Wherein, the i-stage cascade structure of n grades of the cascade structure includes：First one-out-three multiple selector, k inputs are single defeated
Go out look-up table, the second one-out-three multiple selector, register and alternative multiple selector：
The first one-out-three multiple selector, two in three of them input terminal are respectively connected to deposit in this grade of cascade structure
The k input terminal [0 of the output end of device and this grade of cascade structure:K-1] in input terminal 0；
The single output look-up table of k inputs, k input terminal are respectively connected to the k input terminal [0 of this grade of cascade structure:k-1]
In 1~k-1 of input terminal and the first one-out-three multiple selector output end；
The second one-out-three multiple selector is looked into thirdly an input terminal in input terminal is connected to the single output of k inputs
Look for the output end of table；
The register, input terminal are connected to the output end for stating the second one-out-three multiple selector；
The alternative multiple selector, two input terminals be respectively connected to the single output look-up table of k input output end and
The output end of the register, output end of the output end as this grade of cascade structure；
The feedback path is the feedback of register in the single output look-up table to subordinate's cascade structure of k inputs in higher level's cascade structure
Path.
6. FPGA logic cell according to claim 5, which is characterized in that as i ≠ 1：
Another input terminal in the first one-out-three multiple selector in addition to described two input terminals is connected to (i-1)-th grade of grade
It is coupled the output end of the single output look-up table of k inputs in structure；
Another two input terminal of the second one-out-three multiple selector in addition to one input terminal is respectively connected to (i-1)-th
The single output end for exporting look-up table of k inputs in the output end of register, (i-1)-th grade of cascade structure in grade cascade structure.
7. FPGA logic cell according to claim 6, which is characterized in that (i-1)-th grade in the n grades of cascade structure and
The cascade structure of i-stage is arranged in the following way, realizes " look-up table-register-look-up table " structure：
For the cascade structure of i-stage：The first one-out-three multiple selector selects the defeated of register in this grade of cascade structure
Outlet；The second one-out-three multiple selector selects the output end of the single output look-up table of k inputs in (i-1)-th grade of cascade structure；
The alternative multiple selector selects the output end of the single output look-up table of k inputs in this grade of cascade structure.
8. FPGA logic cell according to claim 6, which is characterized in that (i-1)-th grade in the n grades of cascade structure and
The cascade structure of i-stage is arranged in the following way, realizes " register-look-up table-register " structure：
For (i-1)-th grade of cascade structure：The first one-out-three multiple selector selects register in this grade of cascade structure
Output end；The second one-out-three multiple selector select the single output look-up table of the input of k in this grade of cascade structure output end it
One of outer another two input terminal；
For the cascade structure of i-stage：The second one-out-three multiple selector selects k inputs in (i-1)-th grade of cascade structure single
Export the output end of look-up table；The alternative multiple selector selects the output end of register in this grade of cascade structure.
9. a kind of FPGA logic cell with feedback path, which is characterized in that including：N grades of cascade structure, the cascade per level-one
Structure includes：The single output look-up table of k inputs and register；
Wherein, in n grades of the cascade structure, the cascade structure of upper level is to having feedback road between the cascade structure of next stage
Diameter, n >=2；
Wherein, the i-stage cascade structure of n grades of the cascade structure includes：One-out-three multiple selector, the single output of k inputs are looked into
Look for table, the first alternative multiple selector, register and the second alternative multiple selector：
The one-out-three multiple selector, two input terminals in three of them input terminal are respectively connected to post in this grade of cascade structure
The k input terminal [0 of the output end of storage and this grade of cascade structure:K-1] in input terminal 0；
The single output look-up table of k inputs, k input terminal are respectively connected to the k input terminal [0 of this grade of cascade structure:K-1] in
The output end of 1~k-1 of input terminal and the one-out-three multiple selector；
First alternative multiple selector, it is single defeated that an input terminal in two input terminals connects k inputs in this grade of cascade structure
Go out the output end of look-up table；
Register, input terminal are connected to the output end of the first alternative multiple selector；
Second alternative multiple selector, two input terminals be respectively connected to the single output look-up table of k input output end and
The output end of the register, output end of the output end as this grade of cascade structure；
Wherein, the feedback path is output to k inputs list in subordinate's cascade structure for higher level's cascade structure and exports the anti-of look-up table
Feeder diameter.
10. FPGA logic cell according to claim 9, which is characterized in that as i ≠ 1：
Another input terminal in the one-out-three multiple selector in addition to described two input terminals is connected to (i-1)-th grade of level link
The output end of structure；
Another input terminal of the first alternative multiple selector in addition to one input terminal is connected to (i-1)-th grade of cascade
The output end of register in structure.
11. FPGA logic cell according to claim 10, which is characterized in that (i-1)-th grade in the n grades of cascade structure
It is arranged in the following way with the cascade structure of i-stage, realizes look-up table-register-look-up table " structure：
For (i-1)-th grade of cascade structure：The first alternative multiple selector selects k inputs in this grade of cascade structure single defeated
Go out the output end of look-up table；The second alternative multiple selector selects the output end of register in this grade of cascade structure；
For the cascade structure of i-stage：The one-out-three multiple selector selects the output end of (i-1)-th grade of cascade structure；It is described
Second alternative multiple selector selects the output end of this grade of single output look-up table of k inputs.
12. FPGA logic cell according to claim 10, which is characterized in that (i-1)-th grade in the n grades of cascade structure
It is arranged in the following way with the cascade structure of i-stage, realizes " register-look-up table-register " structure：
For (i-1)-th grade of cascade structure：The second alternative multiple selector selects register in this grade of cascade structure
Output end；
For i-stage cascade structure：The one-out-three multiple selector selects the output end of (i-1)-th grade of cascade structure；Described
One alternative multiple selector selects the output end of the single output look-up table of k inputs in this grade of cascade structure；Second alternative
Multiple selector selects the output end of register in this grade of cascade structure.
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| US7663400B1 (en) * | 2007-12-21 | 2010-02-16 | Actel Corporation | Flexible carry scheme for field programmable gate arrays |
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