CN105629250A - Underwater three-dimensional real scene real-time imaging system - Google Patents
Underwater three-dimensional real scene real-time imaging system Download PDFInfo
- Publication number
- CN105629250A CN105629250A CN201610193699.7A CN201610193699A CN105629250A CN 105629250 A CN105629250 A CN 105629250A CN 201610193699 A CN201610193699 A CN 201610193699A CN 105629250 A CN105629250 A CN 105629250A
- Authority
- CN
- China
- Prior art keywords
- module
- data
- underwater
- fpga
- mainboard
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
- G01S15/88—Sonar systems specially adapted for specific applications
- G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
Landscapes
- Engineering & Computer Science (AREA)
- Radar, Positioning & Navigation (AREA)
- Remote Sensing (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Physics & Mathematics (AREA)
- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
Abstract
The invention relates to an underwater three-dimensional real scene real-time imaging system. The underwater three-dimensional real scene real-time imaging system is composed of 48 daughter boards, a mother board and a PC main control machine; the PC main control machine is connected with the mother board through a Gigabit Ethernet; and the mother board is connected with the 48 daughter boards through an LVDS; each daughter board is composed of an output amplifier, a 4-path power amplifier, an AD converter, a DA converter and a peripheral circuit. According to the underwater three-dimensional real scene real-time imaging system of the invention, based on an optimized beam forming algorithm, a large-scale FPGA array is utilized, and therefore, the problems of sampling of a large quantity of transducer signals and massive data parallel computation can be solved. The system has a bright application prospect in aspects such as dam underwater part monitoring, harbor wall inspection, underwater engineering implementation, submarine pipeline inspection, obstacle avoidance and navigation of underwater vehicles.
Description
Technical field
The present invention relates to 3D stereo projection technology field, specifically refer to a kind of underwater 3 D scene Real Time Image System.
Background technology
In recent years, along with people to the continuous demand of oceanic resources and exploitation, underwater exploration technology obtains develop rapidly. The main detection means of ocean is sound wave by people, i.e. sonar technique. Therefore, utilize sonar to carry out emphasis problem that underwater exploration becomes current ocean research. But, major part sonar system is all determine whether sonar target by sound wave, and the azimuth-range of target. At present, in benthal three-dimensional sonar imaging technique, certain achievement has been achieved both at home and abroad; Such as: a new generation numeral sonar SeaBat8125 of RESoN company of U.S. exploitation, the three-dimensional sonar of Echoscope series of the European Economic Community and Norway's joint development, the three-dimensional looking forward sonar of two Farsounder company exploitations frequently identifying sonar and the U.S. of the ocean industrial exploitation of the U.S.; But these sonograms technology are mostly based on two-dimensional map 3-D view, or three-dimensional imaging at a slow speed among a small circle, imaging effect is not good, and real-time is too poor.
Summary of the invention
For above-mentioned the deficiencies in the prior art, the invention reside in and a kind of underwater 3 D scene Real Time Image System is provided, it is possible to the above-mentioned prior art Problems existing of effective solution.
The technical scheme of the present invention is:
A kind of underwater 3 D scene Real Time Image System, comprises and being made up of 48 blocks of sub-plates, mainboard and PC master control machine; Described PC master control machine is connected with mainboard by gigabit Ethernet, and 48 blocks of sub-plates are connected respectively by LVDS for described mainboard; Described sub-plate is made up of transmitting amplifier, No. 4 power amplifiers, a/d converter, D/A converter and peripheral circuit; Described mainboard is made up of embedded processing device, FPGAXC3S1200E and 4 FPGAXC5VSX95T and peripheral circuit;
Also comprising system FPGA functional design module, described system FPGA functional design module comprises sub-plate FPGA design module, mainboard High Performance FPGA Design module and mainboard interface FPGA design module; Described sub-plate FPGA design module comprises A/D controlling of sampling module, data processing module, data conversion and the module that communicates of sending module and master signal disposable plates; Described mainboard interface FPGA design module comprises transponder pulse signal module, sub-plate START signal module, data merge transmission look-at-me module and difference signal changes into single-ended signal module;
Also comprise PowerPC system software framework and real-time visual indicating system; Described PowerPC system software framework comprises built-in Linux operating system, the exploitation of system start-up code, Driver Development and application development; Described real-time visual indicating system comprises data module, three-dimensional modeling module, parameter control module and display module; Described data module comprises network reception module, data memory module and digital independent module; Described three-dimensional modeling module comprises single frame matching module, accuracy registration module and image mosaic module; Described parameter control module comprises sonar control module, algorithm management module and display mode control module; Described display module comprises single frame display module and overall situation display module.
Further, described every block plate is provided with 48 Signal reception passages.
Further, the amplitude of acoustic signal and phase place information are carried out synchronous A/D sampling and sampled-data processing by described control A/D sampling A/D chip, and by low-voltage differential signal interface by data upload mainboard.
Further, Wave beam forming summarized results is passed through gigabit Ethernet port transmission to PC master control machine by described mainboard.
Further, described mainboard High Performance FPGA Design modules acquiring data is averagely allocated to 4 pieces of FPGA and synchronously carries out processing and calculate, and completes Wave beam forming by data interaction each other.
Further, described FPGAXC5VSX95T receives, by LVDS interface, the data that 12 blocks of sub-plates upload, and by high-speed-differential, data line is carried out data interaction each other.
Further, the data that described mainboard interface FPGA is responsible for uploading 4 mainboard high-performance FPGA merge, and are convenient to PowerPC and read. PowerPC controls FPGA and generates pulse signal, and drive system launches acoustic signal, and controls sub-plate by FPGA and start image data. Data summarization generates look-at-me after completing, and PowerPC reads data according to look-at-me.
The advantage of the present invention: the present invention, based on the beamforming algorithm after optimization, utilizes large-scale F PGA array, solves the problem of the sampling of a large amount of transducer signal and mass data parallel computation preferably. This system is with a wide range of applications in the avoidance and navigation etc. of the monitoring of dam underwater portion, harbour wall inspection, underwater engineering enforcement, submerged pipeline inspection, submarine navigation device; And do further improvement in raising system performance and reduction system power dissipation.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, it is briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings;
Fig. 1 is the structural representation of the present invention;
Fig. 2 is the present invention's sub-plate hardware function block diagram;
Fig. 3 is the present invention's sub-plate FPGA workflow schematic diagram;
Fig. 4 is Virtex-5 workflow schematic diagram of the present invention;
Fig. 5 is DDR2 controller data flow diagram of the present invention;
Fig. 6 is interface FPGA workflow schematic diagram of the present invention;
Fig. 7 is PowerpPC system software framework schematic diagram of the present invention;
Fig. 8 is real-time visual indicating system software function diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are described in detail, so that advantages and features of the invention can be easier to be readily appreciated by one skilled in the art, thus protection scope of the present invention are made more explicit defining:
With reference to figure 1, a kind of underwater 3 D scene Real Time Image System, comprises and being made up of 48 blocks of sub-plates, mainboard and PC master control machine; Described PC master control machine is connected with mainboard by gigabit Ethernet, and 48 blocks of sub-plates are connected respectively by LVDS for described mainboard; Described sub-plate is made up of transmitting amplifier, No. 4 power amplifiers, a/d converter, D/A converter and peripheral circuit; Described mainboard is made up of embedded processing device, FPGAXC3S1200E and 4 FPGAXC5VSX95T and peripheral circuit;
Also comprising system FPGA functional design module, described system FPGA functional design module comprises sub-plate FPGA design module, mainboard High Performance FPGA Design module and mainboard interface FPGA design module; Described sub-plate FPGA design module comprises A/D controlling of sampling module, data processing module, data conversion and the module that communicates of sending module and master signal disposable plates; Described mainboard interface FPGA design module comprises transponder pulse signal module, sub-plate START signal module, data merge transmission look-at-me module and difference signal changes into single-ended signal module;
Also comprise PowerPC system software framework and real-time visual indicating system; Described PowerPC system software framework comprises built-in Linux operating system, the exploitation of system start-up code, Driver Development and application development; Described real-time visual indicating system comprises data module, three-dimensional modeling module, parameter control module and display module; Described data module comprises network reception module, data memory module and digital independent module; Described three-dimensional modeling module comprises single frame matching module, accuracy registration module and image mosaic module; Described parameter control module comprises sonar control module, algorithm management module and display mode control module; Described display module comprises single frame display module and overall situation display module.
Described every block plate is provided with 48 Signal reception passages.
The amplitude of acoustic signal and phase place information are carried out synchronous A/D sampling and sampled-data processing by described control A/D sampling A/D chip, and by low-voltage differential signal interface by data upload mainboard.
Wave beam forming summarized results is passed through gigabit Ethernet port transmission to PC master control machine by described mainboard.
Described mainboard High Performance FPGA Design modules acquiring data is averagely allocated to 4 pieces of FPGA and synchronously carries out processing and calculate, and completes Wave beam forming by data interaction each other.
Described FPGAXC5VSX95T receives, by LVDS interface, the data that 12 blocks of sub-plates upload, and by high-speed-differential, data line is carried out data interaction each other.
The data that described mainboard interface FPGA is responsible for uploading 4 mainboard high-performance FPGA merge, and are convenient to PowerPC and read. PowerPC controls FPGA and generates pulse signal, and drive system launches acoustic signal, and controls sub-plate by FPGA and start image data. Data summarization generates look-at-me after completing, and PowerPC reads data according to look-at-me.
As shown in Figure 1, it is made up of 48 blocks of sub-plates, mainboard and master control PC. Sub-plate charge completion signal acquisition function, mainboard has been responsible for Wave beam forming and data summarization, and the function realizing the controlling of sampling of antithetical phrase plate and communicating with master control PC, finally on master control PC, complete real time three-dimensional imaging. Wherein, every block plate has 48 Signal reception passages;
Sub-plate data gathering function is as shown in Figure 2. First the faint electrical signal received from transverter is nursed one's health by each passage, by signal by after the neighbourhood noise of a Hi-pass filter filtering medium and low frequency, again through a second-order bandpass filter, to realize making more than signal attenuation 20dB when frequency input signal is greater than 570kHz, ensure that effective signal scope 270kHz ~ 330kHz (considering the Doppler shift frequency of underwater sound signal) decay is less than 3dB simultaneously. Then under outside homology clock drives, Spartan-3E controls A/D sampling A/D chip and the amplitude of acoustic signal and phase place information carries out synchronous A/D sampling and sampled-data processing, and by low-voltage differential signal (Low-voltageDifferentialSignaling, LVDS) interface by data upload mainboard. Simultaneously, Spartan-3E sends data by Serial Peripheral Interface (SPI) (SerialPeripheralInterface, SPI) to D/A transmodulator, exports temporal gain (TimeVariationofGain after conversion, TVG) control signal, to control sampled signal compression ratio.
As shown in Figure 3, in sub-plate FPGA, A/D controlling of sampling module reads data from 48 channel serial, and point existence 6 sizes are in the dual port RAM of 6KB. Data processing module presses channel sequence, reads 24 sampling points successively, and sampling data are carried out DFT calculating, calculate the DFT value that a frequency is 300kHz from 6 RAM. Data conversion and sending module are pressed channel sequence and are read DFT calculation result, single-ended signal are changed into difference signal, by LVDS interface by data upload. FPGA sends data by SPI interface to D/A transmodulator simultaneously, and the analog signal output TVG control signal after conversion, to control sampled signal compression ratio.
Every block Virtex-5 stores after receiving data from 12 blocks of sub-plates as shown in Figure 4. One-level Wave beam forming module reads data from data memory module, calculates the wave beam forming 12 linear battle arrays in one direction, and data is stored. The intermediate data of one-level Wave beam forming has 1/4 result to be retained, and data line 3/4 is passed to other 3 pieces of Virtex-5 by self-defined high-speed-differential by other, and every block Virtex-5 obtains middle wave beam from other 3 pieces of Virtex-5 simultaneously. Wave of the second order bundle forms module and reads data from intermediate data memory module, calculates the wave beam forming 12 linear battle arrays in the other directions. Every block Virtex-5 completes 32 �� 128 Wave beam forming altogether. Final data, through DDR2 buffer memory, is transferred to mainboard interface FPGA by 2 pairs of difference transmission lines.
Data stream is as shown in Figure 5. DDR2_WR module reads the Wave beam forming result of 12 blocks of sub-plates in a certain order from write data FIFO, and according in the sequencing write DDR2 read, reads data FIFO and read data from DDR2 in the gap writing DDR2 operation.
The data that mainboard interface FPGA is responsible for uploading 4 mainboard high-performance FPGA merge, and are convenient to PowerPC and read. PowerPC controls FPGA and generates pulse signal, and drive system launches acoustic signal, and controls sub-plate by FPGA and start image data. Data summarization generates look-at-me after completing, and PowerPC reads data according to look-at-me. Concrete workflow journey is as shown in Figure 6.
As shown in Figure 7, system architecture is divided into 3 levels to system architecture: (1) completes system Bootloader exploitation, and file system mirror, booting script etc. (2) develop 1000 mbit ethernets drivings on an operating system, TVG drives, FPGA drives, clock drives. (3) application program realize communicating with the data interaction such as master control PC and mainboard, data processing, network, command interaction, TVG control, optimum configurations, code update, the function such as clock transfer;
Whole functions of real-time visual indicating system can be divided into altogether 4 parts, as shown in Figure 8, data are directly carried out real-time visual process by data that data module is uploaded by network reception phased array on the one hand, preserve data for processed offline on the other hand. Three-dimensional modeling module is the main functional modules of native system, and single frame coupling is that consecutive point connect into triangle face sheet, makes point set form topological framework [11]. Accuracy registration adopts contiguous some iteration (IteratedClosestPoint, ICP) algorithm that point set is placed in more suitable position [12]. Image mosaic makes the new frame of input and old frame be fused into the more complete image of a frame. Respectively three-dimensional modeling module and display module are carried out state modulator at parameter control module. Display module is displayed in wicket by list frame matching result, is displayed in big window by global registration and splicing result, and each window all has and shows function alternately. Wherein, parameter control module comprises sonar control, algorithm management and display mode control. Sonar control comprises measures range and drainage pattern control, and algorithm management comprises registration precision and splicing resolving power control, and display mode comprises scheme of colo(u)r and frame per second control.
The present invention is first, system that employs the simulated annealing after optimization, to each transverter distribution weight coefficient on two dimensional planes, when maximum secondary lobe can accept, the weight coefficient of part transverter can be assigned as 0, namely reach transverter sparseization, reduce the effect of system operations amount. Finally realize the acoustic signal receiving plane battle array of the individual transverter composition of system 2304 (48 �� 48).
Simultaneously, this system adopts the substep beamforming algorithm after optimizing, the acoustic signals of space incidence is carried out spatial decomposition, phase shift parameters is optimized, thus reduce phase shift parameters storage area, and acoustic signal receiving plane battle array is divided into 48 linear submatrixs, grouping parallel realizes substep Wave beam forming, finally completes 128 �� 128 Wave beam forming.
Have the characteristics such as data bit width configurability, multi-stage pipeline process and inner integrated a large amount of digital signal processing unit (DSPSlices) due to FPGA, therefore the operation efficiency of FPGA in signal processing is much larger than the operation efficiency of digital signal processor (DSP). In order to accomplish real-time mass data processing, system that employs the system design based on FPGA platform, utilize FPGA that data are carried out parallel processing, and complete Wave beam forming by the data interaction between array.
The standardized parts that the present invention uses all can be commercially, shaped piece all can carry out customized according to the record with accompanying drawing of specification sheets, the concrete mode of connection of each part all adopts the conventional meanses such as bolt ripe in prior art, rivet, welding, machinery, part and equipment all adopt in prior art, conventional model, add that circuit connects and adopt mode of connection conventional in prior art, be not described in detail in this.
The foregoing is only the better embodiment of the present invention, all impartial changes done according to the present patent application patent scope, with modifying, all should belong to the covering scope of the present invention.
Claims (7)
1. a underwater 3 D scene Real Time Image System, it is characterised in that: comprise and being made up of 48 blocks of sub-plates, mainboard and PC master control machine; Described PC master control machine is connected with mainboard by gigabit Ethernet, and 48 blocks of sub-plates are connected respectively by LVDS for described mainboard; Described sub-plate is made up of transmitting amplifier, No. 4 power amplifiers, a/d converter, D/A converter and peripheral circuit; Described mainboard is made up of embedded processing device, FPGAXC3S1200E and 4 FPGAXC5VSX95T and peripheral circuit;
Also comprising system FPGA functional design module, described system FPGA functional design module comprises sub-plate FPGA design module, mainboard High Performance FPGA Design module and mainboard interface FPGA design module; Described sub-plate FPGA design module comprises A/D controlling of sampling module, data processing module, data conversion and the module that communicates of sending module and master signal disposable plates; Described mainboard interface FPGA design module comprises transponder pulse signal module, sub-plate START signal module, data merge transmission look-at-me module and difference signal changes into single-ended signal module;
Also comprise PowerPC system software framework and real-time visual indicating system; Described PowerPC system software framework comprises built-in Linux operating system, the exploitation of system start-up code, Driver Development and application development; Described real-time visual indicating system comprises data module, three-dimensional modeling module, parameter control module and display module; Described data module comprises network reception module, data memory module and digital independent module; Described three-dimensional modeling module comprises single frame matching module, accuracy registration module and image mosaic module; Described parameter control module comprises sonar control module, algorithm management module and display mode control module; Described display module comprises single frame display module and overall situation display module.
2. a kind of underwater 3 D scene Real Time Image System according to claim 1, it is characterised in that: described every block plate is provided with 48 Signal reception passages.
3. a kind of underwater 3 D scene Real Time Image System according to claim 1, it is characterized in that: the amplitude of acoustic signal and phase place information are carried out synchronous A/D sampling and sampled-data processing by described control A/D sampling A/D chip, and by low-voltage differential signal interface by data upload mainboard.
4. a kind of underwater 3 D scene Real Time Image System according to claim 1, it is characterised in that: Wave beam forming summarized results is passed through gigabit Ethernet port transmission to PC master control machine by described mainboard.
5. a kind of underwater 3 D scene Real Time Image System according to claim 1, it is characterized in that: described mainboard High Performance FPGA Design modules acquiring data is averagely allocated to 4 pieces of FPGA and synchronously carries out processing and calculate, and completes Wave beam forming by data interaction each other.
6. a kind of underwater 3 D scene Real Time Image System according to claim 1, it is characterised in that: described FPGAXC5VSX95T receives, by LVDS interface, the data that 12 blocks of sub-plates upload, and by high-speed-differential, data line is carried out data interaction each other.
7. a kind of underwater 3 D scene Real Time Image System according to claim 1, it is characterized in that: the data that described mainboard interface FPGA is responsible for uploading 4 mainboard high-performance FPGA merge, it is convenient to PowerPC read, PowerPC controls FPGA and generates pulse signal, drive system launches acoustic signal, and control sub-plate by FPGA and start image data, data summarization generates look-at-me after completing, and PowerPC reads data according to look-at-me.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610193699.7A CN105629250A (en) | 2016-03-31 | 2016-03-31 | Underwater three-dimensional real scene real-time imaging system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610193699.7A CN105629250A (en) | 2016-03-31 | 2016-03-31 | Underwater three-dimensional real scene real-time imaging system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105629250A true CN105629250A (en) | 2016-06-01 |
Family
ID=56044365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610193699.7A Pending CN105629250A (en) | 2016-03-31 | 2016-03-31 | Underwater three-dimensional real scene real-time imaging system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105629250A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000041162A1 (en) * | 1998-12-31 | 2000-07-13 | General Electric Company | Method and apparatus for distributed, agile calculation of beamforming time delays and apodization values |
| CN101098179A (en) * | 2006-06-30 | 2008-01-02 | 中国科学院声学研究所 | Method for forming broadband frequency domain digital beam |
| CN101236249A (en) * | 2008-03-03 | 2008-08-06 | 哈尔滨工程大学 | Signal treating system for lens sonar |
| CN101625412A (en) * | 2009-08-03 | 2010-01-13 | 浙江大学 | Benthal three-dimensional sonar image imaging system based on multi-FPGA parallel processing |
| CN102096069A (en) * | 2010-12-17 | 2011-06-15 | 浙江大学 | Real-time processing system and method for phased array three-dimensional acoustic camera sonar |
-
2016
- 2016-03-31 CN CN201610193699.7A patent/CN105629250A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000041162A1 (en) * | 1998-12-31 | 2000-07-13 | General Electric Company | Method and apparatus for distributed, agile calculation of beamforming time delays and apodization values |
| CN101098179A (en) * | 2006-06-30 | 2008-01-02 | 中国科学院声学研究所 | Method for forming broadband frequency domain digital beam |
| CN101236249A (en) * | 2008-03-03 | 2008-08-06 | 哈尔滨工程大学 | Signal treating system for lens sonar |
| CN101625412A (en) * | 2009-08-03 | 2010-01-13 | 浙江大学 | Benthal three-dimensional sonar image imaging system based on multi-FPGA parallel processing |
| CN102096069A (en) * | 2010-12-17 | 2011-06-15 | 浙江大学 | Real-time processing system and method for phased array three-dimensional acoustic camera sonar |
Non-Patent Citations (1)
| Title |
|---|
| 万华等: "水下三维场景实时成像系统", 《计算机工程》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1110709C (en) | High resolution submarine microgeomorphy-measuring sounding side scan sonar system and measuring method | |
| CN107449405B (en) | Novel submerged buoy data acquisition system | |
| US11333759B2 (en) | Embedded processor-based three-dimensional acoustic imaging real-time signal processing device | |
| CN101625412A (en) | Benthal three-dimensional sonar image imaging system based on multi-FPGA parallel processing | |
| CN206531959U (en) | Sonar system signal acquisition transmission control unit | |
| CN101344460A (en) | Underwater robot sensor fault diagnosis method and system | |
| CN110824483A (en) | Modular multi-beam imaging sonar | |
| CN101236249B (en) | Signal treating system for lens sonar | |
| CN102323584A (en) | A kind of autonomous anticollision device of AUV/UUV platform under water that is applicable to | |
| CN204203461U (en) | A kind of 3-D scanning acoustics imaging device | |
| CN104730529B (en) | A kind of underwater intelligent avoidance Sonar system and obstacle detection method | |
| CN104569484A (en) | Multi-input multi-output array type ultrasound anemometry system and method | |
| CN204347059U (en) | A kind of multiple-input and multiple-output arrayed ultrasonic wind measuring system | |
| CN104754249B (en) | A kind of signal processing system applied to Underwater Imaging sonar | |
| CN115019825A (en) | Sound channel digital twinning method, device and system for underground tunnel environment | |
| CN103364074A (en) | Infrasound monitoring system | |
| CN105629250A (en) | Underwater three-dimensional real scene real-time imaging system | |
| CN111722232B (en) | Multi-beam imaging sonar real-time signal processing device with three-dimensional positioning capability | |
| CN204788487U (en) | Marine environment field detection system | |
| CN204462385U (en) | A kind of acoustics seabed Range Measurement System | |
| CN109828265B (en) | Multi-beam broadband profile sonar and underwater robot | |
| CN105675721A (en) | Ultrasonic imaging testing device and system | |
| CN113126069B (en) | Forward-looking sonar signal processing hardware system based on ZYNQ | |
| CN112130115B (en) | Transformer micro-robot fish positioning imaging method based on narrow-band ultrasonic beam forming | |
| CN103557843A (en) | Compact underwater microtopography measurement apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160601 |
|
| RJ01 | Rejection of invention patent application after publication |