CN105611271A - Real-time stereo image generating system - Google Patents

Abstract

The invention discloses a real-time stereoscopic image generating system, which belongs to the technical field of image processing. The invention includes a multi-view point generation module, a cache module and a stereoscopic image synthesis module. The multi-view point generation module is composed of N parallel depth-based image rendering processing units, and generates N virtual view point images according to the original image and the disparity map information. The generated virtual viewpoint image data are respectively stored in N dual-port double-buffer units of the cache module. The stereoscopic image synthesis module reads the virtual viewpoint image data from the cache module, and synthesizes N virtual viewpoint images into a stereoscopic image, which is displayed on the lenticular autostereoscopic display. The invention utilizes the characteristics of FPGA supporting parallel and pipeline processing, improves the speed of stereoscopic image generation, and improves the real-time performance of system processing.

Description

A Real-time Stereoscopic Image Generation System

technical field

The invention belongs to the technical field of image processing, and more specifically relates to a real-time stereoscopic image generation system.

Background technique

Now 3D video applications have appeared in people's lives, and can be seen in entertainment, military, and medical fields. When viewing general stereoscopic video, people need to wear auxiliary equipment such as red-blue glasses or polarizing glasses, thereby limiting the popularization and application of stereoscopic video display technology. The so-called autostereoscopic display technology refers to a technology in which the viewer can perceive the three-dimensional effect by directly observing the display screen without any auxiliary equipment, that is, naked-eye 3D technology. Autostereoscopic display technology not only enables the viewer to obtain a three-dimensional sense, but also facilitates viewing. It has broad development prospects and is a current research hotspot.

The principle of autostereoscopic display technology based on lenticular grating is to place a lenticular grating in front of the display to display multiple images with parallax in a staggered manner on the display. When the viewer stands at a certain viewing position, the light emitted by the image pixels on the display is refracted through the lenticular grating and enters the human eye, so that the human eye can observe two different images. Lenticular gratings are widely used in the autostereoscopic display field because of their advantages such as good stereo effect, good optical performance and low cost.

The autostereoscopic display system mainly includes the steps of acquisition, encoding, transmission and display of video information. Existing autostereoscopic displays require information from multiple viewpoints on the display side, so that within the viewing range, the viewer can receive two images with parallax for the left and right eyes, and perceive the stereoscopic effect through fusion processing by the brain. The source of these multi-viewpoint information is a problem to be solved. If multiple cameras are used to collect images, the amount of information will increase sharply, and a better coding scheme needs to be designed. At the same time, it requires high transmission bandwidth and hardware requirements. The storage space requirement is large, so this solution is generally not advisable. In addition, the stereoscopic display system has high requirements on real-time performance, so that the viewer can see continuous and smooth video.

Contents of the invention

Aiming at the demand arising in the above-mentioned background technology, that is, how to generate a 3D image from a 2D image in real time, the present invention provides a real-time stereoscopic image generation system, including a multi-view point generation module, a cache module and a stereoscopic image synthesis module, wherein:

The multi-view generation module includes N parallel depth-based image rendering processing units, where N=x ² , x is a positive integer greater than 1, and each of the depth-based image rendering processing units generates a virtual image based on the original image and the disparity image. The viewpoint image is sent to the cache module, and at the same time, a signal indicating that the rendering of the virtual viewpoint image is completed is sent to the stereoscopic image synthesis module;

The cache module includes N parallel dual-port double-buffer units, respectively receiving and storing the N virtual viewpoint images generated by the multi-viewpoint generating module, wherein each dual-port double-buffer unit includes two depths for the virtual A dual-port RAM whose width and bit width of the viewpoint image are consistent with the color depth of the original image, and the two dual-port RAMs form a double buffer structure to realize a ping-pong operation, so as to realize pipeline processing of the virtual viewpoint image; and

The stereoscopic image synthesis module includes a pixel counter and a stereoscopic image generating unit. After the pixel counter receives the signal indicating that the drawing of the virtual viewpoint image is completed, the count is input to the cache module as an address, and the stereoscopic image generating unit Reading the virtual viewpoint image data stored in the storage unit whose address is the count is read from the cache module, and synthesizing the N virtual viewpoint images into one stereoscopic image for output.

Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:

According to the original image and disparity image information, DIBR technology is used to realize multi-viewpoint rendering, providing multi-viewpoint information for auto-stereoscopic display, reducing the transmission bandwidth, storage space and cost of the system;

Make full use of the characteristics of FPGA supporting parallel and pipeline processing, and use hardware to accelerate the pixel processing, greatly improving the system processing speed and improving the real-time performance of the system processing;

The applicability of the system is good. The way the system generates virtual viewpoint does not depend on the camera parameters and has wide applicability.

Experimental results show that: on the FPGA of the Spartan6 family XC6SLX150 model produced by Xilinx, the processing speed of the present invention is 8 times faster than the software matching speed of a PC whose processor is Intel Core i5.

Description of drawings

Fig. 1 is the hardware block diagram of real-time stereoscopic image generating system of the present invention;

Fig. 2 is the structural block diagram of DIBR processing unit of the present invention;

Fig. 3 is the functional block diagram of dual-port dual-buffer unit of the present invention;

Fig. 4 is a schematic diagram of the connection between the cache module and the stereoscopic image synthesis module of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

The embodiment of the present invention utilizes VHDL to implement on the FPGA of the Spartan6 family XC6SLX150 model of Xilinx Company, fully taps the parallelism of the FPGA, and applies it to multi-view point generation calculation and stereoscopic image synthesis of parallax in combination with pipeline technology and streaming media technology principles.

Fig. 1 shows the hardware block diagram of the real-time stereoscopic image generating system of the present invention. As shown in Figure 1, the real-time stereoscopic image generation system includes a multi-view point generation module, a cache module and a stereoscopic image synthesis module.

In the embodiment of the present invention, the multi-view generation module is composed of 9 parallel depth-image-based rendering (Depth-Image-BasedRendering, hereinafter referred to as DIBR) processing units DIBR_V1~DIBR_V9, which are used to generate 9 views according to the original image and the disparity image respectively. A virtual view point image with a resolution of 640×360, while sending signals hf_over1~hf_over9 (where DIBR_V1 sends hf_over1, DIBR_V2 sends hf_over2, and so on) to stereoscopic image synthesis The module's pixel counter. Among them, the original image (size is 640×360, color depth is 24 bits, R8G8B8) is any one of the left and right view images collected from the binocular camera; the disparity image (size is 640×360, 64 grayscale) is It is calculated from the original image through stereo matching, and its size is the same as the original image.

The cache module includes 9 parallel dual-port double-buffer units 1-9. The DIBR processing units DIBR_V1-DIBR_V9 generate a row of virtual viewpoint image data and respectively store them in the dual-port double-buffer units 1-9 of the cache module. The cache module sends the received virtual viewpoint image data to the stereoscopic image synthesis module.

The stereoscopic image synthesis module includes a pixel counter and a stereoscopic image generating unit. The pixel counter receives signals hf_over1~hf_over9. After all 9 signals arrive, the pixel counter starts to increase by 1 in each clock cycle of the virtual viewpoint image timing signal, and returns to zero when it reaches the maximum value. The range of change is 0~640×360 . The stereoscopic image generation unit reads the virtual viewpoint image data from the cache module, and synthesizes nine virtual viewpoint images with a color depth of 24 and a resolution of 640×360 into a stereoscopic image with a resolution of 1920×1080 (the color depth is 24 bit, R8G8B8). In the embodiment of the present invention, for a virtual viewpoint image whose size is width×height, the size of the composite image is (3×width)×(3×height).

Fig. 2 is a structural block diagram of the DIBR processing unit of the present invention. As shown in FIG. 2 , each DIBR processing unit includes a view mapping module, a hole mark cache module, a virtual view cache module and a hole filling module.

The viewpoint mapping module includes a coordinate calculation unit, a zbuf cache unit and a disparity lookup unit. Wherein, the coordinate calculation unit calculates the corresponding coordinate value (u0+dis ×n,v0), complete the mapping from the reference viewpoint to the virtual viewpoint row by row, and send the row_over signal indicating completion to the hole filling module when the mapping from the reference viewpoint to the virtual viewpoint of a row is completed, so as to notify the hole filling module that it can A new row of data is filled with holes.

The zbuf cache unit consists of two single-port RAMs with a capacity of 640 bits and a bit width of 6 bits (64 levels of disparity map grayscale, 6 bits representing the number of digits of the disparity map grayscale), which are used to store the results of the zbuffer algorithm. After the coordinate calculation unit calculates the coordinate result of a certain pixel point in the disparity map, it first reads and judges whether the unit whose address is the coordinate result in the zbuf cache unit already has a disparity record, and if so, writes the disparity record in the zbuf cache unit Compare with the disparity used in the current calculation, take the coordinates of the pixel with the smaller disparity as the source point coordinates of a pixel in the virtual viewpoint image, and record the calculation in the unit whose address is the coordinate result in the zbuf cache unit The disparity value to use. This process of the zbuffer algorithm can solve the occlusion problem during the pixel mapping calculation process.

The disparity lookup unit is composed of a ROM with a capacity of 64 (consistent with the pixel gray scale number 64 of the disparity map), which contains a disparity lookup table, which is used to complete the calculation from the disparity value to the disparity function, wherein the disparity value is It is the grayscale value of each pixel in the disparity map, ranging from 0 to 63; the offset value is an intermediate result involved in the calculation of virtual viewpoint generation, and is an integer, ranging from -12 to 12. Among them, 0 to 63 linearly correspond to above -12 to 12, for example, the corresponding offset value of the parallax value of 31 is 0. Since the offset value is proportional to the depth, the embodiment of the present invention puts the offset value instead of the depth value into the disparity lookup table, which can speed up calculation.

The coordinate calculation units of the 9 DIBR processing units of the multi-viewpoint generation module respectively calculate the original image, the four virtual viewpoint images on the left side of the original image, and the four virtual viewpoint images on the right side. According to the DIBR algorithm, the simplified equivalent formula (1) is obtained:

VIR_n(u0+DEEP(DIS(u0,v0))×n,v0)=ORI(u0,v0)(1)

Among them, VIR_n represents the pixel matrix (n=-4,-3,...,4) of the nth virtual viewpoint image, ORI (u0, v0) represents the pixel matrix of the original image; the original image n=0, the original image is adjacent m virtual view point images on the left side n=-1～-m, y virtual view point images n=1～m on the right adjacent to the original image, m is an integer, when N is an odd number, m=(N-1)/2 , when N is an even number, m=N/2, in the embodiment of the present invention, the first virtual viewpoint image n=-1 on the left adjacent to the original image, and the first virtual viewpoint image n=-1 on the adjacent right side of the original image 1; the second virtual viewpoint image n=-2 on the left adjacent to the original image, and the second virtual viewpoint image n=2 on the adjacent right side of the original image; ... and so on, it can be known that the leftmost among the nine virtual viewpoint images n=-4 of the virtual viewpoint image, and n=4 of the rightmost virtual viewpoint image; u0 and v0 are the horizontal and vertical coordinates of pixels in the original image respectively; DEEP represents a disparity lookup table, DIS represents a disparity map, and DIS(u0, v0) represents the parallax value of the coordinate point (u0, v0), and DEEP(DIS(u0, v0)) represents the depth value of the coordinate point (u0, v0). For example, for the leftmost virtual viewpoint image, there are:

VIR_-4(u0+DEEP(DIS(u0,v0))×(-4),v0)=ORI(u0,v0)

The value of some points in the pixel matrix of the virtual viewpoint image is not determined, which is a hole, and some points have multiple values, which is occlusion. After calculation, 9 coordinate calculation units respectively calculate 9 virtual viewpoint image data with holes at different viewpoint positions, and mark the hole point positions in the virtual viewpoint image in the hole mark cache module.

The hole mark cache module is composed of two dual-port RAMs with a depth of 640 (the number of pixels in a line in the virtual viewpoint image) and a bit width of 1 bit, namely RAM11 and RAM12, which are used to store non-hole marks. In the embodiment of the present invention, the coordinates of the hole point are marked with 1, and the coordinates of the non-hole point are marked with 0.

The virtual viewpoint cache module consists of two dual-port RAMs with a depth of 640 and a bit width of 24 bits (consistent with the color depth of the original image), namely RAM21 and RAM22, which are used to store the mapped virtual viewpoint image data. The virtual viewpoint cache module uses two RAMs to form a double-buffer structure to realize the ping-pong operation, so as to realize the pipeline access of data.

The hole filling module includes a hole finding unit and a hole repairing unit. The hole search unit outputs the coordinate values of the non-hole pixels in the left and right views collected from the binocular camera to the hole repair unit by reading the RAM11 and RAM12 of the hole mark cache module, wherein the signal Laddr is collected from the binocular camera The coordinate value of the non-hole pixel in the left image of the binocular image, and the signal Raddr is the coordinate value of the non-hole pixel in the right image of the binocular image collected from the binocular camera. The hole repair unit performs hole filling according to the coordinate values of the non-hole pixels in the left and right images, and sends signals hf_over1~hf_over9 (the hole filling module of DIBR_V1 sends hf_over1, and the hole filling module of DIBR_V2 Send hf_over2, and so on) to the pixel counter of the stereoscopic image synthesis module.

In the embodiment of the present invention, the viewpoint mapping module generates virtual viewpoint image data in row units, and stores the pixel values of correctly mapped pixels into the virtual viewpoint buffer module for each row of data in the virtual viewpoint image, and at the same time marks non-holes Stored in the hole mark cache module. The hole search unit outputs the coordinate values of the non-hole pixels in the left and right images of the hole area to the hole repair unit by reading the non-hole marks in the hole mark cache module, and the hole repair unit fills the holes according to the left and right coordinate values. The data after the hole filling is completed is output to the cache module for storage, and is used to generate a virtual viewpoint image.

FIG. 3 is a functional block diagram of a dual-port double-buffer unit of the present invention. As shown in Figure 3, the storage part is composed of two 24-bit dual-port RAMs, namely RAM0 and RAM1. The four data ports of RAM0 and RAM1 are IN0, OUT1, IN1, and OUT0 respectively, and the number of storage units in each RAM is 640. . The ce signal is the enable signal, and the data output by the DIBR processing unit will enter the IN0 port of RAM0 or the IN1 port of RAM1 through the selector muxi controlled by the ce signal; at the same time, the selector muxo controlled by the ce signal will communicate with Data output from another RAM with different data is currently being received. That is, when data is stored in one input terminal of one RAM, the data already stored in another RAM will be used as output, and the ping-pong operation is formed alternately. In_addr is the address line of the data input end, connected to the address line of the input end of RAM0, RAM1; Out_addr is the address line of the data output end, connected to the address line of the output end of RAM0, RAM1.

FIG. 4 is a schematic diagram of the connection between the cache module and the stereoscopic image synthesis module of the present invention. The stereoscopic image synthesis module includes a pixel counter and multiple stereoscopic image generation units. In the embodiment of the present invention, the stereoscopic image synthesis module includes 3 stereoscopic image generation units, more than 3 stereoscopic image generation units can produce better stereoscopic effects but the calculation is too complicated, which reduces real-time performance; less than 3 stereoscopic image generation units Cell calculation speed is fast but the stereo effect is weak. Each stereoscopic image generating unit includes a composite controller, a plurality of data switches, a multiplexer and an output buffer.

In the embodiment of the present invention, the clock of the pixel counter is a system clock or a clock in a video signal. After the pixel counter receives the 9 signals hf_over1~hf_over9, its count piex_num increases by 1 every clock cycle and is transmitted to the composition controller, wherein the count piex_num represents the position ordinal number of the sub-pixel to be composed currently. The compositing controller inputs the count piex_num of the pixel counter as an address to a compositing table included in the compositing controller for lookup.

The synthesis table consists of a ROM with a depth of 640×360 (consistent with the size of the original image and disparity map) and a width of 9 bits (consistent with the number of virtual viewpoint images), and its content is given by the formula Determine, where x represents the abscissa of the sub-pixel; y represents the ordinate of the sub-pixel; a represents the inclination angle of the lenticular grating; A represents the number of sub-pixels spanned by the lenticular grating; N represents the number of virtual viewpoint images. Count an image from left to right and from top to bottom, and the horizontal and vertical coordinates of each sub-pixel can form a pixel serial number. When the pixel serial number is input as an address, the content of the synthesis table is searched, and the view index serial number is output, which indicates the serial number of which virtual viewpoint image the sub-pixel corresponding to the pixel serial number in the stereoscopic image is taken from.

The view index sequence number (in the embodiment of the present invention, the range is 1 to 9) is input to the multiplexer through a four-bit connection, and the multiplexer outputs 9 enable signals sel1 to sel9 according to the view index sequence number, each The enable signal corresponds to controlling a data switch.

At most one of the data switches 1 to 9 is enabled at the same time, and the enabled data switch allows its input data to be output from the output connection, while the outputs of the remaining unenabled data switches are in a high-impedance state. The synthesis controller sends the count piex_num of the pixel counter to the address line Out_addr on the output port side of each dual-port double buffer unit in the buffer module, and the data of the storage unit with the address piex_num in the dual-port double buffer unit will be output to the data switch . The corresponding data switch is turned on according to the strobe signal of the multiplexer, and the data switch outputs the virtual viewpoint image data to the output buffer.

The three stereoscopic image generating units respectively interleave and synthesize the three rows of data, and perform concurrently. When the stereoscopic image generating unit 0 interleaves the pixel data of the yth row, the stereoscopic image generating unit 1 processes the y+1th row, and the stereoscopic image generating unit 2 processes the y+2th row. The image pixel point frequency of the synthesis controller is 3 times of the clock frequency of the pixel counter, that is, within the duration of the count piex_num of each pixel counter, 3 pixels and interleaved synthesis are completed. When the last 3-line interlaced composition is completed, 1920×1080 pixel data can be obtained.

The output buffer is a ROM with a depth of 1920×1080 (stereo image size) and a width of 24 (stereo image color depth digits, consistent with the original image) bits, receiving virtual viewpoint image data from data switches 1-9. When the data is full, it becomes the data stream of the synthesized stereoscopic image, which is arranged and packaged according to time sequence for output, so that real-time stereoscopic image display can be obtained.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (10)

1. a real-time stereo images generation system, comprises many viewpoints generation module, cache module and verticalVolume image synthesis module, is characterized in that:

Described many viewpoints generation module comprise N parallel draw processing unit based on depth image, itsMiddle N=x², x is greater than 1 positive integer, draws processing unit according to former described in each based on depth imageBeginning figure and disparity map generating virtual visual point image are also sent in described cache module, send instruction simultaneouslyThe signal that described drawing virtual view image completes is to described stereo-picture synthesis module;

Described cache module comprises N the two buffer units of parallel dual-port, receives respectively and store instituteState N the described virtual visual point image that many viewpoints generation module generates, wherein the two buffer memorys of each dual-portUnit comprises that two degree of depth are that the color of described virtual visual point image width, bit wide and described original graph is darkSpend consistent two-port RAM, described two two-port RAMs composition double-damping structure is realized ping-pong operation,To realize the stream treatment to described virtual visual point image; And

Described stereo-picture synthesis module comprises pixel counter and stereo-picture generation unit, described pictureElement counter receives after the signal that described instruction drawing virtual view image completes, count asLocation is input to described cache module, and described stereo-picture generation unit reads ground from described cache moduleThe virtual visual point image data that the memory cell that location is described counting is stored, by described N virtual lookingDot image synthesizes 1 stereo-picture and exports.

2. real-time stereo images generation system as claimed in claim 1, is characterized in that, described everyIndividual based on depth image draw processing unit comprise:

Viewpoint mapping block, comprises that coordinate computing unit, zbuf buffer unit and parallax search unit,According to each pixel, the gray value in described disparity map calculates described each picture to described coordinate computing unitThe coordinate figure of vegetarian refreshments correspondence in described virtual visual point image, completes line by line from reference view to virtualThe mapping of viewpoint; Described zbuf buffer unit is described virtual visual point image width by 2 degree of depth, positionWide is the single port RAM composition of described disparity map gray scale figure place, for storing zbuffer arithmetic result;Described parallax is searched unit by the capacity ROM structure consistent with the pixel grey scale progression of described disparity mapBecome, for completing the calculating from parallax value to parallax function;

Cavity tag cache module is that described virtual visual point image width, bit wide are 1 by two degree of depthThe two-port RAM composition of position, for storing non-empty mark;

Empty viewpoint cache module, by two degree of depth be described virtual visual point image width, bit wide and described inThe two-port RAM composition that original graph color depth is consistent, completes for storing described viewpoint mapping blockDescribed virtual visual point image data after mapping, wherein, described two two-port RAMs composition double bufferingStructure realizes ping-pong operation; And

Hole-filling module, comprises that unit is repaired in cavity and unit is searched in cavity, and list is searched in described cavityUnit reads the described non-empty mark of described empty tag cache module stores, and by described original graphThe coordinate figure of non-empty pixel is exported to described cavity and is repaired unit, and unit is repaired according to institute in described cavityState coordinate figure and carry out hole-filling.

3. real-time stereo images generation system as claimed in claim 2, is characterized in that, described seatDescribed in mark computing unit calculates according to the simplification equivalence formula obtaining based on depth image rendering algorithmVirtual visual point image, described simplification equivalence formula is:

VIR_n(u0+DEEP(DIS(u0,v0))×n,v0)＝ORI(u0,v0)

Wherein, VIR_n represents the picture element matrix of described virtual visual point image, described in ORI (u0, v0) representsThe picture element matrix of original graph; Described original graph n=0, m virtual view figure of described original graph adjacent left-handPicture n=-1～-m, the adjacent right side y of described original graph virtual visual point image n=1～m, m is integer,M=in the time that N is odd number (N-1)/2, m=N/2 in the time that N is even number; U0, v0 represent respectively described formerThe transverse and longitudinal coordinate of pixel in beginning figure; The parallax value of DIS (u0, v0) denotation coordination point (u0, v0) point,The depth value of DEEP (DIS (u0, v0)) denotation coordination point (u0, v0) point.

4. real-time stereo images generation system as claimed in claim 2 or claim 3, is characterized in that instituteStating zbuffer algorithm is to calculate from described disparity map pixel according to described coordinate computing unitCoordinate result, reads and judges that address in described zbuf buffer unit is that the unit of described coordinate result isThe no parallax record that existed, if existed, by the parallax in described zbuf buffer unit and currentCalculate the parallax adopting and compare, using pixel place coordinate less parallax as described virtualThe source points coordinate of certain pixel described in visual point image, and address is in described zbuf buffer unitIn the unit of described coordinate result, record the parallax value that calculating adopts.

5. real-time stereo images generation system as claimed in claim 2 or claim 3, is characterized in that instituteState viewpoint mapping block and generate described virtual visual point image data with behavior unit, every generation is described virtualData line in visual point image, deposits the pixel value of the each pixel correctly shining upon in described empty viewpoint slowIn storing module, described non-empty mark is deposited in described empty tag cache module simultaneously.

6. real-time stereo images generation system as claimed in claim 1, is characterized in that, described verticalVolume image synthesis module comprises:

Pixel counter, receives after the signal that N described instruction drawing virtual view image completes,Its counting is in each clock cycle increase by 1 and be sent to stereo-picture generation unit, wherein said countingRepresent the current position ordinal number of wanting synthon pixel; And

Multiple described stereo-picture generation units, each described stereo-picture generation unit comprises synthetic controlDevice processed, MUX, a N data switch and output buffer memory, described synthetic controller is by described pixelThe described counting input synthetic table that counter sends is inquired about, and described synthetic controller is also by described meterNumber is input to described cache module as address, and described synthetic table is according to described counting output view indexSequence number is to described MUX, and described MUX sends enable signal to a described N data and opensOne corresponding with described view index sequence number in the Central Shanxi Plain, the described data switch being enabled will be from described slowThe described virtual visual point image data that the memory cell that in storing module, reading address is described counting is storedBe sent to described output buffer memory, the data of described output buffer memory are exported according to sequential array packages after writing completely,Obtaining real-time described stereo-picture exports.

7. real-time stereo images generation system as claimed in claim 6, is characterized in that, described in closeBecome controller to send to the two buffer memory lists of each dual-port of described cache module using described counting as addressIn the address wire of output port one side of unit.

8. the real-time stereo images generation system as described in claim 6 or 7, is characterized in that, instituteStating synthetic table is that described virtual visual point image width × highly, width are the ROM of N position by a degree of depthForm, its content is by formulaDetermine, wherein x represents sub-pixel abscissa;Y represents described sub-pixel ordinate; A represents column mirror grating inclination angle; A represent described column mirror grating acrossThe sub-pixel numbers of crossing.

9. the real-time stereo images generation system as described in claim 6 or 7, is characterized in that, manyIndividual described stereo-picture generation unit is parallel respectively to interlock and synthesizes three row data, the first stereogramWhen the capable pixel data of y being interlocked as generation unit, the second stereo-picture generation unit processingY+1 is capable, and it is capable that the 3rd stereo-picture generation unit is processed y+2, by that analogy.

10. the real-time stereo images generation system as described in claim 6 or 7, is characterized in that,The image pixel dot frequency of described synthetic controller is k times of described pixel counter clock frequency, and k isThe number of described stereo-picture generation unit.