CN105611225A - SDI multi-stage re-timing real-time transmission apparatus and transmission method thereof - Google Patents
SDI multi-stage re-timing real-time transmission apparatus and transmission method thereof Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
- H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
- H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
- H04N21/23602—Multiplexing isochronously with the video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
- H04N21/4342—Demultiplexing isochronously with video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
The invention discloses a SDI multi-stage re-timing real-time transmission apparatus and a transmission method thereof. A SDI transmission protocol is changed into a general SDI transmission protocol CSDI (Common Serial Digital Interface). The novel protocol defines last bytes in a horizontal row blanking zone as redundancy bytes. An original rigorous protocol format is broken so that a certain quantity of the redundancy bytes is arranged between rows. Simultaneously, a local clock is used to retransmit data. In a redundancy byte interval, the number of bytes is added and deleted conditionally according to a relation of the local clock and a recovered clock so that a purpose of being synchronous with a new clock under the condition that information is not lost is reached. During multistage retransmission, in order to prevent disappearance of the redundancy bytes, the redundancy byte interval needs to be determined and coordinative distribution of operations of deleting the bytes among rows is controlled. In addition, in a multipath SDI transmission system, design cost and equipment power consumption are greatly reduced and system stability is increased.
Description
Technical field
The non-compression high bandwidth transfer systems that the present invention relates to field of video monitoring, relates in particular to when SDI is multistage to be resetReal-time Transmission device and transmission method.
Background technology
Video monitoring system is mainly divided into front end video imaging at present, intermediate fibres transmission, and center matrix platform is cutChange, wall on the large-size screen monitors of rear end, also needs matrix cascade for the transmission of cities and counties of province. Along with client wants picture qualityThat asks improves constantly, the continuous breakthrough of imaging and transmission technology, and field of video monitoring has been stepped into digital high-definitionEpoch. Front end imaging has generally reached 1080p resolution ratio, and is just striding forward fast towards 4K direction. For ensureing the bestImage restoring degree, non-compression video transmission becomes everybody to be selected, and in car plate monitoring, recognition of face etc. need especiallyWant the application scenarios of careful picture. In addition another large advantage of non-compression video transmission is real-time, due to biographyThe specificity of defeated passage, its transmission delay is minimum, is applicable to the field of the real-time command and monitors of needs such as safe city.The technology of utilizing frame gap to use local clock to retransmit than Ethernet, non-compression video host-host protocol is notFoot is that transmission time slot is irredundant, causes the inferior position of non-compression video transmission technology on cost particularly outstanding.Taking the common interfaces standard SDI (SerialDigitalInterface) of field of video monitoring as example, due to transmissionThe parameter influence including impedance operator such as medium, transmission range, transmission equipment, passes this high speed serializationOn defeated every one-level equipment after video imaging, all increased clock jitter, and SDI host-host protocol is irredundantMake its transmission mode be defined as homology transmission, and the mode of eliminating this clock jitter is that recovered clock is goneTremble, then by clock retransmission of video data after debounce. In this process, debounce technology and chip cost are very high,And additionally increase transmission equipment design complexities and equipment power dissipation, particularly outstanding for multichannel SDI transmission flaws.
Summary of the invention
For above-mentioned technological deficiency, real-time Transmission device and transmission method when the present invention proposes that SDI is multistage to be reset.
In order to solve the problems of the technologies described above, technical scheme of the present invention is as follows:
SDI is multistage live transmission method while resetting, comprises the steps:
11) in the time encoding, carry out time domain conversion for outside BT1120 data flow, the clock after conversion is originallyGround clock and source clock remain on 200ppm with interior error;
12) synchronously complete the non-return-to-zero inversion code coding that carries out SDI standard afterwards;
13) coding is completed and send afterwards, send the clock homology after reference clock need to and be encoded;
14) in the time decoding, data to be decoded are carried out to the decoding of non-return-to-zero inversion code, then carry out TRS numberAccording to word alignment, Output rusults is synchronized to local clock again;
In step 11) carry out time domain conversion and step 14) be synchronized in local clock process, all need redundant positionAddress difference calculation procedure between sync byte step and different time domain.
Further, described redundant position sync byte step comprises: data stream is carried out can deleting or can increasingByte manipulation, described operation judges is calculated and is as the criterion according to the address difference between different time domain.
Further, in the time carrying out deletion action, also need to judge whether redundancy bytes subsequent byte is effective imageOrigin identification, if effective image origin identification is no longer deleted byte manipulation.
Further, the address difference calculation procedure between described different time domain comprises: the address of RAM is divided for 4Section, sampling 8 bit address high 2, beats to clap to the address sampling and processes, when many beat of data homogeneous phase simultaneously,Carry out the address at RAM read-write two ends and carry out difference calculating, with calculated value control be labeled byte deletion orPerson can increase byte manipulation, does not surmount mutually finally to control read/write address.
SDI is multistage real-time Transmission device while resetting, comprises coding module and decoder module, outside BT1120 data flowFirst the sdi_resync module that enters coding module is carried out time domain conversion, while making clock after conversion localZhong Yuyuan clock remains on 200ppm with interior error; Synchronously complete afterwards at its sdi_nrzi_encoder mouldPiece carries out the non-return-to-zero inversion code coding of SDI standard, after coding is completed, sends, send with reference to timeClock homology after clock need to and be encoded; Described decoder module is to coding module transmitting terminal decoding data,Data to be decoded are carried out to the decoding of non-return-to-zero inversion code in sdi_nrzi_decoder module, then at itSdi_framer module is carried out the alignment of TRS data word, and Output rusults is synchronized to again in its sdi_resync moduleLocal clock.
Further, in the sdi_resync of the sdi_resync of coding module module and decoder module module, logarithmDelete or can increase byte manipulation according to stream, described deletion or can increase byte manipulation according to difference timeAddress difference between territory is calculated and is as the criterion.
Beneficial effect of the present invention is: SDI host-host protocol is improved to general SDI host-host protocol CSDI(CommonSerialDigitalInterface). This novel agreement is on BT1120 host-host protocol basis, fixedSeveral bit bytes in justice horizontal line blanking zone end are redundancy bytes, break original rigorous protocol format, make row and rowBetween have the redundancy bytes of some, utilize local clock data retransmission simultaneously. This redundancy bytes interval canTo carry out conditionally additions and deletions byte number according to the relation of local clock and recovered clock, do not losing to reachIn the situation of breath of breaking one's promise with the object of new clock synchronous. In the time of multistage re-transmission, be the disappearance that prevents redundancy bytes,Also need redundancy bytes interval to judge, what control deletion byte was such operates in the association between different rowsAdjust and distribute. In addition, in multichannel SDI transmission system, can significantly reduce design cost and reduce equipment power dissipation,Improve the stability of a system.
The present invention also carries out adjustment to the every one-level redundancy bytes in Multi-stage transmission communication system, can greatly improve levelConnection number. Did for previous stage that redundancy bytes adjusts, capable of regulating mark at the corresponding levels does reverse adjustment or notAdjust, to avoid multistage unidirectional cumulative, cause redundancy bytes too much or not enough.
Because data tranmitting data register does not re-use the recovered clock that shake is larger, but use the less this locality of shakeClock, therefore no longer need to use external clock debounce chip, reduces costs and power consumption, also simplified design. WithTime in multiloop loop system, the type selecting of transmission chip no longer relies on and has independent nonhomologous high speed serdes, and canReelect the high speed serdes that general homology sends reference clock, significantly reduce device cost.
The present invention is on BT1120 host-host protocol basis, and the redundancy bytes at definition line blanking zone end, is used thisGround clock is realized multistage real-time Transmission, reduces costs and power consumption, transmits by a relatively large margin for multichannel SDISimplify its design.
Brief description of the drawings
Fig. 1 is logical design module relation diagram;
Fig. 2 is sdi_resync module data process chart;
Fig. 3 is the design that enables while writing RAM in sdi_resync module;
Fig. 4 reads ram clock in sdi_resync module to delete dark-grey byte when writing ram clock;
Fig. 5 reads ram clock to be slower than and while writing ram clock, to increase light gray byte in sdi_resync module.
Detailed description of the invention
Be further described below in conjunction with specific embodiments and the drawings.
Suppose that local clock error is at 100ppm, local clock and data recovered clock error ten thousand/.Show under BT1120 form, if with this local clock data retransmission, so must in 10000 dataSurely can repeat to transmit a byte or transmit less a byte. Taking 1080p25Hz as example, a line has2640 bytes, therefore can loading error occurring after transmission 3.78 row. Numerical procedure is shown in formula a.
Wherein, the l spaced rows number that represents to make mistakes, p represents the trueness error of local clock and recovered clock, w represents to refer toThe byte number of determining video format a line, p1 represents local clock, p2 represents recovered clock. According to formula 1Calculate, the interval line number of makeing mistakes of easily calculating 1080p30Hz is 4.54 row. If clocking error is at 50ppmIn, the interval line number of makeing mistakes increases, synchronously more favourable to data.
Therefore it is feasible with row unit, redundancy bytes interval being adjusted. During from multistage resetting, analyze vacationIf the clock frequency of every one-level is all low than previous stage, and suppose that the redundancy bytes number of definition a line is 1,Data can be transmitted at most 3 grades, suppose that the redundancy bytes number of definition a line is 2, can transmit at most 7 grades.And in this process, without frame buffer, only need row cache, can retain horizontal blanking district simultaneously except redundancy wordEffective information outside joint.
Be illustrated in figure 1 the module relation diagram of top-level module, the course of work that Fig. 2 is data flow is described as follows.This module is divided into two independently submodules, coding module and decoder modules. For coding module sdi_encoder,First outside BT1120 data flow enters sdi_resync module (SDI data Domain Synchronous module) and carries out time domain conversion,Clock (local clock) after conversion must be with original basic with frequently, such as source clock is 74.2500MHz (ATime domain), local clock is 74.2499MHz (B time domain), basic need remains on 200ppm with interior error.Enter sdi_nrzi_encoder module (SDI non-return-to-zero reversal phase coding module) after synchronously completing and carry out SDI standardNon-return-to-zero inversion code coding. After having encoded, can be sent by the serdes of FPGA, certainly send ginsengExamine the clock homology after clock need to and be encoded, need for local clock.
If decoding, is introduced into data to be decoded sdi_nrzi_decoder module (the anti-phase decoding mould of SDI non-return-to-zeroPiece) carry out the decoding of non-return-to-zero inversion code, then enter sdi_framer module (SDI frame format decoder module) and enterThe alignment of row TRS data word, outputs results to sdi_resync module (SDI data Domain Synchronous module) subsynchronous againTo local clock.
From above-mentioned description, be in the output of B time domain or the output of C time domain is not standardSDI form BT1120 data flow, the length of the blanking zone of every a line can be inconsistent. For A time domain and DThe input data of time domain, do not need the SDI form BT1120 for standard, therefore this module can multistagely be gone here and thereConnect use.
In codec design, emphasis need to be described the design of redundancy bytes position, and ground between different time domainThe difference of location is calculated. Above two steps all complete in the sdi_resync module shown in Fig. 1.
1. redundant position sync byte step:
In Fig. 3,715 these bytes are marked as and can delete or can increase byte, and after deleting in Fig. 4Format description, the format description after increasing in Fig. 5. And delete and increase the work of byte beAddress difference calculation procedure between different time domain judges.
Should be noted that a bit, when this data flow is during by multistage transmission, if continuously this what all need to delete byte,Need so to prevent deleted multiple bytes in a line, therefore also need this situation to judge. Because 715The subsequent byte of byte is SAV effective image origin identification, thus in data line, be unique, after instituteIf continuous SAV byte shows that prime coding module or decoder module did deletion byte in this lineOperation, in order to prevent that destroying this row of frame structure can not delete byte manipulation again. Increase byte feasible.2. the address difference calculation procedure between different time domain:
Because the clock of writing of RAM is SDI recovered clock, read clock and be local with clock frequently, be homology not, in different time domain, therefore need the address at RAM read-write two ends to carry out difference calculating, read-write clock is notWhen homology, need to calculate, and be to calculate always, controls the additions and deletions operation that is labeled byte with calculated value, withControlling eventually read/write address does not surmount mutually. Therefore not directly with reading clock sampling write address, particularly with frequency notThe clock of homology, otherwise very easily make mistakes in the address sampling. Therefore in the time designing this, address of RAM is dividedFor 4 sections, get the high 2 of 8 bit address. These 2 saltus steps can be very not frequent on the one hand, easily quiltSampling, just can distinguish read/write address interval and need to be 1/4 the address ram degree of depth on the other hand. ButIn the time of high two bit map, still may there is sample error, process therefore need to beat to clap to the address sampling,Beat bat processing mode and can adopt traditional processing mode, when many beat of data homogeneous phase represents not in saltus step district simultaneously,Can compare.
Following steps are to read the detailed description that address is controlled:
1) write address of initialization RAM is 0, and reading address is the half length address of RAM;
2) data are write to RAM, and mark can increase or delete the position of byte, andWhether this row can carry out deletion action;
3) the high 2bits data of read-write address ram are beaten and are clapped and get the poor of read/write address;
4), in the time that difference is greater than threshold value, illustrates and read faster than writing, and if now in flag byte position,The next one is read still current address, address; In the time that difference is less than threshold value, illustrate to read to be slower than and write, andIf now in flag byte position, the row data were not once done deletion action yet, nextReading address should certainly add 2 and jump; Other situations are next from adding 1.
The above is only the preferred embodiment of the present invention, it should be pointed out that common for the artTechnical staff, without departing from the inventive concept of the premise, can also make some improvements and modifications, theseImprovements and modifications also should be considered as in protection domain of the present invention.
Claims (6)
1.SDI is multistage live transmission method while resetting, is characterized in that, comprises the steps:
11) in the time encoding, carry out time domain conversion for outside BT1120 data flow, the clock after conversion is originallyGround clock and source clock remain on 200ppm with interior error;
12) synchronously complete the non-return-to-zero inversion code coding that carries out SDI standard afterwards;
13) coding is completed and send afterwards, send the clock homology after reference clock need to and be encoded;
14) in the time decoding, data to be decoded are carried out to the decoding of non-return-to-zero inversion code, then carry out TRS numberAccording to word alignment, Output rusults is synchronized to local clock again;
In step 11) carry out time domain conversion and step 14) be synchronized in local clock process, all need redundancyAddress difference calculation procedure between position sync byte step and different time domain.
2. SDI according to claim 1 is multistage live transmission method while resetting, is characterized in that, described superfluousRemaining position sync byte step comprises: data stream is carried out can deleting or can increasing byte manipulation, described behaviourWork judges according to address difference between different time domain and calculates and be as the criterion.
3. SDI according to claim 2 is multistage live transmission method while resetting, is characterized in that, is carrying outWhen deletion action, also need to judge whether redundancy bytes subsequent byte is effective image origin identification, if hadEffect image origin identification, no longer deletes byte manipulation.
4. SDI according to claim 3 is multistage live transmission method while resetting, is characterized in that, describedComprise with the address difference calculation procedure between time domain: the address of RAM is divided for 4 sections to sampling 8 bit addressHigh 2, the address sampling is beaten to clap and processes, when many beat of data homogeneous phase simultaneously, carry out RAM read-write twoDifference calculating is carried out in the address of end, controls and is labeled the deletion of byte or can increases byte behaviour with calculated valueDo, do not surmount mutually finally to control read/write address.
5.SDI is multistage real-time Transmission device while resetting, is characterized in that, comprises coding module and decoder module, outerFirst the BT1120 of portion data flow enters the sdi_resync module of coding module and carries out time domain conversion, makes conversionAfter clock be that local clock and source clock remain on 200ppm with interior error; Synchronously complete afterwards at itSdi_nrzi_encoder module is carried out the non-return-to-zero inversion code coding of SDI standard, after coding is completed, carries outSend, send the clock homology after reference clock need to and be encoded; Described decoder module sends coding moduleEnd data is decoded, and data to be decoded is carried out to the solution of non-return-to-zero inversion code in sdi_nrzi_decoder moduleCode, then carries out the alignment of TRS data word in its sdi_framer module, and Output rusults is at its sdi_resyncModule is synchronized to local clock again.
6. SDI according to claim 5 is multistage real-time Transmission device while resetting, is characterized in that, at codingIn the sdi_resync module of module and the sdi_resync module of decoder module, data stream is deleted orCan increase byte manipulation, described deletion or can increase byte manipulation according to the address difference meter between different time domainBe as the criterion.
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Denomination of invention: SDI multi-level retiming real-time transmission device and transmission method Effective date of registration: 20220904 Granted publication date: 20190423 Pledgee: Bank of Hangzhou Limited by Share Ltd. science and Technology Branch Pledgor: Hangzhou Zhongwei Digital Technology Co.,Ltd. Registration number: Y2022980014448 |
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Denomination of invention: SDI multi-level retiming real-time transmission device and transmission method Effective date of registration: 20230608 Granted publication date: 20190423 Pledgee: Bank of Hangzhou Limited by Share Ltd. science and Technology Branch Pledgor: Hangzhou Zhongwei Digital Technology Co.,Ltd. Registration number: Y2023980043248 |
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