CN105609416A - Silicon etching method - Google Patents
Silicon etching method Download PDFInfo
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- CN105609416A CN105609416A CN201610087506.XA CN201610087506A CN105609416A CN 105609416 A CN105609416 A CN 105609416A CN 201610087506 A CN201610087506 A CN 201610087506A CN 105609416 A CN105609416 A CN 105609416A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
The invention provides a silicon etching method, which comprises the steps as follows: (1) an etching mask pattern is fabricated on a silicon substrate; and (2) the silicon substrate with fabricated etching mask pattern is placed into an etching machine for etching; the bottom electrode power of the etching machine is generated by 100-1,000Hz of pulsed power supply; and the temperature of a slide holder of the etching machine is -120 DEG C and -100 DEG C. The silicon etching method combines a low-temperature silicon etching process and a low-frequency process, can well control a side tracking phenomenon generated in the silicon etching process, is suitable for nanoscale silicon etching with a high aspect ratio, and avoids the side tracking phenomenon generated in the prior art in the silicon etching process.
Description
Technical field
The present invention relates to semiconductor micro-nano processing technique field, relate in particular to a kind of silicon etching method.
Background technology
Integrated circuit, micro-electro-mechanical systems unify optics manufacture field, all wish to realizeThe dry etching of monocrystalline silicon and polysilicon high aspect ratio structure. So plasma etching technology is notOnly to possess certain etch rate, etching selection ratio, also need to possess intimate completely controlledAnisotropy sidewall etching. At present, general adopted anisotropic dry etch is due to can notAvoid having the lateral etching that on sidewall, Ions Bombardment causes, and cannot reach etching profundityThe anisotropy requirement that width-ratio structure is required. Therefore, obtain the structure of high-aspect-ratio, canIn sidewall surfaces in etching process, cover one deck resistance erosion property film with protective side wall not by laterallyEtching, obtains longitudinal etching result thus.
General corrosion preventing layer is the organic polymer thin film that chemical deposition generates in etching process,In reacting gas, need to introduce C (carbon) element for this reason. Introduce CF class gas and etching gas sameIn time, produces plasma and carries out etching, but due to the generation of organic polymer, is subject in chamber eachClass physics and chemistry influence factor is more, and in etching process, realize adequate thickness and stablize canThe polymer corrosion preventing layer leaning on is very difficult, does not often reach the high-aspect-ratio knot that sidewall quality is higherStructure. For this point, researcher has developed Bosch etching technics, by polymer resistance erosionThe deposit of layer and the etching of monocrystalline silicon is separated into two independently process cycle alternation enterOK, so just avoid influencing each other between deposit and etching, ensured the steady of resistance erosion qualityFixed reliable, thus needed anisotropic etching can be obtained, and there is higher etching speedRate and selection ratio.
Bosch etching technics also has the limitation of its application, and for example sidewall is coarse, has hundred nano-scaleSidetracking groove, therefore Bosch etching technics is applicable to the etching of the above size of micron order.If obtain the etching structure of the high-aspect-ratio that sidewall is smooth, can adopt inorganic corrosion preventing layerLow temperature plasma lithographic method. The slide holder temperature of low temperature silicon etching is generally-150 DEG C～-100 DEG C, it is gas that etching gas is selected F (fluorine), in the presence of oxygen, generates SiFxOy，Volatile under the cavity environment of normal temperature, but be solid-state in the time of low temperature. By reducing surface reactionGenerate the volatility of material, promote thickness and the reliability of corrosion preventing layer, to stop in etching processThe lateral etching of oppose side wall, can reach higher depth-to-width ratio etching figure, has higher simultaneouslySelect ratio.
Although low temperature plasma silicon etching process has advantage as above, normal in experimentIn the Cryo-etching of rule (frequency in lower electrode power source is 13.56MHz, belongs to radio frequency:RadioFrequency), when the structure of the nano level high-aspect-ratio of etching, because channel opening is narrower,Activity chemistry reactive material is diffused into the relatively difficulty of bottom land that depth-to-width ratio is higher, bottom land simultaneouslyThe volatile matter generating after chemical reaction is more difficult being pulled out also. That is to say, narrower channel opening is attachedThe reactive material concentration of near reactive material concentration ratio bottom land is high, so near easy shape channel openingThe sidetracking phenomenon that becomes indent, widens opening size, finally makes the sidewall of whole groove not beRequired anisotropy. As shown in Figure 1, the channel opening of the electron beam adhesive on silicon chip in Fig. 1Width is 100nm, and after etching, the width of channel opening is 145.8nm, broadening 45.8nm.The baseline of etching pit bottom and the angle in etching groove sideline are 92.6 °, therefore, after etchingTrench bottom is narrow 50nm, sidewall degree is not high.
In addition, if adopt SiO2Deng insulating materials as mask, the electric discharge at this insulating barrier tipEffect can form internal field, and this electric microfield has deflecting action to the ion of downward bombardment, causesThere is sidetracking phenomenon in mask lower sidewalls. So in nano level etching, similarly sidetracking is existingResemble the performance that can greatly reduce various devices.
Summary of the invention
Based on the defect of prior art, the invention provides a kind of silicon etching method, existing to solveThe sidetracking phenomenon that technology occurs in silicon etching process.
For this purpose, the invention provides a kind of silicon etching method, comprise the following steps:
(1) on silicon chip, make etch mask figure;
(2) silicon chip of making described etch mask figure is placed in etching machine and is carvedErosion; The lower electrode power of described etching machine is produced by the pulse power of 100～1000Hz, described quarterThe slide holder temperature of erosion machine is-120 DEG C～-100 DEG C.
Preferably, said method is further comprising the steps of:
(3) silicon chip after etching is carried out to over etching.
Preferably, the slide holder temperature of etching machine described in described step (3) and described step (2)Described in the slide holder temperature of etching machine identical.
Preferably, in described etching process, the power of the described pulse power is 3～30W, producesThe dutycycle of raw pulse signal is 10%～50%, and the upper electrode power of described etching machine is200～1000W, the pressure in vacuum tank of described etching machine is 5～15mTorr, described etching machine adoptsSF6The flow of gas is 20～40sccm, the O that described etching machine adopts2The flow of gas is5～30sccm。
Preferably, in described etching process, the power of the described pulse power is 5W, described arteries and veinsThe frequency of rushing power supply is 500Hz, and the pulse signal dutycycle that the described pulse power produces is 35%;The upper electrode power of described etching machine is 400W, and the pressure in vacuum tank of described etching machine is5mTorr, the SF that described etching machine adopts6The flow of gas is 20sccm, and described etching machine is adoptedWith O2The flow of gas is 5sccm, and the slide holder temperature of described etching machine is-120 DEG C.
Preferably, in described etching process, the power of the described pulse power is 5W, described arteries and veinsThe frequency of rushing power supply is 300Hz, and the pulse signal dutycycle that the described pulse power produces is made as35%; The upper electrode power of described etching machine is 400W, and the pressure in vacuum tank of described etching machine is9mTorr, the SF that described etching machine adopts6The flow of gas is 30sccm, and described etching machine is adoptedWith O2The flow of gas is 9sccm, and the slide holder temperature of described etching machine is-110 DEG C.
Preferably, in described etching process, the power of the described pulse power is 30W, described inThe frequency of the pulse power is 1000Hz, and the pulse signal dutycycle that the described pulse power produces is50%; The upper electrode power of described etching machine is 1000W, the pressure in vacuum tank of described etching machineFor 15mTorr, the SF that described etching machine adopts6The flow of gas is 40sccm, described etchingThe O that machine adopts2The flow of gas is 20sccm, and the slide holder temperature of described etching machine is-100 DEG C.
Preferably, in described over etching process, the power of the described pulse power is 3W, described inThe frequency of the pulse power is 500Hz, and the pulse signal dutycycle that the described pulse power produces is made as10%; The upper electrode power of described etching machine is 400W, and the pressure in vacuum tank of described etching machine is7mTorr, the SF that described etching machine adopts6The flow of gas is 20sccm, and described etching machine is adoptedWith O2The flow of gas is 15sccm, and the slide holder temperature of described etching machine is-110 DEG C.
Preferably, described electron beam adhesive is positive glue or negative glue.
Preferably, described step is made etch mask figure in (1) on silicon chip, comprising:
On silicon chip, applying electron beam adhesive, electron beam exposure and electron beam develops.
As shown from the above technical solution, silicon etching method of the present invention, by by low temperature silicon etchingTechnique and the combination of low frequency technique, used the bottom electrode power supply of low-frequency pulse power supply as etching machine,The temperature of slide holder is set in certain low temperature range, can be good at being controlled at silicon etching mistakeThe sidetracking phenomenon producing in journey, is applicable to the nano silicone etching of high-aspect-ratio.
Brief description of the drawings
Fig. 1 is the image that the profile scanning electron microscope of prior art etching nano-silicon obtains;
The schematic flow sheet of the silicon etching method that Fig. 2 provides for one embodiment of the invention;
The profile scanning of the silicon etching method etching nano-silicon that Fig. 3 provides for one embodiment of the inventionThe image that electron microscope obtains;
Fig. 4 sweeps for the section of the silicon etching method etching nano-silicon that another embodiment of the present invention providesRetouch the image that electron microscope obtains;
Fig. 5 sweeps for the section of the silicon etching method etching nano-silicon that another embodiment of the present invention providesRetouch the image that electron microscope obtains different graphic array;
Fig. 6 sweeps for the section of the silicon etching method etch polysilicon that another embodiment of the present invention providesRetouch the image that electron microscope obtains.
Detailed description of the invention
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is done further in detailDescribe. Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.
Fig. 2 shows the schematic flow sheet of the silicon etching method that one embodiment of the invention provides. AsShown in Fig. 2, the silicon etching method of the present embodiment comprises step (1) and step (2).
(1) on silicon chip, make etch mask figure;
(2) silicon chip of making described etch mask figure is placed in etching machine and is carvedErosion.
Wherein, the lower electrode power of described etching machine is produced by the pulse power of 100～1000Hz,The slide holder temperature of described etching machine is-120 DEG C～-100 DEG C.
The silicon etching method of the present embodiment, combines low-frequency pulse technology with Cryo-etching technology,The etching groove perpendicularity obtaining is good, without sidetracking phenomenon.
Fig. 3 shows the section of the silicon etching method etching nano-silicon that one embodiment of the invention providesThe image that SEM obtains. The silicon etching method of the present embodiment is as follows:
(1) on silicon chip, apply the positive glue ZEP520 of electron beam, expose to the sun through front baking, electron beamAfter light, development, prepare positive photoresist figure.
(2) silicon chip is placed in to inductively coupled plasma etching machine and carries out etching.
Wherein, the power of the pulse power is made as 5W, and frequency is made as 500Hz, and the pulse power producesPulse signal dutycycle be made as 35%. The upper electrode power of inductively coupled plasma etching machineBe made as 400W, the pressure of vacuum chamber is made as 5mTorr, SF6The flow of gas is 20sccm,O2The flow of gas is 5sccm, and slide holder temperature is made as-120 DEG C.
Silicon chip after etching is cut open along etching groove direction, utilized SEM SEM to seeExamine the section of etching groove, the SEM obtaining schemes as shown in Figure 3. As shown in Figure 3, the present embodimentSilicon chip on the channel opening width of electron beam adhesive be 100nm, after etching, channel opening is wideDegree is for 104.4nm, broadening 4.4nm. The baseline of etching pit bottom and the angle in etching groove sidelineDegree is 89.7 °, and the degree of depth of etching groove is 1.46 μ m, and therefore, the depth-to-width ratio of etching groove reaches 14:1,Channel opening width and glue A/F are consistent, and opening part is without sidetracking phenomenon, the quarter after etchingErosion trough rim line is almost vertical with baseline, and etching groove steepness is high, and sidewall is smooth.
The silicon etching method of the present embodiment, utilizes the positive glue of electron beam as etch mask, by lowFrequently the pulse power, and low temperature slide holder, completes the etching to silicon chip, the etching groove obtainingHave high-aspect-ratio, and erosion groove steepness is high, sidewall is smooth, has overcome prior art and has carved at siliconSidetracking phenomenon in erosion process.
Fig. 4 shows cuing open of silicon etching method etching nano-silicon that another embodiment of the present invention providesThe image that face SEM obtains. The silicon etching method of the present embodiment is as follows:
(1) the upper electricity that applies of the silicon chip SOI (SiliconOnInsulator) in dielectric substrateThe positive glue ZEP520 of son bundle, after front baking, electron beam exposure, development, prepares positivity photoetchingGlue pattern.
(2) silicon chip is placed in to inductively coupled plasma etching machine and carries out etching.
Wherein, the power of the pulse power is made as 5W, and frequency is made as 300Hz, and the pulse power producesPulse signal dutycycle be made as 35%. The upper electrode power of inductively coupled plasma etching machineBe made as 400W, the pressure of vacuum chamber is made as 9mTorr, SF6The flow of gas is 30sccm,O2The flow of gas is 9sccm, and slide holder temperature is made as-110 DEG C.
(3) utilize the SOI that inductively coupled plasma etching machine is crossed etching to carry out over etching.
Wherein, the power of the pulse power is made as 3W, and frequency is made as 500Hz, and the pulse power producesPulse signal dutycycle be made as 10%. The upper electrode power of inductively coupled plasma etching machineBe made as 400W, the pressure of vacuum chamber is made as 7mTorr, SF6The flow of gas is 20sccm,O2The flow of gas is 15sccm, and slide holder temperature is made as-110 DEG C.
Silicon chip after etching is cut open along etching groove direction, utilized SEM SEM to seeExamine the section of etching groove, the SEM obtaining schemes as shown in Figure 4. As shown in Figure 4, the present embodimentSOI sheet on the channel opening width of electron beam adhesive be 110nm, after etching, channel opening is wideDegree is for 110.0nm, without broadening. The baseline of etching pit bottom and the angle in etching groove sideline are90.4 °, the degree of depth of etching groove is 1.06 μ m. Therefore, etching depth-to-width ratio reaches 10:1, and groove is openedMouth width and glue A/F are consistent, and opening part is without sidetracking phenomenon; The steepness of etching grooveHeight, sidewall is smooth; Etching groove bottom does not have footing (footing) phenomenon, and etching bottom does not have sideBore.
The silicon etching method of the present embodiment, utilizes the SOI sheet after etching is carried out to over etching,The etching groove opening arriving is not broadened, and etching groove steepness is high, and sidewall is smooth, and at the bottom of etching groovePortion does not have sidetracking.
Fig. 5 shows cuing open of silicon etching method etching nano-silicon that another embodiment of the present invention providesFace SEM obtains the image of different graphic array. The silicon etching method of the present embodimentAs follows:
(1) on silicon chip, apply electron beam adhesive HSQ, through electron beam lithography, preparationGo out negative photoresist figure, lines critical size is sub-10nm, the about 30nm of thickness.
(2) silicon chip is placed in to inductively coupled plasma etching machine etching.
Wherein, the power of the pulse power is made as 12W, and frequency is made as 350Hz, and the pulse power producesRaw pulse signal dutycycle is 25%. The upper electrode power of inductively coupled plasma etching machineFor 350W, the pressure of vacuum chamber is 7mTorr, SF6The flow of gas is 30sccm, O2GasThe flow of body is 20sccm, and slide holder temperature is made as-110 DEG C.
Silicon chip after etching is cut open along etching groove direction, utilized SEM SEM to seeExamine the section of etching groove, the SEM obtaining schemes as shown in Figure 5. As shown in Figure 5, the present embodimentSilicon chip on annular etching structure, dot matrix etching structure, straight line etching structure, hexagonal lineThe sub-10nm lines etching depth of etching structure is 300nm, and the depth-to-width ratio of each etching structure is10:1, lines sidewall is without sidetracking phenomenon, and steepness is high, and sidewall is smooth.
The silicon etching method of the present embodiment, can the different structure of etching, and each etching structureLines sidewall is without sidetracking phenomenon, and steepness is high.
Fig. 6 shows cuing open of silicon etching method etch polysilicon that another embodiment of the present invention providesThe image that face SEM obtains. The silicon etching method of the present embodiment is as follows:
(1) (utilize plasma enhanced chemical vapor deposition method PECVD at polysilicon SOI sheetGrowth 700nm top layer polysilicon) the upper electron beam adhesive ZEP520 that applies, through front baking, electron beamAfter exposure, development, prepare positive photoresist figure.
(2) silicon chip is placed in to inductively coupled plasma etching machine and carries out etching.
Wherein, the power of the pulse power is made as 30W, and frequency is made as 1000Hz, and the pulse power producesRaw pulse signal dutycycle is made as 50%. The top electrode merit of inductively coupled plasma etching machineRate is made as 1000W, and the pressure of vacuum chamber is made as 15mTorr, SF6The flow of gas is 40sccm,O2The flow of gas is 20sccm, and slide holder temperature is made as-100 DEG C.
(3) utilize the SOI that inductively coupled plasma etching machine is crossed etching to carry out over etching.
Wherein, the power of the pulse power is made as 5W, and frequency is made as 100Hz, and the pulse power producesPulse signal dutycycle be made as 10%. The upper electrode power of inductively coupled plasma etching machineBe made as 200W, the pressure of vacuum chamber is made as 15mTorr, SF6The flow of gas is 30sccm,O2The flow of gas is 30sccm, and slide holder temperature is made as-100 DEG C.
Silicon chip after etching is cut open along etching groove direction, utilized SEM SEM to seeExamine the section of etching groove, the SEM obtaining schemes as shown in Figure 6. As shown in Figure 6, the present embodimentSOI sheet on the channel opening width of electron beam adhesive be 169.0nm, the degree of depth of etching groove is705.3nm. Therefore, etching depth-to-width ratio reaches 4:1, and channel opening width and glue A/F keepUnanimously, opening part is without sidetracking phenomenon; The steepness of etching groove is high, and sidewall is smooth; At the bottom of etching groovePortion does not have footing (footing) phenomenon, and etching bottom does not have sidetracking.
The silicon etching method of the present embodiment, carries out etching to polysilicon SOI sheet, the etching obtainingGroove steepness is high, and sidewall is smooth, there is no footing and sidetracking phenomenon.
One of ordinary skill in the art will appreciate that: although the above general explanation of use,Detailed description of the invention and test, the present invention is described in detail, but on basis of the present invention,Can make some modifications or improvements it, this will be apparent to those skilled in the art.Therefore, these modifications or improvements without departing from theon the basis of the spirit of the present invention, all belong toThe scope of protection of present invention.
Claims (10)
1. a silicon etching method, is characterized in that, comprises the following steps:
(1) on silicon chip, make etch mask figure;
(2) silicon chip of making described etch mask figure is placed in etching machine and is carvedErosion; The lower electrode power of described etching machine is produced by the pulse power of 100～1000Hz, described quarterThe slide holder temperature of erosion machine is-120 DEG C～-100 DEG C.
2. method according to claim 1, is characterized in that, said method also comprise withLower step:
(3) silicon chip after etching is carried out to over etching.
3. method according to claim 2, is characterized in that, in described step (3)The slide holder temperature of etching machine described in the slide holder temperature of described etching machine and described step (2)Identical.
4. method according to claim 1, is characterized in that, in described etching process,The power of the described pulse power is 3～30W, and the dutycycle of the pulse signal of generation is10%～50%, the upper electrode power of described etching machine is 200～1000W, described etching machine trueEmpty constant pressure is by force 5～15mTorr, the SF that described etching machine adopts6The flow of gas is20～40sccm, the O that described etching machine adopts2The flow of gas is 5～30sccm.
5. method according to claim 1, is characterized in that, in described etching process,The power of the described pulse power is 5W, and the frequency of the described pulse power is 500Hz, described pulseThe pulse signal dutycycle of power generation is 35%; The upper electrode power of described etching machine is400W, the pressure in vacuum tank of described etching machine is 5mTorr, the SF that described etching machine adopts6GasThe flow of body is 20sccm, the O that described etching machine adopts2The flow of gas is 5sccm, described inThe slide holder temperature of etching machine is-120 DEG C.
6. method according to claim 1, is characterized in that, in described etching process,The power of the described pulse power is 5W, and the frequency of the described pulse power is 300Hz, described pulseThe pulse signal dutycycle of power generation is made as 35%; The upper electrode power of described etching machine is400W, the pressure in vacuum tank of described etching machine is 9mTorr, the SF that described etching machine adopts6GasThe flow of body is 30sccm, the O that described etching machine adopts2The flow of gas is 9sccm, described inThe slide holder temperature of etching machine is-110 DEG C.
7. method according to claim 1, is characterized in that, in described etching process,The power of the described pulse power is 30W, and the frequency of the described pulse power is 1000Hz, described arteries and veinsThe pulse signal dutycycle of rushing power generation is 50%; The upper electrode power of described etching machine is1000W, the pressure in vacuum tank of described etching machine is 15mTorr, the SF that described etching machine adopts6The flow of gas is 40sccm, the O that described etching machine adopts2The flow of gas is 20sccm,The slide holder temperature of described etching machine is-100 DEG C.
8. method according to claim 2, is characterized in that, in described over etching processIn, the power of the described pulse power is 3W, the frequency of the described pulse power is 500Hz, described inThe pulse signal dutycycle that the pulse power produces is made as 10%; The upper electrode power of described etching machineFor 400W, the pressure in vacuum tank of described etching machine is 7mTorr, the SF that described etching machine adopts6The flow of gas is 20sccm, the O that described etching machine adopts2The flow of gas is 15sccm,The slide holder temperature of described etching machine is-110 DEG C.
9. method according to claim 1, is characterized in that, described electron beam adhesive is for justGlue or negative glue.
10. method according to claim 1, is characterized in that, in described step (1)On silicon chip, make etch mask figure, comprising:
On silicon chip, apply electron beam adhesive, exposure and development.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US10170697B2 (en) | 2016-09-07 | 2019-01-01 | International Business Machines Corporation | Cryogenic patterning of magnetic tunnel junctions |
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| CN101379600A (en) * | 2006-02-01 | 2009-03-04 | 阿尔卡特朗讯公司 | Anisotropic etching method |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
| CN101988197A (en) * | 2009-08-03 | 2011-03-23 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method, plasma processing method and system |
| CN104465336A (en) * | 2014-12-02 | 2015-03-25 | 国家纳米科学中心 | Low-frequency BOSCH deep silicon etching method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101379600A (en) * | 2006-02-01 | 2009-03-04 | 阿尔卡特朗讯公司 | Anisotropic etching method |
| CN101962773A (en) * | 2009-07-24 | 2011-02-02 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
| CN101988197A (en) * | 2009-08-03 | 2011-03-23 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method, plasma processing method and system |
| CN104465336A (en) * | 2014-12-02 | 2015-03-25 | 国家纳米科学中心 | Low-frequency BOSCH deep silicon etching method |
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| US10170697B2 (en) | 2016-09-07 | 2019-01-01 | International Business Machines Corporation | Cryogenic patterning of magnetic tunnel junctions |
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Application publication date: 20160525 |