CN105607357A - Array substrate and manufacturing method thereof and display device - Google Patents
Array substrate and manufacturing method thereof and display device Download PDFInfo
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- CN105607357A CN105607357A CN201610008966.9A CN201610008966A CN105607357A CN 105607357 A CN105607357 A CN 105607357A CN 201610008966 A CN201610008966 A CN 201610008966A CN 105607357 A CN105607357 A CN 105607357A
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- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 239000002070 nanowire Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims description 42
- 239000000243 solution Substances 0.000 claims description 40
- 239000000203 mixture Substances 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000010023 transfer printing Methods 0.000 claims description 7
- 239000012670 alkaline solution Substances 0.000 claims description 6
- 229910000029 sodium carbonate Inorganic materials 0.000 claims description 6
- CDBYLPFSWZWCQE-UHFFFAOYSA-L sodium carbonate Substances [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 7
- 238000010276 construction Methods 0.000 abstract 3
- 239000010409 thin film Substances 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 206010070834 Sensitisation Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
The invention relates to an array substrate and a manufacturing method thereof and a display device, and aims at solving the problem that in a manufacturing method of the array substrate of the prior art, graphs of an electrode layer and a flat layer can be completed by performing a graph construction technology for two times when ITO is adopted as the electrode layer. The array substrate comprises a lining substrate, the first electrode layer and the flat layer, wherein a thin film formed by connecting multiple conductive nanowires in a lapping mode is adopted as the first electrode layer, and the pattern of the first electrode layer is the same as that of the flat layer. The thin film formed by connecting the conductive nanowires in the lapping mode is adopted as the first electrode layer, the pattern of the flat layer is the same as that of the first electrode layer, and therefore the flat layer can be etched by adopting an exposure developing mode; a developing solution can be permeated to the flat layer through gaps formed among the conductive nanowires, the conductive nanowires which are located on the etched flat layer are simultaneously cleaned while the flat layer is cleaned, therefore, the graphs of the flat layer and the electrode layer are simultaneously formed through one-time performance of the graph construction technology, and one-time performance of the graph construction technology is omitted.
Description
Technical field
The present invention relates to display floater field, relate in particular to a kind of array base palte, its preparation method and show dressPut.
Background technology
Array base palte is the significant components of composition liquid crystal indicator, existing for ADS (AdvancedSuperDimensionSwitch, senior super dimension field switch) array base palte of display floater, in manufacturing processThe middle making that need to just can complete successively array base palte through minimum 6 composition techniques. And employing ITO(Indium-TinOxide, tin indium oxide) during as electrode layer, the figure of electrode layer and flatness layer needs twoInferior composition technique just can complete.
In sum, in the manufacture method of current existing array base palte, while adopting ITO as electrode layer,The figure of electrode layer and flatness layer needs twice composition technique just can complete.
Summary of the invention
A kind of array base palte, its preparation method and display unit that the embodiment of the present invention provides, existing in order to solveHave in the manufacture method of the array base palte existing in technology, while adopting ITO as electrode layer, electrode layer peaceThe problem that twice composition technique of figure needs of smooth layer just can complete.
A kind of array base palte that the embodiment of the present invention provides, comprising: underlay substrate, is arranged on underlay substrateEach pixel cell region in the first electrode layer, be arranged on described the first electrode layer below and with describedThe flatness layer that the first electrode layer directly contacts;
Wherein, described the first electrode layer film that many conducting nanowires are overlapped to form of serving as reasons; Described the first electrodeLayer is identical with the pattern of described flatness layer.
Because the first electrode layer in the present invention is to overlap by many conducting nanowires the film forming, and flatness layerThere is identical pattern with the first electrode layer, thereby can adopt the mode of exposure imaging to carry out etching to flatness layer,While development after exposure etching, developer solution can be penetrated into flat by the gap between conducting nanowiresSmooth layer, in cleaning flatness layer, can rinse out together and be positioned at the flatness layer top that etched awayConducting nanowires; And then form the figure of flatness layer and electrode layer by composition technique simultaneously, so notOnly can reduce composition technique one time, can also be cost-saving, improve production capacity.
Optionally, the material of described nano wire is nano metal.
Optionally, described nano metal is Nano Silver.
Optionally, the rugosity of described nano wire is not more than 1 μ m.
Optionally, the length of described nano wire is the pattern choosing according to described the first electrode layer and described flatness layerThe numerical value of getting.
Optionally, the length of described nano wire is 3 μ m-20 μ m.
Optionally, the transmitance of described the first electrode layer is greater than 80%.
Optionally, the resistance value of described the first electrode layer is not more than 200 ohms/square.
Optionally, also comprise: be arranged on described the first electrode layer top and there is the second electrode of shape of slitLayer.
Optionally, described the first electrode layer is common electrode layer, and described the second electrode lay is pixel electrode layer;Or,
Described the first electrode layer is pixel electrode layer, and described the second electrode lay is common electrode layer.
A kind of display unit that the embodiment of the present invention provides, comprises that the embodiment of the present invention provides described aboveArray base palte.
The making side of the embodiment of the present invention provides a kind of above-mentioned array base palte providing as the embodiment of the present inventionMethod, comprising:
On underlay substrate, form the flatness layer of a whole layer and the first electrode layer of a whole layer;
Use mask plate to form the pattern of described flatness layer and described the first electrode layer by composition technique;
Wherein, described the first electrode layer film that many conducting nanowires are overlapped to form of serving as reasons; Described the first electrodeLayer is identical with the pattern of described flatness layer.
Optionally, on underlay substrate, form the flatness layer of a whole layer and the first electrode layer of a whole layer, comprising:
On underlay substrate, deposit the flatness layer of a whole layer;
On described flatness layer, apply the volatilizable solution that a whole layer comprises conducting nanowires, wave so that describedSend out solution after volatilization, can form the first electrode layer of a whole layer;
Wherein, described volatilizable solution is the solution that can volatilize while exceeding preset temperature threshold value; Described defaultTemperature threshold is to make described array base palte that the minimum temperature value of fusing occur.
Optionally, on underlay substrate, form the flatness layer of a whole layer and the first electrode layer of a whole layer, comprising:
First electrode that comprises flatness layer and be overlapped to form by conducting nanowires of the whole layer of transfer printing one on underlay substrateThe laminated film of layer, forms and is positioned at the flatness layer of the whole layer on underlay substrate and the first electrode layer of a whole layer.
Optionally, use mask plate to form described flatness layer and described the first electrode layer by a composition techniquePattern, comprising:
Use mask plate to the described flatness layer etching of exposing;
After exposure completes, use developer solution to clean the part etching away on described flatness layer, and clearWash the conducting nanowires that is positioned at the part top etching away on described flatness layer off, form described flatness layer and instituteState the pattern of the first electrode layer.
Optionally, described developer solution is weakly alkaline solution.
Optionally, described weakly alkaline solution is Na2CO3Solution.
Optionally, described Na2CO3The concentration of solution is 0.1%-1%.
Brief description of the drawings
The structural representation of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention;
A kind of method of making the array base palte that the embodiment of the present invention provides that Fig. 2 provides for the embodiment of the present inventionFlow chart;
The first that Fig. 3 provides for the embodiment of the present invention forms the method flow diagram of flatness layer and the first electrode layer;
The second that Fig. 4 provides for the embodiment of the present invention forms the method flow diagram of flatness layer and the first electrode layer;
The structural representation of the first electrode layer that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 forms flatness layer and the first electrode layer figure for the composition technique passed through that the embodiment of the present invention providesThe method flow diagram of case;
The overall flow figure of the preparation method of the array base palte that Fig. 7 provides for the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearlyChu, intactly description, obviously, described embodiment is only the present invention's part embodiment, is not completeThe embodiment of portion. Based on the embodiment in the present invention, those of ordinary skill in the art are not making creativenessThe every other embodiment obtaining under work prerequisite, belongs to the scope of protection of the invention.
As shown in Figure 1, the structural representation of a kind of array base palte providing for the embodiment of the present invention, array basePlate comprises underlay substrate 101; Be positioned at the grid 102 on underlay substrate 101; Be positioned on underlay substrate 101,And the gate insulation layer 103 of cover gate 102 comprehensively; Be positioned at the active layer 104 on gate insulation layer 103; Be positioned atOn active layer 104, lay respectively at the source-drain electrode 105 of active layer 104 both sides; Be positioned on source-drain electrode 105The first insulating barrier 106; Be positioned at the flatness layer 107 on the first insulating barrier 106; Be positioned on flatness layer 107The first electrode layer 108; Be positioned at the second insulating barrier 109 on the first electrode layer 108; Be arranged on the first electrode layer108 tops and there is the second electrode lay 110 of shape of slit. In enforcement, except flatness layer 107 and the first electricityOutside utmost point layer 108, other rete all adopts standard technology of the prior art, in lower mask body pair array substrateFlatness layer 107 and the first electrode layer 108 be introduced.
As shown in Figure 1, this array base palte comprises: underlay substrate 101, is arranged on each on underlay substrate 101The first electrode layer 108 in pixel cell region, be arranged on the first electrode layer 108 belows and with the first electricityThe flatness layer 107 that utmost point layer 108 directly contacts; Wherein, the first electrode layer 108 many conducting nanowires of serving as reasons are takenThe film being connected into; The first electrode layer 108 is identical with the pattern of flatness layer 107.
In enforcement, in prior art, conventionally use ITO as electrode layer (i.e. the first electrode layer 108), useResin material is as flatness layer 107, and flatness layer 107 be positioned at the first electrode layer 108 belows and with the first electrodeLayer 108 is contact directly, to flatness layer 107 (such as resin) and the first electrode layer 108 (such as ITO)While carrying out composition, due to the ITO of a whole layer, can cause ITO to peel off along with resin, or ITOBy sheet peel off form bad, even thereby flatness layer 107 and the first electrode layer 108 have identical pattern,Also must adopt twice composition technique just can complete.
And the first electrode layer 108 providing in the embodiment of the present invention is formed by many conducting nanowires overlap jointsFilm, and flatness layer 107 and the first electrode layer 108 have identical pattern, thereby can adopt exposure imagingMode flatness layer 107 is carried out to etching, in the time that exposure is developed after etching, developer solution can pass throughGap between conducting nanowires is penetrated on flatness layer 107, in cleaning flatness layer 107, togetherRinse out the conducting nanowires that is positioned at flatness layer 107 tops that etched away, and then by a composition workSkill forms the figure of flatness layer 107 and the first electrode layer 108 simultaneously, so not only can reduce composition one timeTechnique, can also be cost-saving, improves production capacity.
In enforcement, many conducting nanowires of composition the first electrode layer 108, can be can be made into arbitrarilyThe conductive material of nanoscale fine rule, optional, the material of nano wire is nano metal. And the embodiment of the present inventionIn nano metal can be the metal that can conduct electricity arbitrarily, optional, nano metal is Nano Silver.
Concrete, for many conducting nanowires of above-mentioned composition the first electrode layer 108, ensureing resistance valueSituation under more carefully better because thinner transmitance will be higher, visual effect can be better, do not have mist coverThe visual effect of covering; Optionally, the rugosity of nano wire is not more than 1 μ m.
The length of conducting nanowires is chosen according to the pattern of the first electrode layer and flatness layer, for example,Choose according to the pore size of exposure, just select if hole is smaller the conducting nanowires that length is less,Prevent like this in the time rinsing with developer solution, conducting nanowires is long and remain on flatness layer 107;Optionally, the length of nano wire is the numerical value of choosing according to the pattern of the first electrode layer and flatness layer. Nano wireLength be 3 μ m-20 μ m.
In enforcement, the resistance value of the first electrode layer (being square resistance) is relevant with the transmitance of the first electrode layer,Transmitance is larger and resistance value is the smaller the better, and optional, the transmitance of the first electrode layer is greater than 80%. FirstThe resistance value of electrode layer is not more than 200 ohms/square. The embodiment of the present invention draws through overtesting, is ensureing thoroughlyIn more than 90% situation of the rate of crossing, the resistance value minimum of the first electrode layer can be accomplished 20 ohms/square, therebyTransmitance can reach more than 90%.
As shown in Figure 1, in the above-mentioned array base palte providing in the embodiment of the present invention, optional, also comprise:Be arranged on the first electrode layer 108 tops and there is the second electrode lay 110 of shape of slit. As shown in Figure 1,One electrode layer 108 is plane-shape electrode, and the second electrode 110 is gap electrode.
In the above-mentioned array base palte providing in the embodiment of the present invention, according to the different display mode of display floater,Optionally, the first electrode layer 108 is common electrode layer, and the second electrode lay 110 is pixel electrode layer; OrIt is another kind of mode. Optionally, the first electrode layer 108 is pixel electrode layer, and the second electrode lay 110 is publicCommon electrode layer. In the specific implementation, can be according to actual needs, by the concrete display mode of display floaterDecide.
In enforcement, the array base palte that the embodiment of the present invention provides can be comprise electrode layer and flatness layer anyThe array base palte of display mode, for example, be applied to ADS (AdvancedSuperDimensionSwitch,Senior super dimension field switch) array base palte of display floater. And the present invention adopts conducting nanowires as electrode layerThought, also can carry out other distortion and application, for example, apply it in other rete, orAdopt other material to make fine rule, to reach the object etc. that reduces manufacture craft.
It should be noted that, the present invention is in the time that common electrode layer is slit-shaped electrode layer, and pixel electrode layer is plateShape electrode layer, the image that such set-up mode can be realized high-quality shows.
Based on same inventive concept, the embodiment of the present invention also provides above-mentioned that a kind of embodiment of the present invention providesThe preparation method of array base palte, because the principle that the method is dealt with problems is similar to aforementioned a kind of array base palte,Therefore the enforcement of the method can be referring to the enforcement of array base palte, repeats part and repeat no more.
The above-mentioned array base palte that the embodiment of the present invention provides, its main beneficial effect is to reduce composition one timeTechnique, when array base palte is made in lower mask body introduction, makes the process of the first electrode layer and flatness layer. As Fig. 2Shown in, a kind of method stream of making the array base palte that the embodiment of the present invention provides providing for the embodiment of the present inventionCheng Tu, concrete steps comprise:
Step 201 forms the flatness layer of a whole layer and the first electrode layer of a whole layer on underlay substrate;
Step 202, is used mask plate to form the pattern of flatness layer and the first electrode layer by composition technique;
Wherein, the first electrode layer film that many conducting nanowires are overlapped to form of serving as reasons; The first electrode layer and smoothThe pattern of layer is identical.
Make the embodiment of the present invention provide array base palte time, due to the pattern of the first electrode layer and flatness layerIdentical, and the first electrode layer adopts the film being overlapped to form by many conducting nanowires, thereby need first at substrate(forming a whole layer does not have figuratum on substrate, to form the flatness layer of a whole layer and the first electrode layer of a whole layerRete), and adopt composition technique to form the pattern of flatness layer and the first electrode layer. Lower mask body introduction asWhat forms flatness layer and first electrode layer of one whole layer.
As shown in Figure 3, the first providing for the embodiment of the present invention forms the side of flatness layer and the first electrode layerMethod flow chart. In enforcement, the embodiment of the present invention provides a kind ofly makes the array base that the embodiment of the present invention providesIn the method for plate, the implementation of step 201, can specifically realize in the following ways:
Step 301 deposits the flatness layer of whole layer on underlay substrate;
Step 302 applies the volatilizable solution that a whole layer comprises conducting nanowires, so that can wave on flatness layerSend out solution after volatilization, can form the first electrode layer of a whole layer;
Wherein, volatilizable solution is the solution that can volatilize while exceeding preset temperature threshold value; Preset temperature threshold valueFor making array base palte that the minimum temperature value of fusing occur.
In step 301, can adopt existing mode, on underlay substrate, deposit the flatness layer of a whole layer;After having deposited flatness layer, on flatness layer, make the first electrode layer, because the embodiment of the present invention providesThe first electrode layer film that many conducting nanowires are overlapped to form of serving as reasons, thereby can be by conducting nanowires is putEnter in volatilizable solution, and the method that applies volatilizable solution on flatness layer makes the first electrode layer, existIn step 302, can on flatness layer, apply the volatilizable solution that a whole layer comprises conducting nanowires, so thatVolatilizable solution, after volatilization, can form the first electrode layer of a whole layer.
The method that the volatilizable solution that adopts above-mentioned coating to comprise conducting nanowires is made the first electrode layer, forAccelerate the volatilization of volatilizable solution, can be before carrying out composition, pair array substrate carries out low temperature drying, withPromote the volatilization of volatilizable solution, preferably, can, at the temperature of 110 DEG C, dry 130s.
As shown in Figure 4, the second providing for the embodiment of the present invention forms the side of flatness layer and the first electrode layerMethod flow chart. In enforcement, the embodiment of the present invention provides a kind ofly makes the array base that the embodiment of the present invention providesIn the method for plate, the implementation of step 201, also realizes in the following ways:
Step 401, on underlay substrate, transfer printing one whole layer comprises flatness layer and is overlapped to form by conducting nanowiresThe laminated film of the first electrode layer, forms and is positioned at the of the flatness layer of the whole layer on underlay substrate and a whole layerOne electrode layer.
Except the above-mentioned method that applies the volatilizable solution that comprises conducting nanowires on flatness layer, also canTo adopt the mode of transfer printing laminated film, be about to the flatness layer of a whole layer and be overlapped to form by conducting nanowiresThe first electrode layer of a whole layer, be made into the form of laminated film, directly on underlay substrate, transfer printing one is wholeThe laminated film of layer, is positioned at the flatness layer of the whole layer on underlay substrate and the first electrode of a whole layer to formLayer.
In enforcement, above-mentioned two kinds of methods of making the first electrode layer, are all in order to form by many on flatness layerThe film that bar conducting nanowires is overlapped to form, and the parameter such as length, rugosity of conducting nanowires is at above-mentioned array baseIn the introduction of plate, provide, in the embodiment of the present invention, form the conducting nanowires of the first electrode layer, do not limitThe mode of fixed its arrangement, and concrete position, the thickness etc. of arranging can be adjusted as required, but frontCarry and must ensure that film that conducting nanowires is overlapped to form can realize the function of the first electrode layer completely, and rightAfter the first electrode layer carries out composition, also can not affect the function of the first electrode layer. As shown in Figure 5, be thisThe structural representation of the first electrode layer that inventive embodiments provides, in figure, the rambling fine rule of white isConducting nanowires 501, the grey color part of seeing, is the flatness layer of seeing from the gap of conducting nanowires107。
And form the figure of flatness layer and the first electrode layer for composition technique mentioning in the embodiment of the present inventionCase, the mode of concrete composition technique does not limit, and preferably, the present invention adopts the mode of exposure imaging to enterRow composition.
As shown in Figure 6, the composition technique of passing through providing for the embodiment of the present invention forms flatness layer and firstThe method flow diagram of electrode layer pattern. In enforcement, the one that the embodiment of the present invention provides is made the invention processIn the method for the array base palte that example provides, the implementation of step 202, can be specifically real in the following waysExisting:
Step 601, is used mask plate to the flatness layer etching of exposing;
Step 602, after exposure completes, is used developer solution to clean the part etching away on flatness layer,And wash the conducting nanowires that is positioned at the part top etching away on flatness layer, form flatness layer and the first electricityThe pattern of utmost point layer.
The mode of the exposure etching that the embodiment of the present invention provides, can be the mode that adopts laser explosure, due toThe material (such as resin) of flatness layer has the character of sensitization, thereby without applying photoresist, just can be straightConnect flatness layer is exposed, in the time that the exposure machine adopting is different, the relevant ginsengs such as time for exposure and exposure intensityNumber is not identical yet, and the material, the thickness of flatness layer etc. that adopt to flatness layer relevant simultaneously, in concrete enforcementTime, can adjust according to actual needs.
For the preparation method of array base palte is more clearly described, the method is to adopt transfer printing laminated filmMode is made flatness layer and first electrode layer of a whole layer. As shown in Figure 7, for the embodiment of the present invention providesThe overall flow figure of the preparation method of array base palte, concrete steps comprise:
Step 701, on underlay substrate, transfer printing one whole layer comprises flatness layer and is overlapped to form by conducting nanowiresThe laminated film of the first electrode layer, forms and is positioned at the of the flatness layer of the whole layer on underlay substrate and a whole layerOne electrode layer;
Step 702, is used mask plate to the flatness layer etching of exposing;
Step 703, after exposure completes, is used developer solution to clean the part etching away on flatness layer,And wash the conducting nanowires that is positioned at the part top etching away on flatness layer, form flatness layer and the first electricityThe pattern of utmost point layer.
In enforcement, what the method for the exposure imaging that the embodiment of the present invention provides, do not have on developing processParticular/special requirement, and the above-mentioned developer solution that develops and use, must guarantee can be to not leading in the first electrode layerSusceptance rice noodles have impact, and the solution type that it is concrete can adopt developer solution conventional in prior art, canChoosing, developer solution is weakly alkaline solution. Preferably, this weakly alkaline solution is Na2CO3Solution. And Na2CO3The concentration of solution is 0.1%-1%.
Based on same inventive concept, the embodiment of the present invention also provides a kind of display unit, comprises that the present invention is realExecute the above-mentioned array base palte that example provides, this display unit can be: mobile phone, panel computer, television set, aobviousShow any product or parts with Presentation Function such as device, notebook computer, DPF, navigator. RightBe and will be understood by those skilled in the art that in other requisite part of this display unitHave, do not repeat at this, also should not serve as limitation of the present invention. The enforcement of this display unit canReferring to the embodiment of above-mentioned array base palte, repeat part and repeat no more.
In sum, because the first electrode layer in the present invention is to overlap by many conducting nanowires the film forming,Thereby in the time that exposure is developed after etching, developer solution can permeate by the gap between conducting nanowiresTo flatness layer, in cleaning flatness layer, can rinse out together and be positioned on the flatness layer having etched awayThe conducting nanowires of side; And then form the figure of flatness layer and electrode layer, this by composition technique simultaneouslySample not only can reduce composition technique one time, can also be cost-saving, improve production capacity.
Obviously, those skilled in the art can carry out various changes and modification and not depart from this present inventionBright spirit and scope. Like this, if of the present invention these amendment and modification belong to the claims in the present invention andWithin the scope of its equivalent technologies, the present invention be also intended to comprise these change and modification interior.
Claims (18)
1. an array base palte, is characterized in that, comprising: underlay substrate, is arranged on underlay substrateThe first electrode layer in each pixel cell region, is arranged on described the first electrode layer below and with described theThe flatness layer that one electrode layer directly contacts;
Wherein, described the first electrode layer film that many conducting nanowires are overlapped to form of serving as reasons; Described the first electrodeLayer is identical with the pattern of described flatness layer.
2. array base palte as claimed in claim 1, is characterized in that, the material of described nano wire is for receivingRice metal.
3. array base palte as claimed in claim 2, is characterized in that, described nano metal is Nano Silver.
4. array base palte as claimed in claim 1, is characterized in that, the rugosity of described nano wire is littleIn 1 μ m.
5. array base palte as claimed in claim 1, is characterized in that, the length of described nano wire is rootThe numerical value of choosing according to the pattern of described the first electrode layer and described flatness layer.
6. array base palte as claimed in claim 5, is characterized in that, the length of described nano wire is3μm-20μm。
7. array base palte as claimed in claim 1, is characterized in that, the seeing through of described the first electrode layerRate is greater than 80%.
8. array base palte as claimed in claim 7, is characterized in that, the resistance of described the first electrode layerValue is not more than 200 ohms/square.
9. the array base palte as described in claim 1-8 any one, is characterized in that, also comprises: arrangeAbove described the first electrode layer and there is the second electrode lay of shape of slit.
10. array base palte as claimed in claim 9, is characterized in that, described the first electrode layer is publicElectrode layer, described the second electrode lay is pixel electrode layer; Or,
Described the first electrode layer is pixel electrode layer, and described the second electrode lay is common electrode layer.
11. 1 kinds of display unit, is characterized in that, comprise the battle array as described in claim 1-10 any oneRow substrate.
The preparation method of 12. 1 kinds of array base paltes as described in claim 1-10 any one, is characterized in that,Comprise:
On underlay substrate, form the flatness layer of a whole layer and the first electrode layer of a whole layer;
Use mask plate to form the pattern of described flatness layer and described the first electrode layer by composition technique;
Wherein, described the first electrode layer film that many conducting nanowires are overlapped to form of serving as reasons; Described the first electrodeLayer is identical with the pattern of described flatness layer.
13. methods as claimed in claim 12, is characterized in that, form a whole layer on underlay substrateFlatness layer and the first electrode layer of a whole layer, comprising:
On underlay substrate, deposit the flatness layer of a whole layer;
On described flatness layer, apply the volatilizable solution that a whole layer comprises conducting nanowires, wave so that describedSend out solution after volatilization, can form the first electrode layer of a whole layer;
Wherein, described volatilizable solution is the solution that can volatilize while exceeding preset temperature threshold value; Described defaultTemperature threshold is to make described array base palte that the minimum temperature value of fusing occur.
14. methods as claimed in claim 12, is characterized in that, form a whole layer on underlay substrateFlatness layer and the first electrode layer of a whole layer, comprising:
First electricity that comprises flatness layer and be overlapped to form by conducting nanowires of the whole layer of transfer printing one on underlay substrateThe laminated film of utmost point layer, forms and is positioned at the flatness layer of the whole layer on underlay substrate and the first electrode of a whole layerLayer.
15. methods as claimed in claim 12, is characterized in that, use mask plate by a compositionTechnique forms the pattern of described flatness layer and described the first electrode layer, comprising:
Use mask plate to the described flatness layer etching of exposing;
After exposure completes, use developer solution to clean the part etching away on described flatness layer, and clearWash the conducting nanowires that is positioned at the part top etching away on described flatness layer off, form described flatness layer and instituteState the pattern of the first electrode layer.
16. methods as claimed in claim 15, is characterized in that, described developer solution is weakly alkaline solution.
17. methods as claimed in claim 16, is characterized in that, described weakly alkaline solution is Na2CO3Solution.
18. methods as claimed in claim 17, is characterized in that, described Na2CO3The concentration of solution is0.1％-1％。
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