CN105592290A - High-resolution video source compression method and high-resolution compressed video display method - Google Patents
High-resolution video source compression method and high-resolution compressed video display method Download PDFInfo
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- CN105592290A CN105592290A CN201410559305.6A CN201410559305A CN105592290A CN 105592290 A CN105592290 A CN 105592290A CN 201410559305 A CN201410559305 A CN 201410559305A CN 105592290 A CN105592290 A CN 105592290A
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Abstract
The invention relates to a high-resolution video source compression method and a high-resolution compressed video display method. The high-resolution video source compression method includes the following steps that: a video processing chip is adopted as a main control chip, the other at least one video processing chip is adopted as slave chips, and the main control chip is in serial connection with the slave chips; the main control chip receives high-resolution video source signals to be processed or high-resolution compressed video code streams to be processed, and thereafter, reserves a portion of the signals or video code streams and transfers the remaining part of the signals or video code streams to a slave chip connected with the main control chip, and the transfers the remaining part of the signals or video code streams to an n-th slave chip in the same manner until the high-resolution video source signals to be processed or high-resolution compressed video code streams to be processed are all allocated, wherein n is equal to and larger than 2; and the main control chip and the slave chips independently process parts allocated to them, and then the slave chips return processed results to the main control chip. According to the high-resolution video source compression method and the high-resolution compressed video display method of the present invention, the plurality of processing chips are interconnected, so that the performance of a video processing system can be significantly enhanced (be multiplied or be improved manyfold).
Description
Technical field
The present invention relates to a kind of electric video monitoring technique field, particularly a kind of high-resolution video source compression method and high scoreDistinguish rate compressed video display methods.
Background technology
Video monitoring system is to utilize Video Supervision Technique to survey, monitor the region of setting up defences, and shows in real time, records image scene,Electronic system or the network system of retrieval and demonstration history image. Along with the current continuous pursuit to monitoring image definition, heightClear video has become the Developing mainstream of current video monitoring, and all kinds of HD video Related products arise at the historic moment.
For example high-definition network camera conventionally with its resolution ratio namely the difference of pixel count but divide different size and classification, cityOn field, there is already the high-definition network camera of 1,000,000 above pixels, as 1280x720,1,300,000 pixels (1280x960),2000000 pixels (1920x1080 is full HD), 3,200,000 pixels (2048x1536) etc. and even higher by 5,000,000,8,000,000,1000The high-definition camera of ten thousand pixels. For another example, along with the growing market demand of consumer is in high-end demonstration field, from initial480P television picture tube TV set, the display device of the resolution ratio such as 720P, 1080P finally, 2K, 4K, 8K, showsThe size of resolution ratio and display device is progressively promoting. Video frequency processing chip is the core of all kinds of HD video Related productsHeart element, traditional video frequency processing chip, often only for specific indexes, just defines its property indices at the beginning of design,If internal bus bandwidth ability, processing resolution ratio etc. are all often just can meet the demands, surplus is very little, and this restrictionBe difficult to meet market for the demand of high-performance Video processing ability more current. In prior art, there is certain methods for this reasonThe performance that improves video frequency processing chip, as overclocking, Elevating Pressure Method, but these methods micro-tensioning system performance is among a small circle rightThe raising of video frequency processing chip performance is very limited, still can not meet current for the need of high-performance Video processing ability moreAsk.
Summary of the invention
The present embodiment provides a kind of high-resolution video source compression method and high-resolution compressed video display methods, and realization is lookedFrequently the significantly lifting for the treatment of system performance.
The one that the embodiment of the present invention provides ... (this part supplements after claims are finalized a text)
Technique scheme of the present invention has the following advantages compared to existing technology: the compression of high-resolution video of the present invention sourceMethod and high-resolution compressed video display methods, the mode interconnected by some process chip can significantly promote (multiplicationOr several times promote) performance of processing system for video.
Brief description of the drawings
For content of the present invention is more likely to be clearly understood, below according to a particular embodiment of the invention and in conjunction with attachedFigure, the present invention is further detailed explanation, wherein
Fig. 1 is the device pie graph of the high-resolution video source compression method that provides of one embodiment of the invention;
Fig. 2 is the device pie graph of the high-resolution compressed video display methods that provides of one embodiment of the invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, completeGround is described, and obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment. BaseEmbodiment in the present invention, those of ordinary skill in the art are not making obtain under creative work prerequisite allOther embodiment, belong to the scope of protection of the invention.
Fig. 1 is the device pie graph of the high-resolution video source compression method that provides of one embodiment of the invention. As Fig. 1 instituteShow, (Master) chip using a certain video frequency processing chip as master control, using other video frequency processing chips as subordinate chip(Slave); Between main control chip 1 and subordinate chip 2, subordinate chip 2 and subordinate chip 3, pass through HSSI High-Speed Serial Interface 4Connect successively. Meanwhile, main control chip 1, subordinate chip 2, subordinate chip 3 etc. connect by generic disk level shared bus 5Arrive together.
Particularly, pending high-resolution video source signal is introduced into main control chip 1, main control chip 1 receiver, video letterA part in number, then passes to connected subordinate chip 2 by remainder by HSSI High-Speed Serial Interface 4, withThis analogizes until be delivered to the individual subordinate chip 3 of n (n is positive integer and n >=2), until pending video source all by pointJoin complete, n=3 in the present embodiment.
The disposal ability of each process chip inside can only meet the real-time processing of a certain resolution ratio. Each process chip (nothingOpinion is main control chip or one or more subordinate chip) process and distribute to its pending high-resolution video source sheet respectivelySection. Process chip at different levels are independent encodes or other Video processing to the appropriate section in pending high-resolution video source,Generate compressed bit stream.
Subordinate chips at different levels are passed compressed bit stream after treatment back main control chip 1 by generic disk level shared bus 5, by leadingControl chip 1 carries out uniform packing storage or transmission to the compressed bit stream of handling, and realizes the compression in high-resolution video sourceAnd transmission.
Here the quantity that it should be noted that subordinate chip is by the size of pending high-resolution video source resolution ratio and everyIndividual video frequency processing chip determines the disposal ability of video source.
In an embodiment of the present invention, process chip at different levels may be identical to the disposal ability of video source, also likelyDifferent.
The method of utilizing the present embodiment by the interconnected mode of some process chip after, a high-resolution image is divided intoThe sub-block of several low resolution, transfers to each process chip parallel processing, thereby significantly promoted, (multiplication or several times are carriedRise) performance of processing system for video.
Fig. 2 is the device pie graph of the high-resolution compressed video display methods that provides of one embodiment of the invention. As Fig. 2Shown in, identical with compression end, (Master) chip using a certain video frequency processing chip as master control, by other Video processingChip is as subordinate chip (Slave); Master control (Master) chip 1 and subordinate chip (Slave) 2, subordinate chip 2And be connected successively by HSSI High-Speed Serial Interface 4 between subordinate chip 3. Meanwhile, main control chip 1, subordinate chip 2, subordinateChip 3 grades connect together by generic disk level shared bus 5. Its difference is only, in order to allow user more intuitivelyView video decode effect, at main control chip, 1 place is also connected with display 6.
Particularly, pending high-resolution compressed video bit stream is introduced into main control chip 1, and main control chip 1 receives compressionA part in code stream, then passes to subordinate chip 2 by remainder by HSSI High-Speed Serial Interface 4, straight by that analogyTo being delivered to n (n is positive integer and n >=2) level subordinate chip 3, all quilts of pending high-resolution compressed video bit streamBe assigned, in the present embodiment n=3.
Process chip at different levels (main control chip and each subordinate chip) are independent of pending high-resolution compressed video bit streamAppropriate section is decoded, convergent-divergent processing, generates high-resolution compressed video.
Process chip at different levels are passed high-resolution compressed video after treatment back master control processing by generic disk level shared bus 5Chip 1, the display splicing that is carried out high-resolution compressed video by main control chip 1 shows afterwards on display 6.
It should be noted that according to size and the video frequency processing chip of pending high-resolution compressed video bit stream resolution ratioTo the disposal ability of compressed bit stream, select to arrange the quantity of video frequency processing chip.
The method of the present embodiment is divided into several by the interconnected mode of some process chip by high-resolution compressed video bit streamThe sub-block of low resolution, and by each process chip parallel processing, look thereby significantly promoted (multiplication or several times promote)Frequently the performance for the treatment of system.
In an embodiment of the present invention, can select the at different levels process chip identical to compressed bit stream disposal ability, convenient selectionThe quantity of video frequency processing chip is set. Certainly, also can select the process chip at different levels different to compressed bit stream disposal ability.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all in spirit of the present inventionWithin principle, any amendment of doing, be equal to replacement etc., within protection scope of the present invention all should be included in.
Claims (10)
1. a high-resolution video source compression method, is characterized in that, comprising:
Using a video frequency processing chip as main control chip, using other at least one video frequency processing chips as subordinate chip, mainControl chip and each subordinate chip are connected in series;
Main control chip receives after pending high-resolution video source signal, retains a part of pending video source signal, will remainRemaining part is divided and is passed to connected subordinate chip, is delivered to by that analogy last subordinate chip, looks until pendingFrequently source is all assigned with complete;
The appropriate section of main control chip and the independent pending video source that it is distributed of described at least one subordinate chip is carried outCoding, generates compressed bit stream;
Described at least one subordinate chip is passed compressed bit stream after treatment back described main control chip, by described main control chip pairThe compressed bit stream of handling carries out uniform packing storage or transmission.
2. method according to claim 1, is characterized in that, described main control chip and described at least one subordinate coreSheet is identical or different to the disposal ability of video source.
3. method according to claim 1 and 2, is characterized in that, described main control chip and described at least one fromBelong to chip, and utilize HSSI High-Speed Serial Interface to connect successively between described at least one subordinate chip.
4. according to the arbitrary described method of claim 1-3, it is characterized in that, described at least one subordinate chip is by logicalPass compressed bit stream after treatment back described main control chip by plate level shared bus.
5. according to the arbitrary described method of claim 1-4, it is characterized in that the quantity of described at least one subordinate chipSize and video frequency processing chip by described pending high-resolution video source resolution ratio are true to the disposal ability of video sourceFixed.
6. a high-resolution compressed video display methods, is characterized in that, comprising:
Using a video frequency processing chip as main control chip, using other at least one video frequency processing chips as subordinate chip, mainControl chip and each subordinate chip are connected in series;
Main control chip receives after pending high-resolution compressed video bit stream, retains a part of pending compressed video bit stream,Remainder is passed to connected subordinate chip, be delivered to by that analogy last subordinate chip, until wait to locateReason compressed video bit stream is all assigned with complete;
The corresponding portion of main control chip and the independent pending compressed video bit stream that it is distributed of described at least one subordinate chipDivide and decode, generating video source;
Described at least one subordinate chip is passed video source after treatment back described main control chip, by described main control chip to locatingThe video source of having managed is carried out tiled display.
7. method according to claim 6, is characterized in that, described main control chip and described at least one subordinate coreSheet is identical or different to the disposal ability of compressed bit stream.
8. according to the method described in claim 6 or 7, it is characterized in that, described main control chip and described at least one fromBelong to chip, and utilize HSSI High-Speed Serial Interface to connect successively between described at least one subordinate chip.
9. according to the arbitrary described method of claim 6-8, it is characterized in that, described at least one subordinate chip is by logicalPass compressed bit stream after treatment back described main control chip by plate level shared bus.
10. according to the arbitrary described method of claim 6-9, it is characterized in that the number of described at least one subordinate chipAmount is by size and the disposal ability of video frequency processing chip to compressed bit stream of described pending high-resolution compressed video bit streamDetermine.
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| CN201041670Y (en) * | 2007-04-10 | 2008-03-26 | 青岛海信电器股份有限公司 | Data transmission circuit and TV set using this circuit |
| CN101282478A (en) * | 2008-04-24 | 2008-10-08 | 上海华平信息技术股份有限公司 | Method and system for implementing parallel encoding of high-definition video |
| CN102510495A (en) * | 2011-10-12 | 2012-06-20 | 杭州华三通信技术有限公司 | Collaboration processing method and equipment for image |
| CN102547238A (en) * | 2011-12-29 | 2012-07-04 | 上海威乾视频技术有限公司 | Video cascade system applied in multi-channel DVRs (digital video recorder) and method |
| CN102572398A (en) * | 2012-01-06 | 2012-07-11 | 安科智慧城市技术（中国）有限公司 | Multi-path video processing device, multi-path video processing system and multi-path video processing method |
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Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1168053A (en) * | 1997-01-30 | 1997-12-17 | 广播电影电视部广播科学研究院电视研究所 | System for transmission of high distinctness TV by use of existing digital broadcast equipment |
| CN201041670Y (en) * | 2007-04-10 | 2008-03-26 | 青岛海信电器股份有限公司 | Data transmission circuit and TV set using this circuit |
| CN101282478A (en) * | 2008-04-24 | 2008-10-08 | 上海华平信息技术股份有限公司 | Method and system for implementing parallel encoding of high-definition video |
| CN102510495A (en) * | 2011-10-12 | 2012-06-20 | 杭州华三通信技术有限公司 | Collaboration processing method and equipment for image |
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Effective date of registration: 20180919 Address after: 411100 room 1006, innovation building, 9 Xiao Tang Road, hi tech Zone, Xiangtan, Hunan Applicant after: Xiangtan Zhongxing Electronics Co., Ltd. Address before: 519000 room 105, 6 Baohua Road, Hengqin New District, Zhuhai, Guangdong -478 Applicant before: GUANGDONG ZHONGXING ELECTRONICS CO., LTD. |
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Effective date of registration: 20190308 Address after: 519031 Room 105-15070, No. 6 Baohua Road, Hengqin New District, Zhuhai City, Guangdong Province Applicant after: Guangdong Vimicro Corp Address before: 411100 room 1006, innovation building, 9 Xiao Tang Road, hi tech Zone, Xiangtan, Hunan Applicant before: Xiangtan Zhongxing Electronics Co., Ltd. |
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