CN105573923A - Control circuit for accessing multi-block storage space - Google Patents
Control circuit for accessing multi-block storage space Download PDFInfo
- Publication number
- CN105573923A CN105573923A CN201510926803.4A CN201510926803A CN105573923A CN 105573923 A CN105573923 A CN 105573923A CN 201510926803 A CN201510926803 A CN 201510926803A CN 105573923 A CN105573923 A CN 105573923A
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- CN
- China
- Prior art keywords
- storage space
- control module
- pointer control
- read
- write
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
Abstract
The invention provides a control circuit for accessing a multi-block storage space. The control circuit comprises a write pointer control unit, a buffer unit, a read pointer control unit and a state management unit. The write pointer control unit is connected with the buffer unit, the write pointer control unit is connected with the state management unit, the read pointer control unit is connected with the buffer unit, and the read pointer control unit is connected with the state management unit. The control circuit provided by the invention can process the multi-block storage access of an upper layer program. The design method provided by the invention is used for improving the access efficiency of the multi-block storage. The interface circuit provided by the invention can adjust a buffer space by little modification.
Description
Technical field
The invention belongs to integrated circuit (IC) design technology, relate to a kind of control circuit of accessing polylith and storing.
Background technology
In system application, there are many application to need to divide polylith buffer memory and data are processed.Existing solution is generally adopt software to divide the function such as address switchover and control between each storage to complete storage space.But the program adds scale and the complicacy of software code, and owing to employing a large amount of pointers, increase the risk of system cloud gray model, and the operational efficiency of software is also low more than hardware, in order to solve the problem, the present invention proposes a kind of control circuit of accessing polylith storage space.
Summary of the invention
In order to solve the existing complexity by processor software code access polylith storage space, reliability and inefficient technical matters, the invention provides a kind of control circuit of accessing polylith storage space.
Solution technical scheme of the present invention:
Access a control circuit for polylith storage space, its special character is, comprises write pointer control module, buffer unit, read pointer control module and state managing unit;
State managing unit is used for: receive from external reference request, receive the write pointer from write pointer control module, receive the read pointer from read pointer control module, the using state of buffer unit is calculated according to write pointer and read pointer, send current using state and the write request of buffer unit to write pointer control module, send current using state and the read request of buffer unit to read pointer control module;
Described write pointer control module receives current using state from the buffer unit of state managing unit and write request, upgrades write pointer and feeds back to state managing unit,
Described read pointer control module receives current using state from the buffer unit of state managing unit and read request, upgrades read pointer and feeds back to state managing unit.
Technique effect of the present invention is:
The control circuit of access polylith storage space provided by the invention, by the control of the read-write pointer to storage space, simplifies the control work of upper layer software (applications).The start address that appointment one is fixing is only needed when upper application software operates spatial cache at every turn, do not need to be concerned about the blocked operation between each spatial cache, do not need to process a large amount of read-write pointer informations yet, decrease the complicacy of program, enhance the reliability of access process, improve the operational efficiency of system.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the control circuit of access polylith storage space of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail.
The structured flowchart of the control circuit of access polylith storage space of the present invention as shown in Figure 1, the invention provides a kind of control circuit of accessing polylith storage space, comprises write pointer control module, buffer unit, read pointer control module and state managing unit; Write pointer control module is connected with buffer unit, and write pointer control module is connected with buffer unit with state managing unit, read pointer control module, and read pointer control module is connected with state managing unit.
Wherein write pointer control module, for the address conversion between polylith storage space during controlling write operation; Be specially, after write pointer control module receives write request and writes data, adopt polling mechanism to determine to use which block storage space according to the storage space situation used last time, if first time operation is then from the first block cache space, add up successively according to polling mechanism later; After determining the storage space used, then on the basis, base address of this storage space, basis writes enable synchronized update write pointer; After current write operation completes, storage space seizure condition is reported to state managing unit.Buffer unit uses for storing data.
Read pointer control module is for the address conversion between polylith storage space during controlling read operation.
State managing unit is used for managed storage space hold status information, and it is mutual to complete with upper procedure.
The course of work of the control circuit of the access polylith storage space of the present embodiment is: first, after write pointer control module receives write request and writes data, polling mechanism is adopted to determine to use which block storage space according to the storage space situation used last time, if first time, operation was then from the first block cache space, add up successively according to polling mechanism later; Then also data are write in the corresponding address of buffer unit according to writing enable synchronized update write pointer on the basis, base address of this storage space after determining the storage space used simultaneously; After current write operation completes, storage space seizure condition is reported to state managing unit.State managing unit 4 informs read pointer control module after receiving storage space seizure condition, read pointer control module determines the need of sense data according to configuration after receiving storage space seizure condition information, if desired sense data, the storage space information then read according to the last time adopts polling mechanism to determine to read the data of which block storage space, and by this storage space of write pointers point, according to reading enable signal, read pointer is cumulative successively until this operation terminates during read data; The storage space seizure condition clear signal that after this read operation completes, feedback is corresponding is to state managing unit.State managing unit removes corresponding storage space occupied information after receiving storage space seizure condition clear signal, and by its synchronized update in the readable register of upper level applications.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although explain invention has been with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (1)
1. access a control circuit for polylith storage space, it is characterized in that, comprise write pointer control module, buffer unit, read pointer control module and state managing unit;
State managing unit is used for: receive from external reference request, receive the write pointer from write pointer control module, receive the read pointer from read pointer control module, the using state of buffer unit is calculated according to write pointer and read pointer, send current using state and the write request of buffer unit to write pointer control module, send current using state and the read request of buffer unit to read pointer control module;
Described write pointer control module receives current using state from the buffer unit of state managing unit and write request, upgrades write pointer and feeds back to state managing unit,
Described read pointer control module receives current using state from the buffer unit of state managing unit and read request, upgrades read pointer and feeds back to state managing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510926803.4A CN105573923A (en) | 2015-12-11 | 2015-12-11 | Control circuit for accessing multi-block storage space |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510926803.4A CN105573923A (en) | 2015-12-11 | 2015-12-11 | Control circuit for accessing multi-block storage space |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105573923A true CN105573923A (en) | 2016-05-11 |
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| CN201510926803.4A Pending CN105573923A (en) | 2015-12-11 | 2015-12-11 | Control circuit for accessing multi-block storage space |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002108714A (en) * | 2000-09-29 | 2002-04-12 | Sony Corp | Memory device and access limiting method |
| US20070067559A1 (en) * | 2005-09-22 | 2007-03-22 | Akira Fujibayashi | Storage control apparatus, data management system and data management method |
| CN102096648A (en) * | 2010-12-09 | 2011-06-15 | 深圳中兴力维技术有限公司 | System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array) |
| CN104731747A (en) * | 2013-12-20 | 2015-06-24 | 中国航空工业集团公司第六三一研究所 | Method for hierarchically buffering high-speed bus data during receiving |
| CN104767914A (en) * | 2015-04-20 | 2015-07-08 | 哈尔滨工业大学 | Parallel digital image signal receiving system based on RS-422 level |
-
2015
- 2015-12-11 CN CN201510926803.4A patent/CN105573923A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002108714A (en) * | 2000-09-29 | 2002-04-12 | Sony Corp | Memory device and access limiting method |
| US20070067559A1 (en) * | 2005-09-22 | 2007-03-22 | Akira Fujibayashi | Storage control apparatus, data management system and data management method |
| CN102096648A (en) * | 2010-12-09 | 2011-06-15 | 深圳中兴力维技术有限公司 | System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array) |
| CN104731747A (en) * | 2013-12-20 | 2015-06-24 | 中国航空工业集团公司第六三一研究所 | Method for hierarchically buffering high-speed bus data during receiving |
| CN104767914A (en) * | 2015-04-20 | 2015-07-08 | 哈尔滨工业大学 | Parallel digital image signal receiving system based on RS-422 level |
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Application publication date: 20160511 |