CN105573885A - Method and device for monitoring and counting bottom hardware behaviours - Google Patents
Method and device for monitoring and counting bottom hardware behaviours Download PDFInfo
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- CN105573885A CN105573885A CN201510718898.0A CN201510718898A CN105573885A CN 105573885 A CN105573885 A CN 105573885A CN 201510718898 A CN201510718898 A CN 201510718898A CN 105573885 A CN105573885 A CN 105573885A
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Abstract
The invention discloses a method and device for monitoring and counting bottom hardware behaviours. The method comprises the following steps that: a monitoring and counting module is connectedly hung on a bus of a centre processing unit CPU; and the monitoring and counting module counts and monitors bottom hardware behaviours of an upper-layer application and performs classified statistic of the bottom hardware behaviours of the upper-layer application, such that the classified statistic data of the bottom hardware behaviours of the upper-layer application are obtained.
Description
Technical field
The present invention relates to technical field of intelligent card, particularly relate to and a kind ofly monitor and add up method and the device of bottom hardware behavior.
Background technology
Smart card comprises bottom hardware and upper layer software (applications).Along with the development of application, it has been a kind of trend that smart card transforms from native card to JAVA card, it is also proposed higher requirement to performance simultaneously.So, when card performance does not meet application demand, we need the key factor finding restriction performance, as slow in which module runtime, which module be scheduled often, high to the visiting frequency of any block storage, there are these bottom-up informations, just can have carried out the optimization of software and hardware targetedly.So for the complication system that JAVA card is such, comprise bottom hardware, JAVA virtual machine, application Applet three-decker, how the bottleneck of quick position restriction Applet layer application performance, and improved; Usually two kinds of methods are had in prior art:
One, application programs is successively decomposed, and learns the dispatch situation of certain application to low-level hardware by analyzing; The shortcoming of this method be workload large, analyze inaccurate, repeatable difference and inefficiency;
Two, emulated by application program and obtain bottom hardware operation information; The shortcoming of this method is speed slow (especially for large-scale application program), and is not easy to add up the hardware scheduling information that distinct program performs section.
Summary of the invention
For solving the technical matters of existing existence, the embodiment of the present invention expects that providing a kind of monitors and add up method and the device of bottom hardware behavior.
For achieving the above object, the embodiment of the present invention realizes in the following ways:
Embodiments provide and a kind ofly monitor and add up the method for bottom hardware behavior, described method comprises:
Central processor CPU bus mounts monitoring and statistics module; Described monitoring and statistics module is added up and is monitored the bottom hardware behavior of upper layer application, and carries out statistic of classification to the bottom hardware behavior of described upper layer application, obtains the classifiction statistics of the bottom hardware behavior of upper layer application.
In such scheme, the object of described statistic of classification comprise following one of at least: the number of times of the number of operations of particular module, the working time of particular module, CPU access program storer, the number of times of CPU accesses data memory, CPU perform the time of specific program.
In such scheme, described method also comprises:
For each objects of statistics, all enable switch is set, can starts at any time in program operation process and close described enable switch.
In such scheme, described method also comprises: arrange corresponding register respectively for different objects of statistics and be used for storage statistical data.
In such scheme, described method also comprises:
Statistical operation counter realizes, and described counter adopts the clock source of on-site programmable gate array FPGA external stabilization.
The embodiment of the present invention additionally provides a kind ofly monitors and adds up the device of bottom hardware behavior, and described device comprises: monitoring and statistics module, and described monitoring and statistics module is articulated in central processor CPU bus; Described monitoring and statistics module for adding up and monitoring the bottom hardware behavior of upper layer application, and carries out statistic of classification to the bottom hardware behavior of described upper layer application, obtains the classifiction statistics of the bottom hardware behavior of upper layer application.
In such scheme, the object of described statistic of classification comprise following one of at least: the number of times of the number of operations of particular module, the working time of particular module, CPU access program storer, the number of times of CPU accesses data memory, CPU perform the time of specific program.
In such scheme, monitoring and statistics module comprises n cluster counters and n group register, n be greater than 1 integer; Every cluster counters works alone and controls by enable switch respectively, only have enable effective time, described counter just can carry out statistical counting; Often organize the statistics that register is used for preserving corresponding counter.
In such scheme, described counter adopts the clock source of on-site programmable gate array FPGA external stabilization.
What the embodiment of the present invention provided a kind ofly monitors and adds up method and the device of bottom hardware behavior, for monitoring the behavior of bottom hardware in certain upper layer application, and carries out statistic of classification record.The embodiment of the present invention does not affect the normal execution of bottom hardware, can be enable or close statistical function at any time, and realize the derivation of statistics, decomposing for upper layer application provides data supporting, be conducive to better positioning performance bottleneck, and carry out performance optimization targetedly.
Accompanying drawing explanation
Fig. 1 is that the embodiment of the present invention a kind of monitors and add up the apparatus structure schematic diagram of bottom hardware behavior;
Fig. 2 is the structural representation of a kind of monitoring and statistics module of the embodiment of the present invention;
Fig. 3 is the implementing procedure figure of a kind of monitoring and statistics method of the embodiment of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the technical solution of the present invention is further elaborated.
What the embodiment of the present invention provided a kind ofly monitors and adds up the method for bottom hardware behavior, mainly comprises: in central processing unit (CPU) bus, mount monitoring and statistics module; Described monitoring and statistics module is added up and is monitored the bottom hardware behavior of upper layer application, and carries out statistic of classification to the bottom hardware behavior of described upper layer application, obtains the classifiction statistics of the bottom hardware behavior of upper layer application.
The embodiment of the present invention designs a monitoring and statistics module, and for obtaining chip run duration, CPU performs instruction and the time devided modulation situation of accessing each hardware module, and the number of run of peripheral hardware IP.This monitoring and statistics module, as from equipment, is articulated to (as ahb bus) on cpu bus, specifically can be shown in Figure 1.
This module only realizes monitoring and statistics function, not affecting CPU normally to perform, simultaneously in order to save area and power consumption, can remove in the formal chip produced, only realize in programmable gate array (FPGA, FieldProgrammableGateArray) system verification version at the scene.
Wherein, the object of described statistic of classification comprise following one of at least: the number of times of the number of operations of particular module, the working time of particular module, CPU access program storer, the number of times of CPU accesses data memory, CPU perform time of specific program etc.Had these information, just can:
1, obtain CPU fetching and perform whether there is hardware bottleneck, and then proposing innovative approach.
2, after learning that the different program of execution or program are revised, CPU performs the situation of change of instruction and access hardware module time, and then confirms the improvement effect of program.
The content of concrete statistics can be determined according to the actual requirements, but in order to ensure dirigibility, for each objects of statistics, all arranges enable switch, can start at any time in program operation process and close, arrange special register to store statistics simultaneously.Statistical operation can realize with counter, in order to ensure some timing statistical accuracy, the stabilizing clock of FPGA outside can be adopted to count.
After program end of run, statistics can be checked by the window of compiler, such as: the Memory window by Keil is checked, or derive statistics, for applied analysis by Keil order line.
Monitoring and statistics module as above, can be realized by n cluster counters and n group register, n be greater than 1 integer, specifically see Fig. 2.Counter number and register number are determined according to real needs, and every cluster counters works alone, and automatically add 1 when satisfied counting condition.Wherein, every cluster counters is all subject to enable control, only have enable effective time, just can carry out statistical counting." statistical signal n " is from peripheral module, different according to objects of statistics difference, if objects of statistics is the execution time of certain section of program, then statistical signal is clock, as the number of run that objects of statistics is certain peripheral module, then statistical signal is the startup id signal of this module.
Describe the monitoring and statistics implementation process of the embodiment of the present invention again see Fig. 3, Fig. 3, comprise lower several step:
301, determine objects of statistics, and before application program to be assessed is run, it is enable that corresponding statistics is set;
302, run application program to be assessed, in program operation process, monitoring and statistics module can carry out statistical counting for different objects;
303, program is run complete, closes and adds up enable;
304, statistics is derived, for application assessment.
In sum, the embodiment of the present invention is used for the behavior of monitoring bottom hardware in certain upper layer application, and carries out statistic of classification record.The embodiment of the present invention does not affect the normal execution of bottom hardware, can be enable or close statistical function at any time, and realize the derivation of statistics, decomposing for upper layer application provides data supporting, be conducive to better positioning performance bottleneck, and carry out performance optimization targetedly.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (9)
1. monitor and add up the method for bottom hardware behavior, it is characterized in that, described method comprises:
Central processor CPU bus mounts monitoring and statistics module; Described monitoring and statistics module is added up and is monitored the bottom hardware behavior of upper layer application, and carries out statistic of classification to the bottom hardware behavior of described upper layer application, obtains the classifiction statistics of the bottom hardware behavior of upper layer application.
2. monitor according to claim 1 and add up the method for bottom hardware behavior, it is characterized in that, the object of described statistic of classification comprise following one of at least: the number of times of the number of operations of particular module, the working time of particular module, CPU access program storer, the number of times of CPU accesses data memory, CPU perform the time of specific program.
3. monitor according to claim 1 or 2 and add up the method for bottom hardware behavior, it is characterized in that, described method also comprises:
For each objects of statistics, all enable switch is set, can starts at any time in program operation process and close described enable switch.
4. monitor according to claim 1 or 2 and add up the method for bottom hardware behavior, it is characterized in that, described method also comprises: arrange corresponding register respectively for different objects of statistics and be used for storage statistical data.
5. monitor according to claim 1 or 2 and add up the method for bottom hardware behavior, it is characterized in that, described method also comprises:
Statistical operation counter realizes, and described counter adopts the clock source of on-site programmable gate array FPGA external stabilization.
6. monitor and add up the device of bottom hardware behavior, it is characterized in that, described device comprises: monitoring and statistics module, and described monitoring and statistics module is articulated in central processor CPU bus; Described monitoring and statistics module for adding up and monitoring the bottom hardware behavior of upper layer application, and carries out statistic of classification to the bottom hardware behavior of described upper layer application, obtains the classifiction statistics of the bottom hardware behavior of upper layer application.
7. monitor according to claim 6 and add up the device of bottom hardware behavior, it is characterized in that, the object of described statistic of classification comprise following one of at least: the number of times of the number of operations of particular module, the working time of particular module, CPU access program storer, the number of times of CPU accesses data memory, CPU perform the time of specific program.
8. monitor according to claim 6 or 7 and add up the device of bottom hardware behavior, it is characterized in that, monitoring and statistics module comprises n cluster counters and n group register, n be greater than 1 integer; Every cluster counters works alone and controls by enable switch respectively, only have enable effective time, described counter just can carry out statistical counting; Often organize the statistics that register is used for preserving corresponding counter.
9. monitor according to claim 8 and add up the device of bottom hardware behavior, it is characterized in that, described counter adopts the clock source of on-site programmable gate array FPGA external stabilization.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106227641A (en) * | 2016-07-29 | 2016-12-14 | 北京润科通用技术有限公司 | A kind of hardware performance monitoring method and system |
| CN108874613A (en) * | 2017-05-10 | 2018-11-23 | 鸿秦（北京）科技有限公司 | A kind of performance bottleneck positioning quantization method, device and Embedded I/O System |
| CN111611199A (en) * | 2020-04-16 | 2020-09-01 | 福州瑞芯微电子股份有限公司 | Method, device, equipment and medium for optimizing performance and power consumption of Soc chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101067797A (en) * | 2007-06-25 | 2007-11-07 | 中兴通讯股份有限公司 | Processor availability measuring device and method |
| US20070294583A1 (en) * | 2004-02-09 | 2007-12-20 | Continental Teves Ag & Co. Ohg | Device and Method for Analyzing Embedded Systems for Safety-Critical Computer Systems in Motor Vehicles |
| CN102184134A (en) * | 2010-06-22 | 2011-09-14 | 上海盈方微电子有限公司 | System-on-chip performance analyzer |
-
2015
- 2015-10-30 CN CN201510718898.0A patent/CN105573885A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070294583A1 (en) * | 2004-02-09 | 2007-12-20 | Continental Teves Ag & Co. Ohg | Device and Method for Analyzing Embedded Systems for Safety-Critical Computer Systems in Motor Vehicles |
| CN101067797A (en) * | 2007-06-25 | 2007-11-07 | 中兴通讯股份有限公司 | Processor availability measuring device and method |
| CN102184134A (en) * | 2010-06-22 | 2011-09-14 | 上海盈方微电子有限公司 | System-on-chip performance analyzer |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106227641A (en) * | 2016-07-29 | 2016-12-14 | 北京润科通用技术有限公司 | A kind of hardware performance monitoring method and system |
| CN106227641B (en) * | 2016-07-29 | 2019-01-29 | 北京润科通用技术有限公司 | A kind of hardware performance monitoring method and system |
| CN108874613A (en) * | 2017-05-10 | 2018-11-23 | 鸿秦（北京）科技有限公司 | A kind of performance bottleneck positioning quantization method, device and Embedded I/O System |
| CN108874613B (en) * | 2017-05-10 | 2021-11-05 | 鸿秦（北京）科技有限公司 | Method and device for positioning and quantizing performance bottleneck and embedded IO system |
| CN111611199A (en) * | 2020-04-16 | 2020-09-01 | 福州瑞芯微电子股份有限公司 | Method, device, equipment and medium for optimizing performance and power consumption of Soc chip |
| CN111611199B (en) * | 2020-04-16 | 2023-04-11 | 瑞芯微电子股份有限公司 | Method, device, equipment and medium for optimizing performance and power consumption of Soc chip |
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