CN105553614B - Integrating device based on signal detection algorithm - Google Patents
Integrating device based on signal detection algorithm Download PDFInfo
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- CN105553614B CN105553614B CN201510925676.6A CN201510925676A CN105553614B CN 105553614 B CN105553614 B CN 105553614B CN 201510925676 A CN201510925676 A CN 201510925676A CN 105553614 B CN105553614 B CN 105553614B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/0413—MIMO systems
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a kind of integrating device based on signal detection algorithm, which includes: matrix and matched filtering computing module, for obtaining the first matrix, matched filtering vector and the second matrix；Preprocessing module, for obtaining parameter matrix, primary vector and efficient channel gain according to the first matrix, matched filtering vector and the second matrix；Iteration module obtains testing result vector for being iterated by parameter matrix, primary vector；And max log likelihood ratio computing module, max log likelihood ratio is obtained by testing result vector and efficient channel gain.The integrating device is big based on the ultra-large integrated circuit structure special data throughout that extensive multiple-input and multiple-output is designed, and arithmetic speed is fast, low in energy consumption.
Description
Technical field
The present invention relates to field of communication technology, in particular to a kind of integrating device based on signal detection algorithm.
Background technique
With the development of communication technology, frequency spectrum resource becomes more and more rare.How to allow data can it is more, faster into
Row transmission is current urgent problem.
In the related technology, multiple data stream is carried out by extensive multi-input multi-output system to pass simultaneously in identical frequency band
It is defeated, although solving the problems, such as multiple data stream, the transmission rate of multiple data stream is not effectively improved.Nowadays, in order to
Improve data transfer rate, it will usually it is improved from two angles of algorithm and implementation, it is more commonly used from algorithm angle
Have squeeze theorem method (ZF), least mean-square error (MMSE), globular decoding (SD) etc., these algorithms it is different degrees of reduce meter
Complexity is calculated, arithmetic speed is improved.However, from the angle of implementation, although making these by writing one section of detection program
Algorithm is run on aageneral-purposeaprocessor, but the efficiency of transmission of data is lower, is not well positioned to meet the demand of line communication.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.
For this purpose, it is an object of the invention to propose a kind of integrating device based on signal detection algorithm, the integrating device energy
It is enough to realize the detection and decoding for wirelessly communicating extensive multi-input multi-output system, make full use of data parallelism to calculate.
In order to achieve the above objectives, the embodiment of the present invention proposes a kind of integrating device based on signal detection algorithm, comprising:
Matrix and matched filtering computing module, steady rayleigh distributed channel matrix, base station end for being obtained according to signal detection receive
The power spectral density and transmission vector power of the signal vector, noise that arrive obtain the first matrix, matched filtering vector and the
Two matrixes；Preprocessing module, for being located in advance to first matrix, the matched filtering vector and second matrix
Reason, to obtain parameter matrix, primary vector and efficient channel gain；Iteration module, for passing through the parameter matrix, described
Primary vector is iterated calculating, to obtain testing result vector；And max log likelihood ratio computing module, pass through the inspection
It surveys result vector and the efficient channel gain obtains max log likelihood ratio.
Integrating device according to an embodiment of the present invention based on signal detection algorithm is obtained steady auspicious by signal detection
Sharp distribution channel matrix, the signal vector that base station end receives, the power spectral density of noise and transmission vector power obtain most
Max log likelihood ratio afterwards, thus realize the detection and decoding for wirelessly communicating extensive multi-input multi-output system, it is sufficiently sharp
It is calculated with data parallelism, realizes the detection decoding of high-speed low-power-consumption.
In addition, the integrating device according to the above embodiment of the present invention based on signal detection algorithm can also have it is following attached
The technical characteristic added:
Further, in one embodiment of the invention, the matrix and matched filtering computing module include: multiple the
One processing unit, the signal vector for being received according to the steady rayleigh distributed channel matrix and the base station end obtain institute
State matched filtering vector, first matrix, first matrix the elements in a main diagonal and first matrix master it is diagonal
The inverse of line element；Multiple the second processing unit, for according to the noise the general density of power and the transmission vector power,
First matrix obtains the optimum filtering matrix, and the master of optimum filtering matrix is obtained according to the optimum filtering matrix
The non-master diagonal part of diagonal part and optimum filtering matrix, and described second is obtained by non-master diagonal part is inverted
Matrix；And multiple third processing units, for obtaining the steady rayleigh distributed matrix according to the steady rayleigh distributed
Associate matrix.
Further, in one embodiment of the invention, the preprocessing module includes: multiple fourth processing units,
For according to first matrix, the matched filtering vector and second matrix obtain parameter matrix, primary vector with
And efficient channel gain.
Further, in one embodiment of the invention, the iteration module includes: multiple 5th processing units, is used
In obtaining iteration initial value according to the parameter matrix and the primary vector, and preset according to the iteration initial value
The iterative calculation of number obtains the testing result vector.
Further, in one embodiment of the invention, the max log likelihood ratio computing module includes:
Multiple 6th processing units are obtained for will test result vector and efficient channel gain substitution linear equation
Signal is calculated, and the max log likelihood ratio is obtained according to the ratio of the calculating signal and interference plus noise.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is the structural schematic diagram of the integrating device according to an embodiment of the present invention based on signal detection algorithm；
Fig. 2 is the structural schematic diagram for wirelessly communicating multi-input multi-output system according to one embodiment of present invention；
Fig. 3 is matrix according to an embodiment of the invention and matched filtering computing module structural schematic diagram；
Fig. 4 is processing unit PE-A structural schematic diagram according to an embodiment of the invention；
Fig. 5 is processing unit PE-B structural schematic diagram according to an embodiment of the invention；
Fig. 6 is processing unit PE-C structural schematic diagram according to an embodiment of the invention；
Fig. 7 is preprocessing module structural schematic diagram according to an embodiment of the invention；
Fig. 8 is processing unit PE-D structural schematic diagram according to an embodiment of the invention；
Fig. 9 is iteration module structural schematic diagram according to an embodiment of the invention；
Figure 10 is processing unit PE-E structural schematic diagram according to an embodiment of the invention；
Figure 11 is max log likelihood ratio computing module structural schematic diagram according to an embodiment of the invention.
Figure 12 is processing unit PE-F structural schematic diagram according to an embodiment of the invention；And
Figure 13 is the structural schematic diagram of the integrating device based on signal detection algorithm accord to a specific embodiment of that present invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
The integrating device based on signal detection algorithm proposed according to embodiments of the present invention is described with reference to the accompanying drawings.Reference
Shown in Fig. 1, being somebody's turn to do the integrating device 100 based on signal detection algorithm includes: matrix and matched filtering computing module 10, pretreatment mould
Block 20, iterative calculation module 30 and max log likelihood ratio computing module 40.
Wherein, the steady rayleigh distributed channel square that matrix and matched filtering computing module 10 are used to be obtained according to signal detection
Battle array, the signal vector that base station end receives, the power spectral density of noise and transmission vector power obtain respectively the first matrix,
With filter vector and the second matrix.Specifically, matrix and matched filtering computing module 10 include: multiple first processing units,
Signal vector for being received according to steady rayleigh distributed channel matrix and base station end obtains matched filtering vector, the first square
The inverse of the elements in a main diagonal of battle array, the elements in a main diagonal of the first matrix and the first matrix；Multiple the second processing unit, are used for
Optimum filtering matrix is obtained according to the power spectral density of noise and transmission vector power, the first matrix, and according to optimum filtering
Matrix obtains the leading diagonal part of optimum filtering matrix and the non-master diagonal part of optimum filtering matrix, and will be non-master right
Angle part is inverted to obtain the second matrix；Multiple third processing units, for obtaining steady Rayleigh point according to steady rayleigh distributed
The associate matrix of cloth matrix.
Further, signal vector that signal detection obtains Stationary Distribution channel matrix, base station end receive, noise
Power density, as shown in Fig. 2, wireless communication system is made of base station, user equipment and radio communication channel.For multi input
Multiple output system, channel carries out data transmission multiple user equipmenies with base station by wireless communication simultaneously.In implementation of the invention
In example, without loss of generality, it is assumed that user device quantity M, antenna for base station number is N, therefore radio communication channel can be by N row M
The channel matrix H of column indicates.To simulate actual environment, the element in H meets flat Rayleigh fading distribution.
The communication system is to be suitable for two-way communication, is made of uplink and downlink.Downlink from base station to
User equipment sends data, and uplink sends data from user equipment to base station.The integrating device of the embodiment of the present invention is main
It is designed for the decoding in uplink with detection.Effect in order to better illustrate the present invention, below it is just specific
Introduce uplink and the extrapolation parallel iteration signal detection decoding algorithm based on iterative method.
For uplink, all user equipmenies can same time simultaneous transmission number of signals by antenna amount
M is determined.Therefore all transmitted bits (bits) are the subsets of following binary vector:
Xu=[x1 u；…；xL u],
Wherein, L=Mlog2It (B), is log for the number of signals of each user transmission2(B) bit.Specific uplink
Link realizes that step can be such that
Binary bit stream is mapped (gray mappings) into following transmission vector by S1:
Su∈OM,
Wherein, O indicates the set of constellation point.Subscript u used herein represents uplink uplink.Each user
Equipment can be used identical constellation point also and various constellations point can be used.Where it is assumed that the average energy of each symbol is Es。
S2, vector suBase station end is transmitted upstream to by wireless channel.The uplink can be modeled as such as ShiShimonoseki
It is formula:
yu=Husu+nu；
Wherein, y hereinuIndicate the vector that base station receives, nuIndicate channel additive thermal noise, HuIndicate transmission square
Battle array, contains the transmission characteristic of channel.The binary vector received may be expressed as:
yu=[y1 u；…；yN u]；
Up channel matrix HuWith additive noise nuIt can be expressed as
Hu∈CN×M, nu∈CN；
Wherein the input of H meets flat Rayleigh distribution, and the input of n meets independent identically distributed 0 mean value Gaussian Profile, and
The variance of each complex values input is N0。
For uplink, the function that base station end is realized is to pass through channel matrix HuWith the signal y receiveduCalculate or
Estimate original signal su, initial vector X is formed using decoding and demodulation.Wherein, receiving signal y can be directly by reception day
Line, and channel matrix H can be detected by known pilot signal.Minimum mean square error method in the related technology is will to believe
Road Gram matrix and additive noise sum to obtain matched filtering matrix A=(G+N0EsIN), wherein N0For noise power spectral density,
EsFor transmission vector power, it is the first matrix above-mentioned, by channel matrix and its conjugate transposition phase that G, which is channel Gram matrix,
It is multiplied to arrive.A inverse of a matrix matrix is sought again, with the y after matched filteringMFMultiplication obtains original signal, and matrix inversion is all meters
Computational complexity is maximum in calculation.The New arithmetic method of the embodiment of the present invention: extrapolation parallel iterative algorithm (EXtrapolated
Parallelizable Iteration, EXPI), the process inverted is implied, direct solution equation group yu=Husu+nuIt is close
Like solutionIt reduces computational complexity, promote calculating degree of parallelism, make it preferably to use hardware realization.
Further, matrix and matched filtering module 10 include the diagonal line base pulsation computing array of a unilateral input,
To complete to calculate: yMF=HHY, G=HHH, A=HHH+N0Es -1IMAnd P-1.H is steady rayleigh distributed channel matrix, HHIt is steady
Associate matrix, the N of rayleigh distributed channel matrix0For noise power spectral density, EsFor transmission vector power.
Wherein, matrix and matched filtering module 10 processing unit that contain three kinds different, that is, above-mentioned multiple
One processing unit, multiple the second processing unit and multiple third processing units, such as PE-A, PE-B, PE-C, referring to shown in Fig. 3.Tool
Body, the part PE-A is used to calculate matched filtering vector yMF, the elements in a main diagonal of the first matrix (Gram matrix) and its fall
Number.The part PE-B is used to calculate the MMSE filtering matrix A i.e. non-master diagonal part of optimum filtering matrix.According to Gram matrix
Property and expression formula A=G+N0Es -1IM, it is known that optimum filtering matrix is symmetrical about leading diagonal, therefore can be omitted three
The calculating of angle part is multiplexed using lower triangular portions.The part PE-C is used to calculate the conjugate complex number of data.It is clocked out, has
The calculating step of body can be such that
S1, first clock cycle.Matrix HHThe PE-A in preceding 4 elements input upper left corner of the first row, while vector y
The PE-A in preceding 4 elements input upper left corner calculates y by multiplying accumulatingMFPreceding 4 parts of first element and, calculate simultaneously
Preceding 4 parts of first element of Gram matrix leading diagonal and.
S2, second clock cycle.Upper left corner PE-A continues to input HH4 elements after the first row and y are carried out with the
The identical calculating of a cycle calculates yMFSecond 4 part of first element and, while calculating Gram matrix leading diagonal
Second 4 part of first element and.The H inputted in a cycle simultaneouslyH4 elements enter in PE-C and counted
It calculates, acquires conjugate complex number；4 elements of the y inputted in a cycle are downwardly into the second row PE-A.At this point, HHSecond row
Preceding 4 elements input the second row, by multiplying accumulating, count yMFPreceding 4 parts of second element and.
S3, third clock cycle, the first row, the second row PE-A continue identical operation, only the subscript of input data
Each cycle+4.The conjugate complex number exported simultaneously by the first row PE-C is input to downwards in first PE-B of the second row, a upper period
The H of second row inputH4 elements continue also to enter in PE-B to the right and carry out matrix multiplication operation, calculate G0,1It is i.e. non-master diagonal
Element is also used as the off diagonal element of A.The third line PE-A starts input data simultaneously, similar with the second row.
S4, and so on, i-th of clock cycle, each HHElement is transferred to PE-B by PE-A and is constantly moved to right until PE-
By asking conjugation to move down again after C；Each y element constantly moves down.The i-th row is starting after i-1 clock cycle delay simultaneously
Input data, to guarantee that the calculating input of each unit synchronizes.When to N/4-1 period, the H in the upper left cornerHIt has fully entered
At calculating after the top left hand element of matrix G plus noise parameter N0Es -1And inverted output, while yMFAlso it calculates and completes the
One element is exported, and hereafter next line of each period output is as a result, finally by the inverted rear structure of the main diagonal element of the whole of A
At matrix P, off diagonal element constitutes matrix Q, and exports the first matrix G and matched filtering vector yMF。
It should be noted that firstly, since matrix P will be used at once in the calculating of matrix R and T, therefore PE-A is placed in
Far Left calculates at first.It is counted secondly, the calculated result of PE-A is transferred to next PE in each clock cycle at once
It calculates, therefore the design can achieve high data throughput and hardware is suitble to complete.
Above-mentioned PE-A, PE-B and PE-C difference is as shown in Figure 4,5, 6.
Specifically, Fig. 4 is the structural schematic diagram of PE-A.As shown in figure 4, mainly including: arithmetic logic unit alu tires out
Add device ACC, register REG and seeks reciprocal unit RECU.The input of PE-A includes that a complex matrix and one are complex vector located,
Output is complex vector located and one group of main diagonal element of matrix (matrix is real number with conjugation matrix multiple the elements in a main diagonal)
The real number array of composition, composed structure are made of such as figure left side four mutually isostructural ALU arrays, possess 3 ALU per a piece of
Unit, the multiplication for calculated complex.Because matrix multiplication is more regular, synchronization is improved using 4 identical structures herein
Number of multiplication operations, quickening calculating speed, intermediate is two accumulators, and right upper portion is that a register is used to tire out with following
Add device and reciprocal unit is asked to synchronize output, wherein reciprocal unit is asked to be made of look-up table.
PE-A major function includes the product of calculating matrix and multiplication of vectors and matrix and the associate matrix of itself.
Calculating step can be such that input matrix H* first and vector y, and each clock cycle can input 4 groups of data.By ALU gusts
Column do multiplication, and wherein both the above ALU is used to calculate H* and be multiplied with corresponding element specific in y, and result is formed most by cumulative
Terminate fruit yMF, below ALU be used to calculate H* and be multiplied with itself conjugate transposition H, by adding up and plus additional parameter e, then
Inverse is asked to obtain final result the elements in a main diagonal of obtained matrix.
Fig. 5 is the structural schematic diagram of PE-B.As shown in figure 5, mainly including: arithmetic logic unit alu, accumulator ACC.
The input of PE-B is a complex matrix, and output is also a complex matrix, and composed structure such as figure left side is by four identical knots
The ALU array of structure forms, and possesses 2 ALU units per a piece of, and for the multiplication of calculated complex, right side is two accumulators.
PE-B major function is used to calculate the product of Gram matrix i.e. matrix and the conjugate transposition of itself.Calculating step can be with
As follows: the ranks for needing to be multiplied by matrix H first input 4 ALU arrays, and each clock cycle can input 4 groups of data, pass through
ALU array does multiplication, and result forms final result matrix G by cumulative.
Fig. 6 is the structural schematic diagram of PE-C.As shown in fig. 6, PE-C may include: to seek conjugate complex number module.It forms knot
Structure is also relatively easy, such as conjugate complex number module array can be asked to form by 4, keeps identical 4 battle arrays of PE-A, PE-B herein
Column, which make to calculate, to be synchronized.PE-C major function is used for the conjugate transposition of calculating matrix, by left side input matrix H, each clock cycle
4 groups of plural numbers can be inputted, its conjugate complex number is obtained after conjugate complex number (Conj) module, the conjugation of final composite matrix H turns
Set matrix.
Further, preprocessing module 20 according to the first matrix, matched filtering vector and the second matrix for being joined
Matrix number, primary vector and efficient channel gain.
Wherein, preprocessing module 20 includes: multiple fourth processing units such as PE-D.Multiple fourth processing units are used for basis
First matrix, matched filtering vector and the second matrix obtain parameter matrix, primary vector and efficient channel gain.
As shown in fig. 7, preprocessing module 20 can be only formed in parallel with a PE-D by M-1 PE-D series connection again, with
In completion calculating parameter matrix R=P-1Q, efficient channel gain Uii=(P-1G)ii, primary vector T=P-1yMF.The wherein leftmost side
PE-D be used to calculate vector T, right side is used to calculate R or Uii。
For example, calculating step can be such that
S1, the corresponding y of the i-th periodical inputi MF、Pi -1, Q the i-th row.
S2, T at this time is calculated in leftmost side PE-Di, right side is by each element of the i-th row of Q simultaneously multiplied by Pi -1, obtain R's
I-th row calculates R, T by M period.Herein because element is all real number in P, calculate relatively simple.
S3, it needs to calculate UiiWhen, corresponding matrix G element, which is inputted right side PE-D, to be calculated.
Due to calculating of can synchronizing of each clock cycle PE-D as a result, therefore the degree of parallelism of this structure is very
It is high.
Fig. 8 is the structural schematic diagram of PE-D.As shown in figure 8, PE-D specifically includes that arithmetic logic unit alu, real number-are multiple
Number converting unit COMP.The one of input of PE-D is real vector P-1, another input can be complex vector located yMF, can also
To be complex matrix G, output is a complex matrix or one group of matrix the elements in a main diagonal, and composed structure such as figure left side is by two
A ALU composition, for the multiplication of calculated complex, right side is a real-complex converter, for turning the real number being calculated
It is changed to plural number, to preferably be calculated with other complex matrixs.PE-D major function includes calculating vector and vector/matrix
Product, calculate steps are as follows: a corresponding element is multiplied in each clock cycle input vector or matrix, respectively
Real and imaginary parts are obtained, then is inputted complex conversion device and obtains final result.
Further, iteration module 30 is used to be iterated calculating by parameter matrix, primary vector, to obtain detection knot
Fruit vector.
Wherein, iteration module 30 includes: multiple 5th processing unit such as PE-E, for according to parameter matrix and primary vector
Iteration initial value is obtained, and testing result vector is obtained according to ginseng according to the iterative calculation that iteration initial value carries out preset times
Matrix number and primary vector are iterated calculating, to obtain testing result vector；
As shown in figure 9, iteration module 30 is connected in series by M PE-E unit.This module is for calculating iteration initial valueAnd complete final iterative calculation:The calculating of iteration module 30 can be divided into two ranks
Section, the input in each stage are also not quite similar, therefore are embedded in register file in PE-E module and are used to change input, calculate step
Suddenly it can be such that
S1, in the first phase in order to calculate iteration initial value1st period is by first, left side PE-E input element
TiAnd the operation of multiplication after first subtraction is completed with the R matrix element inputted simultaneously.
S2, each cycle T vector element later move right and the R element of i-th of PE-E i-1 period of delay is defeated
Enter, completes subtraction and add up with after multiplying with the result retained before, untilIt calculates and completes.
S3, into second stage, the i-th period will input TiVector element is changed to initial vector elementIt changes simultaneously
The input of each PE-E configures, and each element of vector moves right according to the clock cycle, calculates first time iteration
S4, repeat the 3) step iterated to calculate out until by k times
On the basis of ensure that the execution cycle to match with above-mentioned each module, processing unit can be accordingly reduced
Quantity reduces chip area and power consumption while keeping high data throughput, takes full advantage of the concurrency of calculating.
Figure 10 is the structural schematic diagram of PE-E.As shown in Figure 10, mainly include: arithmetic logic unit alu, accumulator
ACC, real-complex converting unit COMP.The input of PE-E can be matrix and be also possible to vector, and during calculating
It can change, not repeat specifically herein.
PE-E major function includes the product for being also calculating vector and vector/matrix.Calculate the meter of step and above-mentioned PE-D
It is similar to calculate step, two accumulators are only increased between ALU and COMP unit, in this not go into detail.
Further, max log likelihood ratio computing module 40 is obtained by testing result vector and efficient channel gain
Max log likelihood ratio.Wherein, max log likelihood ratio computing module 40 includes: multiple 6th processing unit such as PE-F, is used for
Be calculated calculating signal according to linear equation, and obtained according to the ratio for calculating signal and interference plus noise it is maximum right
Number likelihood ratio.
As shown in figure 11, max log likelihood ratio computing module 40 can be made of three PE-F units.When base station end will
After the signal detection that user device transmissions come comes out, mapping, such as Gray were carried out due to signal and on a user device
Code mapping, therefore also need to carry out one-step decoding, this operation just calculates 40 pieces of mould completions by max log likelihood ratio, specific to count
Calculating step can be such that
S1, linear equation is calculatedFor each PE-F, input
And Uii, and ask reciprocal using look-up table, then do multiplication subtraction and division.Wherein, step S1 corresponding LUT, ALU all in PE-F
Middle completion.
S2, it multiplication is done according to the ratio (SINR) for calculating signal and interference plus noise obtains final Li,b。
It should be noted that each step is calculated hereinIt is all saved in a lookup table, while U hereii
It is also from the pretreatment link transmission of front.
Figure 12 is the structural schematic diagram of PE-F.As shown in figure 12, mainly include: arithmetic logic unit alu, look-up table
LUT and seek reciprocal unit RECU.The input of PE-F is two groups of complex vector located or matrixes, and output is one group of plural number array, composition
Structure such as figure left side by look-up table and asks reciprocal unit to constitute, and left side is in series by two parallel connection ALU and an ALU.PE-F
Major function is for calculating last max log likelihood ratio.
Four circuit modules as above are connected according to its input and output, final circuit, overall structure can be obtained
Schematic diagram is as shown in Figure 1, finally realize the signal detection of uplink in extensive multiple input, multiple output wireless communication system
With decoding EXPI algorithm.The design of circuit modules is based on pipeline organization, takes full advantage of data parallelism calculating, realizes
The detection decoding of high-speed low-power-consumption.
The integrating device 100 of the embodiment of the present invention is by four electricity as described above in one particular embodiment of the present invention
Road module is connected according to its input and output, and final circuit can be obtained, finally realize extensive multiple-input and multiple-output without
The signal detection of uplink and decoding EXPI algorithm in line communication system.The design of circuit modules is based on flowing water knot
Structure takes full advantage of data parallelism calculating, realizes the detection decoding of high-speed low-power-consumption.It is final by the calculating of disparate modules
It can be realized the detection decoding of high-speed low-consumption.
Specifically, the integrating device 100 of the embodiment of the present invention is for realizing base in wireless communication multi-input multi-output system
It stands the signal detection and decoding at end, is basic modularized design with new signal detection decoding algorithm.The algorithm is based on repeatedly
For the extrapolation parallel iterative algorithm (Extrapolated Parallelizable Iteration, EXPI) of method, it is mainly used for
Solve the approximate solution of system of linear equations y=Hs+nWherein, known to H, y, n.H be N × Metzler matrix, s be the vector of M × 1, y, n be for
The vector of N × 1.
Further, as shown in figure 13, the function that module 1 is realized: Gram matrix and matched filtering vector y are calculatedMF.Its
In, input signal: steady rayleigh distributed channel matrix H, the signal vector y that base station end receives, the power spectral density N of noise0,
Transmission vector power Es；Output signal: matrix G, P-1, vector yMF.The function that module 2 is realized: the pretreatment being iterated calculates
Parameter matrix R and vector T.Wherein, input signal: matrix G, P-1, vector yMF；Output signal: matrix R, vector T, efficient channel
Gain Uii.The function that module 3 is realized: it calculates iteration initial matrix and is iterated calculating.Wherein, input signal: matrix R, to
Measure T, parameter ω；Output signal: testing result vectorThe function that module 4 is realized: LLRs is calculated.Wherein, input signal: detection
Result vectorEfficient channel gain Uii；Output signal: LLRs numerical value.
Integrating device according to an embodiment of the present invention based on signal detection algorithm, firstly, signal detection is obtained flat
Steady rayleigh distributed channel matrix, base station end received signal vector, the power spectral density of noise and transmission vector power obtain the
One matrix, matched filtering vector and the second matrix, secondly, according to the first matrix of acquisition, matched filtering vector and second
Matrix obtains parameter matrix, primary vector and efficient channel gain by preprocessing module, further according to parameter matrix, first to
Amount is iterated to obtain testing result vector, finally, obtaining max log likelihood by testing result and efficient channel gain
Than the signal detection algorithm EXPI based on newest proposition, low with computation complexity, the bit error rate is low, and it is high to calculate degree of parallelism
Advantage is very suitable for hardware realization, while relative to small-scale multiple-input and multiple-output or biography used in current mainstream base station
Single signal of uniting communicates decoding circuit, the ultra-large specific integrated circuit knot based on the design of extensive multi-input multi-output system
Structure data throughout is big, and speed is fast, low in energy consumption.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or
Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must
There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect
It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary
The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art
For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with
It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists
Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of
First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below "
One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (4)
1. a kind of integrating device based on signal detection algorithm characterized by comprising
Matrix and matched filtering computing module, steady rayleigh distributed channel matrix, base station end for being obtained according to signal detection
The power spectral density and transmission vector power of the signal vector, noise that receive obtain the first matrix, matched filtering vector with
And second matrix, the matrix include: with matched filtering computing module
Multiple first processing units, the signal for being received according to the steady rayleigh distributed channel matrix and the base station end
Vector obtains the elements in a main diagonal and first square of the matched filtering vector, first matrix, first matrix
The inverse of the elements in a main diagonal of battle array；
Multiple the second processing unit, for the general density of power and the transmission vector power, described first according to the noise
Matrix obtains optimum filtering matrix, and according to the optimum filtering matrix obtain optimum filtering matrix leading diagonal part and
The non-master diagonal part of optimum filtering matrix, and second matrix is obtained by non-master diagonal part is inverted；And
Multiple third processing units, the conjugation for obtaining the steady rayleigh distributed channel matrix according to steady rayleigh distributed turn
Set matrix；
Preprocessing module, for being pre-processed to first matrix, the matched filtering vector and second matrix,
To obtain parameter matrix, primary vector and efficient channel gain；
Iteration module, for being iterated calculating by the parameter matrix, the primary vector, with obtain testing result to
Amount；And
Max log likelihood ratio computing module obtains max log by the testing result vector and the efficient channel gain
Likelihood ratio.
2. as described in claim 1 based on the integrating device of signal detection algorithm, which is characterized in that the preprocessing module packet
It includes:
Multiple fourth processing units, for being obtained according to first matrix, the matched filtering vector and second matrix
To parameter matrix, primary vector and efficient channel gain.
3. as described in claim 1 based on the integrating device of signal detection algorithm, which is characterized in that the iteration module packet
It includes:
Multiple 5th processing units, for obtaining iteration initial value, and root according to the parameter matrix and the primary vector
The testing result vector is obtained according to the iterative calculation that the iteration initial value carries out preset times.
4. as described in claim 1 based on the integrating device of signal detection algorithm, which is characterized in that the max log likelihood
Include: than computing module
Multiple 6th processing units are calculated for will test result vector and efficient channel gain substitution linear equation
Signal, and the max log likelihood ratio is obtained according to the ratio of the calculating signal and interference plus noise, wherein the line
Property equation are as follows:
Wherein,For testing result vector, UiiFor the efficient channel gain.
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| US15/331,875 US9729277B2 (en) | 2015-12-14 | 2016-10-23 | Signal detecting method and device |
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| CN107733487B (en) * | 2017-10-11 | 2020-06-19 | 北京科技大学 | Signal detection method and device for large-scale multi-input multi-output system |
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