CN105529360A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN105529360A CN105529360A CN201410522582.XA CN201410522582A CN105529360A CN 105529360 A CN105529360 A CN 105529360A CN 201410522582 A CN201410522582 A CN 201410522582A CN 105529360 A CN105529360 A CN 105529360A
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Abstract
The invention discloses a semiconductor device and a forming method thereof. The forming method of the semiconductor device comprises the steps of: providing a silicon-on-insulator, which sequentially comprises a substrate, an insulating layer and a top silicon layer; forming a gate structure on the top silicon layer; forming side walls on two sides of the gate structure; forming a semiconductor layer on the top silicon layer on both sides of the side walls; implanting ions into the semiconductor layer and the top silicon layer under the semiconductor layer until a heavily-doped region is formed; removing the side walls to expose the top silicon layer under the side walls after ion implantation; performing lightly-doped ion implantation process on the exposed top silicon layer and at least a partial thickness of the semiconductor layer; and carrying out annealing process after the lightly-doped ion implantation process. The semiconductor device formed by adopting the forming method has improved performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of semiconductor device and forming method thereof.
Background technology
Along with the development of semiconductor technology, the integrated level of integrated circuit is more and more higher, and the characteristic size (CD) of device is more and more less.When the feature size downsizing of device is to deep-submicron (0.25 micron hereinafter referred to as deep-submicron), the leakage current of device increases, drain-induced barrier reduces (Draininductionbarrierlower, DIBL) effect and short-channel effect (SCE) etc. are more and more obvious, the subject matter that the needs becoming device dimensions shrink overcome.
There is the FDSOI (FullyDepletedSiliconOnInsulator of the raceway groove that undopes, fully-depleted silicon-on-insulator) semiconductor device (hereinafter referred to as FD device) of structure can overcome the various problems that device dimensions shrink is brought, its concrete advantage is: 1) owing to having for ultra-shallow junctions, therefore FD device can suppress leakage current, control SCE effect; 2) eliminate the random fluctuation of doping because raceway groove undopes, therefore the mutability of FD device is very low; 3) due to FD device buried oxide layer and body substrate completely isolated, therefore the error rate of FD device is very low; 4) because the source/drain of FD device normally docks thick insulator (buried oxide layer in such as FDSOI), therefore the junction capacitance of FD device is very low.
Multiple FD device architecture has been developed in prior art, as FinFET (FinField-effecttransistor, fin field-effect transistor), 3 grid structures, nano wire and ETSOI (ExtremelyThinSiliconOnInsulator, silicon on ultrathin insulating body).
Although often kind of device architecture has himself special benefits and challenge, ETSOI is noticeable especially because of its planar structure, it make ETSOI and main flow planar CMOS manufacture process completely compatible.Be different with fin number quantized FinFET from device widths, ETSOI can have the width required arbitrarily.In addition, ETSOI exhausts completely, does not have floater effect.As a result, in fact ETSOI circuit can be similar to conventional body silicon circuit and design like that, therefore can realize the seamless design migration from bulk silicon technology to ETSOI.Finally, when adopting ultra-thin buried oxide layer (UTBOX) together with ETSOI, additional device adjustment and power management can with adding dopant and/or the realization of substrate place reverse bias.
But the performance of semiconductor device that silicon is formed existing ultrathin insulating body is not good.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device and forming method thereof, to improve the performance of semiconductor device.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising:
There is provided silicon-on-insulator, described silicon-on-insulator comprises substrate, insulating barrier and top silicon layer successively;
Described top silicon layer forms grid structure;
Side wall is formed in described grid structure both sides;
The top silicon layer of described side wall both sides forms semiconductor layer;
Ion is injected, until form heavily doped region to the top silicon layer below described semiconductor layer and described semiconductor layer;
After ion implantation, described side wall is removed to expose the top silicon layer below described side wall;
Light dope ion implantation technology is carried out to the top silicon layer of described exposure and the described semiconductor layer of at least part of thickness;
After described light dope ion implantation technology, carry out annealing process.
Optionally, the annealing region of described annealing process is 400 DEG C ~ 800 DEG C, and annealing time scope is 10min ~ 180min.
Optionally, the ion that described light dope ion implantation technology is injected be phosphonium ion and arsenic ion at least one of them, the doping content scope of described ion is 1E14atom/cm
2~ 1E16atom/cm
2, the Implantation Energy scope of described ion is 100eV ~ 5KeV.
Optionally, the ion that described light dope ion implantation technology is injected be boron ion and indium ion at least one of them, the doping content scope of described ion is 1E14atom/cm
2~ 1E16atom/cm
2, the Implantation Energy scope of described ion is 100eV ~ 5KeV.
Optionally, epitaxial growth method is adopted to form described semiconductor layer on the silicon layer of described top.
Optionally, after the described side wall of removal, metalized is carried out to the described semiconductor layer of the top silicon layer exposed and at least part of thickness, until form metal silicide layer.
Optionally, the described metal silicide layer thickness be formed in described semiconductor layer is more than or equal to the described metal silicide thickness be formed in the silicon layer of described top, and the thickness being formed in the described metal silicide layer in the silicon layer of described top is more than or equal to described top silicon layer thickness.
Optionally, the thickness range of described semiconductor layer is
Optionally, the thickness range of described top silicon layer is
Optionally, the thickness range of described side wall is
Optionally, after described top silicon layer forms grid structure, and before described grid structure both sides form described side wall, be also included in the step that described grid structure both sides form biased side wall; Described light dope ion implantation technology with described biased side wall and described grid structure for mask; Segregation light doping section is formed in the described top silicon layer that described annealing process exposes after making removal side wall.
For solving the problem, present invention also offers a kind of semiconductor device, comprising:
Silicon-on-insulator, described silicon-on-insulator comprises substrate, insulating barrier and top silicon layer successively;
Be positioned at the grid structure on the silicon layer of described top;
Also comprise:
Be positioned at the semiconductor layer on the silicon layer of top, described grid structure both sides, between described semiconductor layer and described grid structure, there is gap;
Be arranged in the heavily doped region of the top silicon layer below described semiconductor layer and described semiconductor layer;
The top silicon layer be arranged in below described gap is neutralized to the light doping section of semiconductor layer described in small part.
Optionally, the thickness range of described semiconductor layer is
Optionally, the thickness range of described top silicon layer is
Optionally, the width range in described gap is
Optionally, the metal silicide layer that the top silicon layer be arranged in below described gap is neutralized to semiconductor layer described in small part is also comprised.
Optionally, described grid structure both sides also have biased side wall, also have segregation light doping section in the top silicon layer below described gap.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, the top silicon layer of first silicon on insulator forms grid structure, then light dope ion implantation technology is not carried out, but form side wall in described grid structure both sides, and semiconductor layer is formed on the top silicon layer of described side wall both sides, backward described semiconductor layer and described semiconductor layer below top silicon layer inject ion, until formation heavily doped region, after ion implantation, remove described side wall to expose the top silicon layer below described side wall, now, again light dope ion implantation technology is carried out to the top silicon layer of described exposure and the described semiconductor layer of at least part of thickness, and carry out annealing process, thus formation semiconductor device.After the formation process of heavily doped region and light dope ion implantation technology are comparatively adjusted to and are formed semiconductor layer by described formation method, therefore, the top silicon layer of crystal structure can be prevented to be amorphous before formation semiconductor layer, thus ensure that semiconductor layer is formed smoothly, thus improve the performance of final formed semiconductor device.
Further, the thickness range of side wall is
top silicon layer immediately below side wall is follow-up for the formation of light doping section, and the top silicon layer of side wall both sides is follow-up for the formation of heavily doped region, and therefore, the heavily doped region of the follow-up formation of thickness effect of side wall, to the distance of channel region, affects the width range of light doping section simultaneously.Visible, the thickness of side wall is an important size factor.If the thickness range of side wall is greater than
then heavily doped region is too large to the distance of channel region, has a negative impact to the performance of semiconductor device.If the thickness range of side wall is less than
then the width of light doping section is too little, has a negative impact equally to the performance of semiconductor device.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is structural representation corresponding to each step of formation method of existing semiconductor device;
The structural representation that each step of formation method of the semiconductor device that Fig. 4 to Figure 13 provides for the embodiment of the present invention is corresponding.
Embodiment
As described in background, performance of semiconductor device silicon formed existing ultrathin insulating body is not good.Ultrathin insulating body silicon is formed the existing method of semiconductor device as shown in Figure 1 to Figure 3.
Please refer to Fig. 1, the silicon-on-insulator comprising substrate (not shown), insulating barrier (not shown) and top silicon layer 100 is provided, and grid structure (mark) is formed on the silicon layer 100 of top, described grid structure generally includes gate dielectric layer (mark) and grid (mark).Described grid structure top can also have mask layer (mark).The side of described grid structure and the side of described mask layer are biased side wall 120 and cover.And be arranged in the top silicon layer 100 of described grid structure both sides, usually after the biased side wall 120 of formation, light dope ion implantation technology (LDD, that is lightly doped drain injection technology) can be carried out, thus form light doping section 110.
Please refer to Fig. 2, the top silicon layer 100 of biased side wall 120 both sides forms semiconductor layer 130, and semiconductor layer 130 is formed in above light doping section 110.
Please refer to Fig. 3, side wall 140 is formed in the side of the side of described grid structure and described mask layer, side wall 140 covers biased side wall 120, and Semiconductor substrate 130 shown in the Fig. 2 of cover part, then with side wall 140 for mask, ion implantation is carried out to the Semiconductor substrate 130 do not covered by side wall 140, forms heavily doped region 130a.
But, in above-mentioned existing method, when forming semiconductor layer 130 in fig. 2, encounter difficulty.Originally, usual semiconductor layer 130 needs to adopt epitaxial growth method to be formed, but, before Semiconductor substrate 130 is formed, first carry out light dope ion implantation technology and form light doping section 110, and light dope ion implantation technology can make the silicon crystal in doped region 110 be amorphous (amorphized), and amorphous silicon surfaces substantially cannot the single crystalline layer (i.e. semiconductor layer 130) of epitaxially grown silicon.
For this reason, the invention provides a kind of formation method of new semiconductor device, the top silicon layer of described formation method silicon on insulator forms grid structure, do not carry out light dope ion implantation technology, but form side wall in described grid structure both sides, and semiconductor layer is formed on the top silicon layer of described side wall both sides, backward described semiconductor layer and described semiconductor layer below top silicon layer inject ion, until formation heavily doped region, after ion implantation, remove described side wall to expose the top silicon layer below described side wall, now, again light dope ion implantation technology is carried out to the top silicon layer of described exposure and the described semiconductor layer of at least part of thickness, and carry out annealing process, thus formation semiconductor device.After the formation process of heavily doped region and light dope ion implantation technology are comparatively adjusted to and are formed semiconductor layer by described formation method, therefore, the top silicon layer of crystal structure can be prevented to be amorphous before formation semiconductor layer, thus ensure that semiconductor layer is formed smoothly, thus improve the performance of final formed semiconductor device.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The embodiment of the present invention provides a kind of formation method of semiconductor device, incorporated by reference to reference to figure 4 to Figure 13.
Please refer to Fig. 4, provide silicon-on-insulator (SOI does not mark), described silicon-on-insulator comprises substrate 201, insulating barrier 202 and top silicon layer 203 successively.
In the present embodiment, substrate 201 can be the Semiconductor substrate of any materials, such as polysilicon or polycrystalline germanium Semiconductor substrate.The material of insulating barrier 202 can be silica.The material of top silicon layer 203 can be monocrystalline silicon.
In the present embodiment, in the silicon layer 203 of top, isolation structure can also be comprised, such as fleet plough groove isolation structure (STI, not shown).
In the present embodiment, the thickness range of top silicon layer 203 can be
because top silicon layer 203 is positioned at semiconductor material layer unique below the grid structure of follow-up formation, if the thickness of top silicon layer 203 is less than
then follow-up corresponding channel region thickness is too little, and if the thickness of top silicon layer 203 is greater than
then ultra-thin silicon-on-insulator can not be formed.
Control for making the thickness range of top silicon layer 203
the present embodiment can first provide common silicon on insulated substrate, and this silicon on insulated substrate has the larger top layer silicon of thickness, and the thickness range of such as top layer silicon can be 30nm ~ 80nm (being specifically as follows 30nm, 50nm or 80nm).Then can thinning top layer silicon with obtain push up silicon layer 203, thus make the silicon on insulated substrate shown in Fig. 4 (comprise substrate 201, insulating barrier 202 and top silicon layer 203) become ultra-thin silicon-on-insulator.
Please continue to refer to Fig. 4, top silicon layer 203 forms grid structure, and described grid structure comprises gate dielectric layer 211 and grid 212.
In the present embodiment, the material of gate dielectric layer 211 can be silica, and the material of grid 212 can be polysilicon.
It should be noted that, in other embodiments of the invention, in subsequent process steps, the grid of polycrystalline silicon material can be removed, and form metal gates.Now, the material of gate dielectric layer can be high-K dielectric layer, namely can be the grid structure forming high-K dielectric layer-metal gate (HKMG).
Please refer to Fig. 5, at end face and the both sides formation first medium layer 221 of grid structure, and first medium layer 221 covers top silicon layer 203 upper surface simultaneously.Then second dielectric layer 222 is formed in first medium layer 221 side of grid structure both sides.
In the present embodiment, the material of first medium layer 221 can be silica, and the thickness of first medium layer 221 can be
the material of second dielectric layer 222 can be silicon nitride, and the thickness of second dielectric layer 222 can be
Please refer to Fig. 6, form the 3rd dielectric layer 223 and cover second dielectric layer 222 and first medium layer 221.
In the present embodiment, the material of the 3rd dielectric layer 223 can be silica, and the thickness of the 3rd dielectric layer 223 can be
Please refer to Fig. 7, return etching to remove and to be positioned at first medium layer 221 on the silicon layer 203 of top and the 3rd dielectric layer 223 shown in Fig. 6, to form side wall 223a and biased side wall (mark) in grid structure both sides, wherein biased side wall comprises second dielectric layer 222 and after returning etching, remaining first medium layer 221a, side wall 223a be back to etch rear remaining 3rd dielectric layer 223.
In the present embodiment, the thickness range of side wall 223a can be
top silicon layer 203 immediately below side wall 223a is follow-up for the formation of light doping section (please refer to Figure 12), and the top silicon layer 203 of side wall 223a both sides is follow-up for the formation of heavily doped region (please refer to Fig. 9), therefore, the heavily doped region of the follow-up formation of thickness effect of side wall 223a, to the distance of channel region, affects the width range of light doping section simultaneously.Visible, in the present embodiment, the thickness of side wall is an important size factor.If the thickness range of side wall is greater than
then heavily doped region is too large to the distance of channel region, has a negative impact to the performance of semiconductor device.If the thickness range of side wall is less than
then the width of light doping section is too little, has a negative impact equally to the performance of semiconductor device.
Please refer to Fig. 8, the top silicon layer 203 of side wall 223a both sides is formed (raised) semiconductor layer 230 raised.
In the present embodiment, forming semiconductor layer 230 is formation requirements in order to meet subsequent metal silicide layer (please refer to Figure 11), if only have top silicon layer 203, because top silicon layer 203 thickness is too little, then follow-uply cannot form metal silicide layer.For this reason, in the present embodiment, the thickness range of semiconductor layer 230 is
if the thickness of semiconductor layer 230 is less than
then be unfavorable for the formation of subsequent metal silicide layer (please refer to Figure 11).If the thickness of semiconductor layer 230 is greater than
not only cause materials and process waste of time, and the heavily doped region of follow-up formation (please refer to Fig. 9) can be caused too large with the distance of channel region, reduce the performance of semiconductor device.
In the present embodiment, epitaxial growth method can be adopted on the silicon layer 203 of top to form semiconductor layer 230.Epitaxial growth method can grow the identical single-crystal semiconductor layer in crystal orientation on the silicon layer 203 of top, thus improves the performance of semiconductor device.Vapor phase epitaxy method can be adopted to form semiconductor layer 230, and detailed process is well known to those skilled in the art, and does not repeat them here.
Please refer to Fig. 9, ion (that is ion implantation is injected to the top silicon layer 203 below semiconductor layer 230 and semiconductor layer 230, ionimplantation), until form heavily doped region 240, the top silicon layer 203 not forming heavily doped region is positioned at below described grid structure, described biased side wall and side wall 223a.
In the present embodiment, the semiconductor device formed can for PMOS transistor, and now, carrying out the foreign ion that (source and drain) ion implantation technology injects can be boron ion or indium ion.
In other embodiments of the invention, the semiconductor device formed can be also nmos pass transistor, and when carrying out described ion implantation technology, the foreign ion injected can be phosphonium ion or arsenic ion.
Please refer to Figure 10, after described ion implantation, remove side wall 223a shown in Fig. 9 to expose the top silicon layer 203 below side wall 223a.
In the present embodiment, can adopt dry etch process, detailed process is well known to those skilled in the art, and does not repeat them here.
Please refer to Figure 11, metalized is carried out to the described semiconductor layer 230 of the top silicon layer 203 exposed and at least part of thickness, until form NiSi phase nickel silicide layer 250 (i.e. metal silicide).
In the present embodiment, the top silicon layer 203 that NiSi phase nickel silicide layer 250 exposes after being positioned at and removing side wall 223a and top, heavily doped region 240.Described metalized can be carried out the top of grid 212 simultaneously, and namely NiSi phase nickel silicide layer 250 is formed in the top of grid 212 simultaneously.
In the present embodiment, described metalized is specifically as follows: the top silicon layer 203 exposed after semiconductor layer 230, grid 212 and removal side wall 223a forms metal level (not shown), and the material of described metal level can be nickel; Then spike annealing (spikeanneal thus form NiSi phase nickel silicide layer 250.
In the present embodiment, NiSi phase nickel silicide layer 250 thickness be formed in semiconductor layer 230 can be more than or equal to the thickness of the NiSi phase nickel silicide layer 250 be formed in the silicon layer 203 of top, and the thickness being formed in the NiSi phase nickel silicide layer 250 in the silicon layer 203 of top can be more than or equal to top silicon layer 203 thickness.Further, the metal silicide layer 250 be formed in the silicon layer 203 of top is generally equal to top silicon layer 203 thickness.
Please refer to Figure 12, the top silicon layer 203 exposed after removing the 223a of side wall shown in Fig. 9 and the semiconductor layer 230 of at least part of thickness carry out light dope ion implantation technology, form light doping section 260.In the present embodiment, region, light doping section 260 shown in Figure 12 overlaps substantially with the phase of NiSi shown in Figure 11 nickel silicide layer 250 region.
In the present embodiment, shown in removal Fig. 9 after side wall 223a, in biased side wall, the side of second dielectric layer 222 is exposed, described light dope ion implantation technology with described biased side wall and described grid structure for mask and carrying out.When with described biased side wall and described grid structure for mask time, after can preventing the subsequent anneal formed on the one hand, light doping section 260 too extends to channel region central authorities, thus prevent short-channel effect, after ensureing subsequent anneal on the other hand, light doping section 260 extends to the enough near distance in edge, channel region, thus reduces dead resistance.
In the present embodiment, the semiconductor device formed can for PMOS transistor, now, the ion that light dope ion implantation technology is injected be boron ion and indium ion at least one of them, the doping content scope of ion can be 1E14atom/cm
2~ 1E16atom/cm
2, the Implantation Energy scope of ion can be 100eV ~ 5KeV.By the Implantation Energy of controlled doping concentration and ion, ensure in light doping section 260, dead resistance is reduced to ideal level, and make light doping section in subsequent annealing process, there is doping segregation (dopingsegregation), thus make light doping section 260 extend to channel region edges at two ends, that is: the foreign ion making lightly doped drain injection technology inject is positioned at the position being close to edge, channel region, thus provide impurity concentration gradient for source-drain area, reduce the electric field between knot and channel region, maximum field position in knot is separated with the maximum current path in raceway groove, and then can hot carrier be prevented.
It should be noted that, in other embodiments of the invention, the semiconductor device formed also can for nmos pass transistor, the ion that now described light dope ion implantation technology is injected can be phosphonium ion and arsenic ion at least one of them, the doping content scope of ion can be 1E14atom/cm
2~ 1E16atom/cm
2, the Implantation Energy scope of ion can be 100eV ~ 5KeV.
Please refer to Figure 13, after light dope ion implantation technology, carry out annealing process (annealing also can treat as one of them step of light dope ion implantation technology).
In the present embodiment, as shown in figure 13, in annealing process, the ion injected in light dope ion implantation technology has carried out doping segregation, thus define segregation light doping section 261 (segregation light doping section 261 belongs to a part for the rear light doping section 260 of annealing), and the present embodiment selecting according to above-mentioned each process conditions, the width W scope that can control segregation light doping section 261 is
thus make light doping section 260 be close to edge, channel region (channel region is formed in the top silicon layer 203 below grid structure described in Figure 13).
Spike annealing or millisecond laser annealing can be adopted in the present embodiment, a step annealing can be adopted, also can adopt multiple step anneal.The temperature range of described annealing in process can be 400 DEG C ~ 800 DEG C, as: 400 DEG C, 500 DEG C, 600 DEG C, 700 DEG C or 800 DEG C.If annealing temperature is lower than 400 DEG C, in annealing process, the ion injected in light dope ion implantation technology can not carry out enough doping segregations, if annealing temperature is higher than 800 DEG C, then can cause adverse effect to other structure of semiconductor device.
In the present embodiment, annealing time scope is 10min ~ 180min.The selection of annealing time and the selection of above-mentioned annealing temperature have similar reason.If annealing time is too short, the ion injected in light dope ion implantation technology can not carry out enough doping segregations, and if annealing time is oversize, the ion of doping segregation is too many, causes ion diffuse to channel region central authorities, causes short-channel effect.
In the present embodiment, by carrying out annealing process after light dope ion implantation technology, NiSi phase nickel silicide layer 250 is made to form extension type NiSi
2phase nickel silicide (mark), extension type NiSi
2phase nickel silicide (extension type NiSi
2phase nickel silicide region and region, light doping section 260 basically identical).
From foregoing description, extension type NiSi
2phase nickel silicide is the metal silicide that the present embodiment is finally formed.Extension type NiSi
2phase nickel silicide and silicon single crystal have substantially identical (111) crystal face, therefore, and extension type NiSi
2phase nickel silicide can be formed along (111) crystal face, therefore shows extension type NiSi in Figure 12
2phase nickel silicide region is an inclined plane, and this inclined plane is (111) crystal face.And because nickel silicon suicide is extension type, therefore, when carrying out annealing process, in nickel silicon suicide, nickel metal diffusion weakens, therefore in annealing process, the ion generation segregation of only injecting, and the metal in nickel silicon suicide does not spread substantially.
In existing method, usual nickel silicide is NiSi phase, although the self-resistance of NiSi phase nickel silicide is lower.But, when the thickness pushing up silicon layer reduces (being such as decreased to about 30nm or 10nm), extension type NiSi
2phase nickel silicide and source/drain region and channel region have minimum contact resistance, and extension type NiSi
2phase nickel silicide can also prevent diffusion.The present embodiment, by above-mentioned annealing process, forms extension type NiSi
2, thus improve the performance of the final semiconductor device formed.
The present embodiment is after removal side wall, first metalized is carried out to the semiconductor layer 230 of the top silicon layer 203 exposed and at least part of thickness, until form NiSi phase nickel silicide layer 250, and then carry out light dope ion implantation technology, finally anneal, make NiSi phase nickel silicide layer 250 form extension type NiSi
2phase nickel silicide.It should be noted that, in other embodiments of the invention, also first light dope ion implantation technology can be carried out to the semiconductor layer of the top silicon layer exposed and at least part of thickness, carry out metalized to the semiconductor layer of the top silicon layer exposed and at least part of thickness again, the present invention is not construed as limiting this.
In the formation method of the semiconductor device that this enforcement provides, after top silicon layer 203 forms grid structure, different from existing method, biased side wall and side wall 223a is formed in described grid structure both sides, and first on the top silicon layer 203 of side wall 223a both sides, form semiconductor layer 230, then (source and drain) ion implantation technology is carried out to the top silicon layer 203 of semiconductor layer 230 and below thereof, form heavily doped region 240, remove side wall 223a afterwards to expose the top silicon layer 203 covered by side wall 223a, the top silicon layer 203 exposed after finally just removing semiconductor layer 230 and side wall 223a carries out light dope ion implantation technology, form light doping section 260.Described formation method, before not carrying out ion implantation technology (comprising source and drain ion implantation technology and light dope ion implantation technology) to top silicon layer 203, just first forms semiconductor layer 230 on the silicon layer 203 of top.When forming semiconductor layer 230, top silicon layer 203 does not also carry out ion implantation technology, namely push up silicon layer 203 internal crystal structure not to be amorphous, epitaxial growth method therefore can be adopted successfully to form required semiconductor layer 230, and then improve the performance of the final semiconductor device formed.
The embodiment of the present invention additionally provides a kind of semiconductor device, and the formation method that described semiconductor device can adopt previous embodiment to provide is formed, and therefore the structures and characteristics of described semiconductor device can in conjunction with reference previous embodiment corresponding contents.
Concrete, please refer to Figure 13, described semiconductor device comprises described silicon-on-insulator (mark), and described silicon-on-insulator comprises substrate 201, insulating barrier 202 and top silicon layer 203 successively.Described semiconductor device also comprises the grid structure be positioned on the silicon layer 203 of top, described grid structure comprises gate dielectric layer 211 and grid 212, described grid structure both sides also have biased side wall, and described biased side wall comprises first medium layer 211a and second dielectric layer 222.Described semiconductor device also comprises the semiconductor layer 230 (please refer to Fig. 8) be positioned on the silicon layer 203 of top, described grid structure both sides, (gap does not mark to have gap between described semiconductor layer 230 and described grid structure, produce after described gap side wall 223a as shown in Figure 9 removes), be arranged in the heavily doped region 240 of the top silicon layer below semiconductor layer 230 and semiconductor layer 230, the top silicon layer 203 be arranged in below described gap is neutralized to the light doping section 260 of small part semiconductor layer 230, and light doping section 260 comprises segregation light doping section 261.Described semiconductor device also comprises the metal silicide layer 250 (please refer to Figure 11) that the top silicon layer 203 be arranged in below described gap is neutralized to small part semiconductor layer 230, and metal silicide layer 250 region and light dope are mixed and do not comprised region, segregation light doping section 261 in district 260 and substantially overlap.
In the present embodiment, the thickness range of top silicon layer 203 can be
the thickness range of semiconductor layer 230 can be
the width range (i.e. the thickness range of the 223a of side wall shown in Fig. 9) in described gap can be
the width W scope of segregation light doping section 261 is
the selection reason of concrete each physical dimension can with reference to previous embodiment corresponding contents.
In the semiconductor device that the present embodiment provides, light doping section 260 is arranged between heavily doped region 240 and channel region (channel region is positioned at the top silicon layer below grid structure), and light doping section 260 has the segregation light doping section 261 being close to edge, channel region, therefore, the dead resistance of whole semiconductor device is little, and performance improves.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a formation method for semiconductor device, is characterized in that, comprising:
There is provided silicon-on-insulator, described silicon-on-insulator comprises substrate, insulating barrier and top silicon layer successively;
Described top silicon layer forms grid structure;
Side wall is formed in described grid structure both sides;
The top silicon layer of described side wall both sides forms semiconductor layer;
Ion is injected, until form heavily doped region to the top silicon layer below described semiconductor layer and described semiconductor layer;
After ion implantation, described side wall is removed to expose the top silicon layer below described side wall;
Light dope ion implantation technology is carried out to the top silicon layer of described exposure and the described semiconductor layer of at least part of thickness;
After described light dope ion implantation technology, carry out annealing process.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the annealing region of described annealing process is 400 DEG C ~ 800 DEG C, and annealing time scope is 10min ~ 180min.
3. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the ion that described light dope ion implantation technology is injected be phosphonium ion and arsenic ion at least one of them, the doping content scope of described ion is 1E14atom/cm
2~ 1E16atom/cm
2, the Implantation Energy scope of described ion is 100eV ~ 5KeV.
4. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the ion that described light dope ion implantation technology is injected be boron ion and indium ion at least one of them, the doping content scope of described ion is 1E14atom/cm
2~ 1E16atom/cm
2, the Implantation Energy scope of described ion is 100eV ~ 5KeV.
5. the formation method of semiconductor device as claimed in claim 1, is characterized in that, adopts epitaxial growth method to form described semiconductor layer on the silicon layer of described top.
6. the formation method of semiconductor device as claimed in claim 1, is characterized in that, after the described side wall of removal, carries out metalized to the described semiconductor layer of the top silicon layer exposed and at least part of thickness, until form metal silicide layer.
7. the formation method of semiconductor device as claimed in claim 6, it is characterized in that, the described metal silicide layer thickness be formed in described semiconductor layer is more than or equal to the described metal silicide thickness be formed in the silicon layer of described top, and the thickness being formed in the described metal silicide layer in the silicon layer of described top is more than or equal to described top silicon layer thickness.
8. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness range of described semiconductor layer is
9. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness range of described top silicon layer is
10. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the thickness range of described side wall is
The formation method of 11. semiconductor device as claimed in claim 1, it is characterized in that, after described top silicon layer forms grid structure, and before described grid structure both sides form described side wall, be also included in the step that described grid structure both sides form biased side wall; Described light dope ion implantation technology with described biased side wall and described grid structure for mask; Segregation light doping section is formed in the described top silicon layer that described annealing process exposes after making removal side wall.
12. 1 kinds of semiconductor device, comprising:
Silicon-on-insulator, described silicon-on-insulator comprises substrate, insulating barrier and top silicon layer successively;
Be positioned at the grid structure on the silicon layer of described top;
It is characterized in that, also comprise:
Be positioned at the semiconductor layer on the silicon layer of top, described grid structure both sides, between described semiconductor layer and described grid structure, there is gap;
Be arranged in the heavily doped region of the top silicon layer below described semiconductor layer and described semiconductor layer;
The top silicon layer be arranged in below described gap is neutralized to the light doping section of semiconductor layer described in small part.
13. semiconductor device as claimed in claim 12, it is characterized in that, the thickness range of described semiconductor layer is
14. semiconductor device as claimed in claim 12, it is characterized in that, the thickness range of described top silicon layer is
15. semiconductor device as claimed in claim 12, it is characterized in that, the width range in described gap is
16. semiconductor device as claimed in claim 12, is characterized in that, also comprise the metal silicide layer that the top silicon layer be arranged in below described gap is neutralized to semiconductor layer described in small part.
17. semiconductor device as claimed in claim 12, it is characterized in that, described grid structure both sides also have biased side wall, also have segregation light doping section in the top silicon layer below described gap.
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| CN110649000A (en) * | 2018-06-27 | 2020-01-03 | 台湾积体电路制造股份有限公司 | Semiconductor device having capacitor and method of manufacturing the same |
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