CN105528310B - The method of elastic buffer and elastic buffer for high-speed serial bus - Google Patents
The method of elastic buffer and elastic buffer for high-speed serial bus Download PDFInfo
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- CN105528310B CN105528310B CN201510885487.0A CN201510885487A CN105528310B CN 105528310 B CN105528310 B CN 105528310B CN 201510885487 A CN201510885487 A CN 201510885487A CN 105528310 B CN105528310 B CN 105528310B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G06F13/1673—Details of memory controller using buffers
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Abstract
A kind of method of the elastic buffer for high-speed serial bus and elastic buffer is provided.The elastic buffer, including：Input interface, for receiving the data from the first clock domain；Controller for being identified to receiving the idle data unit in data, and counts the number of repetition of the idle data unit recognized, and when the number of repetition reaches reference value, the idle data unit of at least one repetition is abandoned from reception data；Memory, for storing treated reception data；And output interface, for being stored in the treated reception data in the memory to the output of second clock domain.
Description
Technical field
The present invention relates to high-speed serial bus transmission technologys, slow more particularly, to the elasticity for high-speed serial bus
The method for rushing device and elastic buffer.
Background technology
Extensive use with digital device in various fields needs the data storage capacity of bigger and higher bandwidth,
(PCIe) and ultrahigh speed I (UHS-I) are quickly interconnected through developing such as Serial Advanced Technology Attachment (SATA), peripheral assembly
With the high-speed serial bus technology of ultrahigh speed II (UHS-II).It, can be in master by two paths (lane) by taking UHS-II as an example
The transmission rate for being up to 156MB/s (full duplex) or 312MB/s (half-duplex) is realized between machine and storage card.
In physical layer transmission, the interface both sides between host and storage card are in different clock domains.It is different
Usually having between the clock source for sending and receiving both sides of clock domain in phase difference or even frequency also has fine distinction.When for
Reduction electromagnetic interference and when using spread spectrum clock (SSC) technology, the above-mentioned difference between clock source may be more serious.
For this purpose, generally use elastic buffer solves the above problems.That is, the reception data from the first clock domain are pushed away
It send in (push) to elastic buffer, and pops up (pop) and arrive second clock domain.However, if the clock frequency in second clock domain
It is less than the clock frequency of the first clock domain for a long time, then the possible spill-over of elastic buffer so that can not further receive data.Mesh
Before, how UHS-II solves the problems, such as buffer spill-over if being not prescribed by.It is often necessary to design additional hardware configuration to cope with buffering
Device spill-over.In addition, when using two paths transmission data simultaneously in a half-duplex mode, other problem also will produce, that is,
There is also difference between the clock source of different accesses, lead to the water level line (water mark) in the elastic buffer of individual channel
Difference, it is crooked (data skew) that this is known as data.Data are crooked to cause difficulty to the merging of the data of each access.Thus, into
The data that one step needs the additional hardware configuration of such as buffer to be used to eliminate between access are crooked.Above-mentioned additional hardware is matched
It sets and improves design complexities, while making manufacturing cost more high.
Invention content
Therefore, to solve the above-mentioned problems, the present invention provide can prevent buffer spill-over and data it is crooked for height
The receiver of fast universal serial bus and the method for receiving data.
According to one embodiment of present invention, a kind of elastic buffer for high-speed serial bus is provided, including：Input
Interface, for receiving the data from the first clock domain；Controller, for knowing to receiving the idle data unit in data
Not, and to the number of repetition of the idle data unit recognized it counts, when the number of repetition reaches reference value, from reception
The idle data unit of at least one repetition is abandoned in data；Memory, for storing treated reception data；And it is defeated
Outgoing interface, for being stored in the treated reception data in the memory to the output of second clock domain.
According to embodiment, the high-speed serial bus can be ultrahigh speed II (UHS-II) bus, the idle data list
Member includes at least one of following link symbol collection (LSS)：Synchronous (SYN), logical idle (LIDL), data transfer logic are empty
Not busy (DIDL) and direction switching (DIR).
According to embodiment, which may further include register, for the reference value to be arranged.
According to embodiment, the reference value can be determined according to the duration of idle data unit.
According to embodiment, the reference value can be 16 to 256.
According to embodiment, which can be push-up storage.
According to embodiment, which can receive the reception number according to the first clock restored from the reception data
According to, which can export the treated reception data being stored in the memory according to second clock, wherein
The reference value can be determined according to the difference of first clock and the second clock.
According to another embodiment of the present invention, a kind of method of the elastic buffer for high-speed serial bus is provided, including：
Receive the data from the first clock domain；It is identified to receiving the idle data unit in data, and to described in recognizing
The number of repetition of idle data unit is counted, and when the number of repetition reaches reference value, is abandoned at least from receiving in data
The idle data unit of one repetition；Store treated reception data；And export stored warp to second clock domain
Cross the reception data of processing.
According to embodiment, the high-speed serial bus can be ultrahigh speed II (UHS-II) bus, the idle data list
Member includes at least one of following link symbol collection (LSS)：Synchronous (SYN), logical idle (LIDL), data transfer logic are empty
Not busy (DIDL) and direction switching (DIR).
According to embodiment, this method may further include：The reference value is set.
According to embodiment, the reference value can be determined according to the duration of idle data unit.
According to embodiment, the reference value can be 16 to 256.
According to embodiment, treated reception data can be stored in push-up storage.
According to embodiment, the reception data can be received according to the first clock restored from the reception data, and can be with
Stored treated reception data are exported according to second clock, wherein the reference value can be according to described first
What the difference of clock and the second clock determined.
According to an embodiment of the invention, when cross clock domain receives data, by certain types of control data cell
The number of repetition of (for example, idle data unit) is counted and abandons the control data cell of at least one repetition, Ke Yiyou
Water level line in effect ground control buffer is to prevent buffer full from overflowing without increasing hardware design complexity.In addition, passing through
It in the case that multiple accesses receive data, can further solve that data occur due to clock frequency difference between different accesses
Crooked problem.
Description of the drawings
Fig. 1 is the block diagram for showing the receiver 100 according to an embodiment of the invention for high-speed serial bus；
Fig. 2 is the flow for the method for showing the reception data according to an embodiment of the invention for high-speed serial bus
Figure；
Fig. 3 is the block diagram for showing the elastic buffer 300 according to an embodiment of the invention for high-speed serial bus；With
And
Fig. 4 is the flow for the method for showing the elastic buffer according to an embodiment of the invention for high-speed serial bus
Figure.
Specific implementation mode
It is described in detail with reference to the accompanying drawings according to an exemplary embodiment of the invention.It, will be same or similar attached in attached drawing
Icon note assigns structure and function substantially the same composition part, and in order to keep specification conciser, be omitted about
The redundancy description of essentially the same composition part.
Hereinafter, implementation of the invention will be described using ultrahigh speed II (UHS-II) as the example of high-speed serial bus
Example.However, the invention is not limited thereto.The solution of the present invention can also be applied to use elastic buffer between different clock-domains
Other high-speed serial bus (such as SATA or PCIe buses) technologies.
Fig. 1 is the block diagram for showing the receiver 100 according to an embodiment of the invention for high-speed serial bus.
Referring to Fig.1, receiver 100 may include decoder 101, counter 102, controller 103 and buffer 104.
In one embodiment, receiver 100 can be set in the physical layer of host or storage card.Receiver 100 connects from the first clock domain
Data are received, and export treated reception data to second clock domain.For example, the side of receiver 100 is via clock number
Recovered clock source is generated from from the data that transmitter (figure is not painted) receives according to recovery (CDR), and according to generated recovery
Clock source will receive in data-pushing (push) to receiver 100, and 100 other sides pop-up (pop) of receiver is treated
Data are received to second clock domain, second clock domain is, for example, host or the clock source of storage card local.
Decoder 101 can determine the type of the control data cell in the data of reception.For example, in UHS-II, control
Data cell processed can be link symbol collection (LLS), including：Synchronous (SYN), bootstrapping synchronous (BSYN), direction switching (DIR),
Logical idle (LIDL), data transfer logic idle (DIDL), data burst start (SDB), data burst terminates (EDB), divides
Group starts (SOP), grouping terminates (EOP) etc..Each LLS has respective signal pattern, the signal that decoder 101 passes through LLS
Pattern determines its type.For example, LIDL may include two symbols, first symbol is comma (COM) (K28.5), second
A symbol can be the randomly selected symbol from LIDL0 (K28.3) and LIDL1 (D16.7).UHS-II physical layer specifications 4.0
The signal pattern of the various LLS of middle specified in more detail and effect, which is not described herein again.
Counter 102 can count the number of repetition of certain types of control data cell.It is according to the present invention
Embodiment, when the type for controlling data cell is determined to belong to idle data unit by decoder 101, controller 103 can be with
The number of repetition that control counter 102 is confirmed as belonging to the control data cell of idle data unit to type counts.
In UHS-II, idle data unit can be at least one of following LLS or whole：SYN, DIR, LIDL and DIDL.So
And this is only example, the invention is not limited thereto.In addition, according to embodiment, it can also be to other than idle data unit
The number of repetition of other control data cells is counted.
When the number of repetition reaches reference value, controller 103 can abandon at least one repetition from receiving in data
Aforementioned certain types of control data cell, and treated reception data are stored in buffer 104, so as to second
Clock domain provides.According to embodiment, buffer 104 can be elastic buffer.Since specific type controls in only input data
The very small part of data cell is dropped, and can efficiently control the water level line of buffer 104, to prevent buffer 104
Spill-over.In order to avoid influencing to transmit signaling, idle data unit can be only abandoned.
In UHS-II, the LLS of such as SYN, DIR, LIDL and DIDL as idle data unit are usually largely weighed
Recurrence is sent, therefore the LLS for suitably abandoning repetition will not cause the subsequently decoding error to receiving data.The present invention is according to reference
Value control abandons the frequency for repeating LLS so that the water level line of elastic buffer will not be both too high and to close to spill-over, will not
It is too low so that close to emptying.For this purpose, according to embodiment, receiver 100 may further include register (not shown), be used for
The reference value is set, certain types of idle data unit is used for.In one embodiment, reference value is by idle data unit
Duration determine, particularly, be by the shortest idle data unit of duration in idle data unit it is lasting when
Between determine.For example, the duration of DIR is most short, it is N_LSS_DIR*8 (for example, N_LSS_DIR can be equal to 8), can incites somebody to action
Reference value is set as 16, i.e., whenever (including SYN, DIR, LIDL and DIDL's is complete for the idle data unit for receiving 16 repetitions
Portion or some types) when, one duration shortest DIR of discarding is just enough to maintain the water level line of buffer 104 relatively low
Level does not interfere with the subsequently decoding to receiving data without spill-over, then then abandoning an any type of free time
Data cell just one establishes a capital and is enough the water level line of buffer 104 being reduced to reduced levels and will not cause decoding error.It is another
Aspect, reference value is also by the clock source difference (including phase difference and/or frequency difference) of the first clock domain and second clock domain
It determines, the difference of clock source is bigger, and the reference value is smaller, but the influence of usually clock source difference is smaller.In other embodiment
In, it might even be possible to the reference value is set as high as 256, that is, the idle data unit of every 256 repetitions just abandons one,
Still it is enough that water level line is reduced to lower level rapidly, and decoding error will not be caused.
According to embodiment, receiver 100 may include multiple data paths, at this point, each data path may include list
Only counter 102 and buffer 104.In a half-duplex mode, idle data can be abandoned respectively in each buffer 104
Unit is crooked to eliminate data so that the water level line of the buffer 104 of individual channel is concordant, in order to the merging of data.
Fig. 2 is the flow for the method for showing the reception data according to an embodiment of the invention for high-speed serial bus
Figure.
With reference to Fig. 2, in step S201, it may be determined that receive the type of the control data cell in data.As described above,
In UHS-II, control data cell can be LLS, including：SYN, BSYN, DIR, LIDL, DIDL, SDB, EDB, SOP, EOP etc..
Its type can be determined by the signal pattern of LLS.
It, can be if the type of control data cell belongs to certain types of control data cell in step S202
Step S203 counts the number of repetition of certain types of control data cell, otherwise, enters step S206.Institute as above
It states, by taking UHS-II as an example, certain types of control data cell may include at least one of following LSS or whole：SYN、
LIDL, DIDL and DIR.However this is example, the invention is not limited thereto.In addition, according to embodiment, it can also be in addition to sky
The number of repetition of other certain types of control data cells except not busy data cell is counted.
In step S204, if number of repetition reaches reference value, can step S205 from receive data in abandon to
The certain types of control data cell (or other control data cells) of a few repetition, otherwise, may return to step S203
Continue to count.
In step S206, treated reception data are stored, to be provided to second clock domain.
As described above, in order to accurately control the water level line in buffer, it can be according to certain types of control data sheet
The duration of member (e.g., including SYN, DIR, LIDL and DIDL) and the clock source of the first clock domain and second clock domain
Difference determines the reference value.The reference value can be 16 to 256.
In addition, according to embodiment, when being transmitted by multiple data paths, meter can be individually performed to each data path
Number and caching.In a half-duplex mode, can to abandon idle data unit respectively in each data path askew to eliminate data
Tiltedly so that water level line is concordant, in order to the merging of data.
Fig. 3 is the block diagram for showing the elastic buffer 300 according to an embodiment of the invention for high-speed serial bus.Figure
3 elastic buffer 300 is different from the buffer 104 of Fig. 1, its own, which has, is counted and abandoned to idle data unit
Function.
With reference to Fig. 3, elastic buffer 300 may include that input interface 301, controller 302, memory 303 and output connect
Mouth 304.
Controller 302 can be to the idle data in the data from the first clock domain that are received by input interface 301
Unit is identified, and is counted to the number of repetition of the idle data unit recognized, when the number of repetition reaches reference
When value, the idle data unit of at least one repetition is abandoned from receiving in data, and treated reception data are stored in
In memory 303.In one embodiment, memory 303 is a first-in first-out buffer (FIFO buffer).
Output interface 304 can be exported to second clock domain at the process above controller 302 being stored in memory 303
The reception data of reason.
As described above, the high-speed serial bus can be UHS-II buses, the idle data unit may include with
At least one of lower LSS or whole：SYN, LIDL, DIDL and DIR.
In addition, according to embodiment, in order to accurately control water level line, elastic buffer 300 may further include deposit
Device (not shown), for the reference value to be arranged.Specifically, can according to idle data unit (including SYN, DIR, LIDL and
The clock source difference in duration DIDL) and/or the first clock domain and second clock domain determines the reference value.The ginseng
It can be 16 to 256 to examine value.
Fig. 4 is the flow for the method for showing the elastic buffer according to an embodiment of the invention for high-speed serial bus
Figure.
With reference to Fig. 4 the data from the first clock domain are received in step S401.
In step S402, it is identified to receiving the idle data unit in data, and the idle data list to recognizing
The number of repetition of member is counted.For UHS-II buses, the idle data unit may include at least one in following LSS
Kind is whole：SYN, LIDL, DIDL and DIR.
In step S403, if number of repetition reaches reference value, at least one is abandoned from receiving data in step S404
Otherwise the idle data unit of a repetition may return to step S402 and continue to count.
In step S405, treated reception data are stored.
In step S406, stored treated reception data are exported to second clock domain.
It, can be according to the duration of idle data unit and/or the first clock domain and second clock domain according to embodiment
Clock source difference determine the reference value.The reference value can be 16 to 256.
As described above, having been described above each embodiment for specifically describing the present invention, but the invention is not restricted to this.
It should be appreciated by those skilled in the art, can be carry out various modifications, be combined according to design requirement or other factors, sub-portfolio or
Person replaces, and they are in the range of the appended claims and its equivalent.
Claims (10)
1. a kind of elastic buffer for high-speed serial bus, including：
Input interface, for receiving the data from the first clock domain；
Controller, for being identified to receiving the idle data unit in data, and the idle data list to recognizing
The number of repetition of member is counted, and when the number of repetition reaches reference value, at least one repetition is abandoned from the reception data
The idle data unit；
Memory, for storing the treated reception data；And
Output interface, for being stored in the treated reception data in the memory to the output of second clock domain.
2. elastic buffer as described in claim 1, wherein the high-speed serial bus is ultrahigh speed II (UHS-II) total
Line, the idle data unit include at least one of following link symbol collection (LSS)：Synchronous (SYN), logical idle
(LIDL), data transfer logic idle (DIDL) and direction switching (DIR).
3. elastic buffer as described in claim 1, further comprises：
Register, for the reference value to be arranged.
4. elastic buffer as described in claim 1, wherein the reference value is continued according to the idle data unit
What the time determined.
5. elastic buffer as described in claim 1, wherein the reference value is 16 to 256.
6. elastic buffer as described in claim 1, wherein the memory is push-up storage.
7. elastic buffer as described in claim 1, wherein the input interface is according to first restored from the reception data
Clock receives the reception data, which is stored in described treated in the memory according to second clock output
The reception data, wherein the reference value is determined according to the difference of first clock and the second clock.
8. a kind of method of elastic buffer for high-speed serial bus, including：
Receive the data from the first clock domain；
It is identified to receiving the idle data unit in data, and to the number of repetition of the idle data unit recognized
It is counted, when the number of repetition reaches reference value, the idle data of at least one repetition is abandoned from reception data
Unit；
Store treated reception data；And
The stored treated reception data are exported to second clock domain.
9. method as claimed in claim 8, wherein the high-speed serial bus is ultrahigh speed II (UHS-II) bus, described
Idle data unit includes at least one of following link symbol collection (LSS)：Synchronous (SYN), logical idle (LIDL), data
Transmission logic free time (DIDL) and direction switching (DIR).
10. method as claimed in claim 8, wherein the reference value is the duration according to the idle data unit
Determining.
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| US8806093B2 (en) * | 2010-04-01 | 2014-08-12 | Intel Corporation | Method, apparatus, and system for enabling a deterministic interface |
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| CN1812313A (en) * | 2005-01-26 | 2006-08-02 | 华为技术有限公司 | Method for controlling radio link control layer buffer area overflow |
| CN101192912A (en) * | 2006-11-30 | 2008-06-04 | 中芯国际集成电路制造(上海)有限公司 | System and method for data transmission based on buffer control |
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