CN105518794A

CN105518794A - Semiconductor storage device and data writing method

Info

Publication number: CN105518794A
Application number: CN201380079357.7A
Authority: CN
Inventors: 白川政信
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 2013-09-05
Filing date: 2013-09-05
Publication date: 2016-04-20
Also published as: WO2015033417A1; JPWO2015033417A1

Abstract

A semiconductor storage device according to one embodiment is equipped with multiple memory cells, word lines, bit lines, and a row decoder. The memory cells are stacked on a semiconductor substrate. The word lines are connected to the gates of the memory cells. The bit lines are electrically connected to the current paths of the memory cells, and are capable of transmitting data. The row decoder applies a voltage to the word lines. Data is written to a memory cell by multiple repetitions of a program loop that includes a program operation and a verification operation. In one program loop the row decoder sequentially applies the program voltage M times (where M is a natural number of 1 or greater) to a selected word line, and then sequentially applies a verification voltage N times (where N is larger than M and is a natural number of 3 or greater) to the selected word line.

Description

Semiconductor storage and method for writing data

Technical field

Embodiments of the present invention relate to semiconductor storage and method for writing data.

Background technology

There will be a known the NAND flash memory of three-dimensional arrangement storage unit.

Summary of the invention

The problem that invention will solve

A kind of semiconductor storage and the method for writing data that can improve the writing speed of data are provided.

For the means of dealing with problems

The semiconductor storage that embodiment relates to possesses multiple storage unit, wordline, bit line and row decoder.Storage unit is layered on semiconductor substrate.Wordline is connected with the grid (gate) of storage unit.Bit line is electrically connected with the current path of storage unit, and can transmit data.Row decoder applies voltage to wordline.Write to the data of storage unit is performed by the program cycles repeatedly repeatedly comprising programing work and checking work.In one-time programming circulation, row decoder applies the first program voltage and second program voltage different from this first program voltage successively to selection wordline.

Accompanying drawing explanation

Fig. 1 is the block diagram of the semiconductor storage that the first embodiment relates to.

Fig. 2 is the circuit diagram of the memory cell array that the first embodiment relates to.

Fig. 3 is the stereographic map of the memory cell array that the first embodiment relates to.

Fig. 4 is the vertical view of the memory cell array that the first embodiment relates to.

Fig. 5 is the cut-open view along the 5-5 line in Fig. 4.

Fig. 6 is the cut-open view along the 6-6 line in Fig. 4.

Fig. 7 is the cut-open view along the 7-7 line in Fig. 4.

Fig. 8 is the chart of the threshold value distribution representing the storage unit that the first embodiment relates to.

Fig. 9 is the circuit diagram of the memory cell array that the first embodiment relates to.

Figure 10 is the process flow diagram of the wiring method representing the data that the first embodiment relates to.

The sequential chart of word line potential when Figure 11 is the write of the data that the first embodiment relates to.

Figure 12 is the sequential chart of the change of the word line potential represented when writing data.

Figure 13 is the process flow diagram of the wiring method representing the data that the second embodiment relates to.

The sequential chart of the change of word line potential when Figure 14 is the write representing the data that the second embodiment relates to.

Figure 15 is the process flow diagram of the wiring method representing the data that the 3rd embodiment relates to.

The sequential chart of the change of word line potential when Figure 16 is the write representing the data that the 3rd embodiment relates to.

Figure 17 is the process flow diagram of the wiring method representing the data that the 4th embodiment relates to.

The sequential chart of wordline when Figure 18 is the write representing the data that the 4th embodiment relates to and the change of bit line potential.

Figure 19 is the circuit diagram of the memory cell array that the 4th embodiment relates to.

Figure 20 is the chart of the changes of threshold representing the storage unit that the 4th embodiment relates to.

Figure 21 is the block diagram of sensor amplifier (SenseAmplifier) module, computing module and the latches data module that the 5th embodiment relates to.

The chart of the change of word line potential when Figure 22 is the write representing the data that the 5th embodiment relates to.

The chart of wordline when Figure 23 is the write representing the data that the 5th embodiment relates to and the change of bit line potential.

Figure 24 is the block diagram of the storage system that the 6th embodiment relates to.

The sequential chart of various signals when Figure 25 is the write work of the first mode that the 6th embodiment relates to.

The sequential chart of various signals when Figure 26 is the write work of the second pattern that the 6th embodiment relates to.

Embodiment

Hereinafter, with reference to the accompanying drawings of embodiment.When carrying out this explanation, throughout whole accompanying drawing, give common reference marks to common part.

1. the first embodiment

The semiconductor storage that first embodiment relates to is described.In the following description, as semiconductor storage, the three-dimension layer stack-type NAND flash memory being set forth in stacked storage unit on semiconductor substrate is that example is described.

1.1 about the formation of semiconductor storage

First, the formation of semiconductor storage of the present embodiment is described.

1.1.1 the entirety about semiconductor storage is formed

Fig. 1 is semiconductor storage block diagram of the present embodiment.As shown in the figure, NAND flash memory 1 possesses memory cell array 10, row decoder 11, sensor amplifier module 12, computing module 13, latches data module 14 and control part 17.

Memory cell array 10 possesses multiple non-volatile memory cells.Storage unit is such as the MOS transistor having possessed stacked grid, and described stacked grid comprise charge accumulation layer and control gate, and each storage unit is associated by row and column.And the control gate being positioned at the storage unit of same a line is connected with same wordline WL, the leakage (drain) being positioned at the storage unit of same row is connected with same bit line BL, and source electrode is connected with source electrode line SL.The details of memory cell array 10 will be described below.

The line direction of row decoder 11 select storage unit array 10.That is, row decoder 11 the write of data, reading and erasing time select wordline WL, and apply suitable voltage to selection wordline and non-selection wordline.

Sensor amplifier module 12 possesses the sensing circuit arranged by every bit lines.Each sensing circuit, when the reading of data, reads the data reading into bit line BL from storage unit and amplifies.In addition, sensing circuit, when the write of data, will answer write storage unit data to send bit line BL to.

Computing module 13 possesses the computing circuit arranged by every bit lines.Each computing circuit, when the reading of data, uses to be read by sensing circuit and amplified the data obtained and carries out computing.In addition, computing circuit, when the write of data, carries out the computing employing write data, and sends operation result to sensing circuit.

Latches data module 14 possesses the latch cicuit arranged by every bit lines.Each latch cicuit, when the reading of data, keeps the sense data sent from sensing circuit via computing circuit.And sense data is outputted to outside by latch cicuit.In addition, latch cicuit, when the write of data, temporarily keeps being received externally write data.And latch cicuit sends write data to sensing circuit via computing circuit.

Control part 15 controls the work of flash memory 1 entirety.

1.1.2 about the formation of memory cell array

Fig. 2 is the circuit diagram of memory cell array 10 of the present embodiment.As shown in the figure, memory cell array 10 possesses multiple storage unit MU (MU1, MU2).In fig. 2, illustrate only two storage unit MU, but also can be more than three, its quantity not circumscribed.

Each storage unit MU such as possesses four string groups (stringgroup) GR (GR1 ~ GR4) respectively.In addition, when distinguishing between storage unit MU1 and MU2, the string group GR of storage unit MU1 is called GR1-1 ~ GR4-1, the string group GR of storage unit MU2 is called GR1-2 ~ GR4-2.

Each string group GR such as possesses three NAND string SR (SR1 ~ SR3) respectively.Certainly, the quantity of NAND string SR is not limited to three, also can be more than four.Each of NAND string SR possesses selection transistor ST1 and ST2 and four memory cell transistor MT (MT1 ~ MT4) respectively.The quantity of memory cell transistor MT is not limited to four, both can be more than five, also can be less than three.Memory cell transistor MT possesses stacked grid and keeps data non-volatilely, and described stacked grid comprise control gate and charge accumulation layer.And memory cell transistor MT is selecting the source electrode of transistor ST1 and is selecting to be connected in series between the leakage of transistor ST2.

In string group GR, three NAND string SR1 ~ SR3 stack gradually on a semiconductor substrate, and NAND string SR1 is formed in orlop, and NAND string SR3 is formed in the superiors.And selection transistor ST1 with ST2 comprised with a string group of GR is connected with same selection grid line GSL1 and GSL2 respectively, and the control gate being positioned at the memory cell transistor MT of same row is connected with same wordline WL.Further, select the leakage of transistor ST1 to connect from mutually different bit line BL for three in certain string group GR, select the source electrode of transistor ST2 to be connected with same source electrode line SL.

In odd number string group GR1 and GR3, even number string group GR2 and GR4, transistor ST1 and ST2 is selected to be configured to its position relationship contrary.That is, if the example of Fig. 2, the selection transistor ST1 of string group GR1 and GR3 is configured in the left end of NAND string SR, selects transistor ST2 to be configured in the right-hand member of NAND string SR.On the other hand, the selection transistor ST1 of string group GR2 and GR4 is configured in the right-hand member of NAND string SR, selects transistor ST2 to be configured in the left end of NAND string SR.

And string group GR1 is connected with same selection grid line GSL1 with the grid of the selection transistor ST1 of GR3, the grid of transistor ST2 are selected to be connected with same selection grid line GSL2.On the other hand, string group GR2 is connected with same selection grid line GSL2 with the grid of the selection transistor ST1 of GR4, selects the grid of transistor ST2 to be connected with same selection grid line GSL1.

In addition, four string group GR1 that certain storage unit MU comprises are connected with same bit line BL mutually with GR2, and different storage unit MU connects from mutually different bit line BL.More specifically, in storage unit MU1, the leakage of the selection transistor ST1 of the NAND string SR1 ~ SR3 in string group GR1 ~ GR4 is connected with bit line BL1 ~ BL3 via column selection grid CSG (CSG1 ~ CSG4) respectively.Column selection grid CSG such as has and memory cell transistor MT, the formation of selecting transistor ST1 and ST2 etc. same, and selects a string group GR in each storage unit MU, and described string group GR selects bit line BL.Therefore, the grid carrying out associating the column selection grid CSG1 ~ CSG4 obtained from each string group GR are controlled by different control signal wire SSL1 ~ SSL4 respectively.

On the paper describing Fig. 2, be arranged with multiple storage unit MU with formation described above in the vertical direction.These multiple storage unit MU have storage unit MU1, wordline WL and select grid line GSL1 and GSL2.On the other hand, bit line BL is independent, such as, relative to storage unit MU2, is associated with the three bit lines BL4 ~ BL6s different from storage unit MU1.To go here and there the sum of SR corresponding with the number of the bit line BL that each storage unit MU associates and the NAND that a string group GR comprises.Therefore, if NAND string is 4 layers, then also arrange 4 bit lines BL, the situation of other quantity too.In addition, control signal SSL1 ~ SSL4 both can share between storage unit MU, or also can control independently.

In the above-described configuration, the set of the multiple memory cell transistor MT be connected with same wordline WL in the string group GR selected one by one from each storage unit MU becomes the unit being called as " page ".And the writing and reading of data are carried out in units of page.

Fig. 3 is the stereographic map of memory cell array 10, and Fig. 4 is the vertical view of memory cell array 10, and Fig. 5 is the cut-open view along the 5-5 line in Fig. 4, and Fig. 6 is the cut-open view along the 6-6 line in Fig. 4, and Fig. 7 is the cut-open view along the 7-7 line in Fig. 4.In Fig. 3, Fig. 5 and Fig. 7, figure is shown with storage unit MU, Fig. 4 and a Fig. 6 and illustrates two storage unit MU1 and MU2.

As shown in the figure, semiconductor substrate 20 is formed with dielectric film 21, dielectric film 21 is formed memory cell array 10.

On dielectric film 21, by formed along the second direction vertical with first direction striated, such as four fin-types structure 24 (24-1 ~ 24-4) and be formed with a storage unit MU, described first direction is the vertical direction relative to semiconductor substrate 20 surface.Each fin-type structure 24 comprises alternately laminated dielectric film 22 (22-1 ~ 22-4) and semiconductor layer 23 (23-1 ~ 23-3).This each fin-type structure 24 is equivalent to the string group GR illustrated in fig. 2.And, undermost semiconductor layer 23-1 is equivalent to the current path (being formed with the region of raceway groove) of NAND string SR1, the semiconductor layer 23-3 of the superiors is equivalent to the current path of NAND string SR3, and the semiconductor layer 23-2 be positioned in the middle of it is equivalent to the current path of NAND string SR2.

In upper surface and the side of fin-type structure 24, be formed with gate insulating film 25, charge accumulation layer 26, block dielectric film 27 and control gate 28 (with reference to Fig. 5) successively.Charge accumulation layer 26 is such as formed by dielectric film.In addition, control gate 28 is formed by conducting film, and plays function as wordline WL or selection grid line GSL1 and GSL2.Wordline WL, selection grid line GSL1 and GSL2 are formed as crossing multiple fin-type structure 24 at multiple storage unit MU span.On the other hand, control signal wire SSL1 ~ SSL4 is independent by each fin-type structure 24.

One end of fin-type structure 24 is drawn out in the end of memory cell array 10, and is connected with bit line BL in the region be drawn out.Namely, as an example, when being conceived to storage unit MU1, an end of odd number fin-type structure 24-1 with 24-3 pulled into certain region along second direction and is commonly connected, and is formed with contact plug (contactplug) BC1 ~ BC3 in this region.String group GR1 is connected with bit line BL1 with the semiconductor layer 23-1 of GR3 by the contact plug BC1 formed in this region, insulate with semiconductor layer 23-2 and 23-3.String group GR1 is connected with bit line BL2 with the semiconductor layer 23-2 of GR3 by contact plug BC2, insulate with semiconductor layer 23-1 and 23-3.String group GR1 is connected with bit line BL3 with the semiconductor layer 23-3 of GR3 by contact plug BC3, insulate with semiconductor layer 23-1 and 23-2.

On the other hand, an end of even number fin-type structure 24-2 with 24-4 pulled into the region in opposite directions, an end constructing 24-1 and 24-3 in a second direction with fin-type and is also commonly connected, and is formed with contact plug BC1 ~ BC3 in this region.String group GR2 is connected with bit line BL1 with the semiconductor layer 23-1 of GR4 by the contact plug BC1 formed in this region, insulate with semiconductor layer 23-2 and 23-3.String group GR2 is connected with bit line BL2 with the semiconductor layer 23-2 of GR4 by contact plug BC2, insulate with semiconductor layer 23-1 and 23-3.String group GR2 is connected with bit line BL3 with the semiconductor layer 23-3 of GR4 by contact plug BC3, insulate with semiconductor layer 23-1 and 23-2.

Certainly, above-mentioned explanation is to explanation when storage unit MU1, such as, when storage unit MU2, is formed with contact plug BC4 ~ BC6, and semiconductor layer 23-1 ~ 23-3 is connected with bit line BL4 ~ BL6 by respectively (with reference to Fig. 6).

In addition, the other end of fin-type structure 24 is formed with contact plug SC.Semiconductor layer 23-1 ~ 23-3 is connected with source electrode line SL by contact plug SC.

In the above-described configuration, to go here and there the size of memory cell transistor that SR1 ~ SR3 comprises mutually different for NAND.More specifically, as shown in Figure 5, in each fin-type structure 24, it is larger that the width along third direction of semiconductor layer 23 is positioned at lower layer width, is positioned at higher layer width less.That is, the width of semiconductor layer 23-1 is the widest, and the width of semiconductor layer 23-3 is the narrowest, and the width of semiconductor layer 23-2 is its intermediate value.That is, multiple memory cell transistor MT that characteristic is different each other due to manufacture deviation are included in 1 page.

1.1.3 the threshold value about memory cell transistor distributes

Fig. 8 represents the threshold value that can the obtain distribution of memory cell transistor MT of the present embodiment.As shown in the figure, memory cell transistor MT according to its threshold value, such as, can keep two bits.These two (bit) data, from threshold value is low, are followed successively by such as " Ep " level, " A " level, " B " level and " C " level.

" EP " level is the threshold value under the state that is wiped free of of data, such as, have positive value, and lower than verifying voltage Vfy_A." A " ~ " C " level is the threshold value under the state being filled with electric charge in charge accumulation layer, " A " level has higher than verifying voltage Vfy_A, and the threshold value lower than verifying voltage Vfy_B, " B " level has higher than verifying voltage Vfy_B, and the threshold value lower than verifying voltage Vfy_C, " C " level has the threshold value higher than verifying voltage Vfy_C.

Like this, can obtain four threshold levels, thus, each memory cell transistor MT can store two bits (4-level data).

1.2 about the write work of data

Then, the write work of data of the present embodiment is described.When the explanation of the work of write, in order to carry out define storage units transistor MT based on its position (layer) and write data, Fig. 9 is used to be described.Fig. 9 is the circuit diagram of memory cell array 10, for the purpose of simplifying the description, represent the situation only comprising two storage unit MU1 and MU2 in memory cell array 10, in addition, showing by selecting control signal wire SSL1 and SSL5, have selected the situation of the string group GR1-1 in storage unit MU1 and the string group GR1-2 in storage unit MU2.Therefore, in string group GR1-1 and GR1-2, form page by 6 the memory cell transistor MT be connected with same wordline WL.In addition, due to the relation of length, only illustrate the string group GR1-1 and GR1-2 that select, in addition, eliminate the diagram of column selection grid CGS.In the explanation below carried out, the situation that have selected the combination of other string groups is like this too.

As mentioned above, in certain string group GR, the width being positioned at the semiconductor layer 23 of undermost memory cell transistor MT (NAND go here and there SR1) is maximum.Therefore, the writing speed of data is the highest.On the other hand, the width being positioned at the semiconductor layer 23 of the memory cell transistor MT (NAND go here and there SR3) of the superiors is minimum.Therefore, the writing speed of data is minimum.

Therefore, when writing data in units of page, writing the orlop that (writing speed the is high) memory cell transistor terminated the soonest is arranged in fin-type structure 24, and being the memory cell transistor MT being written with " A " level.In the following description, such memory cell transistor MT is called first module.On the other hand, write the superiors that (writing speed the is low) memory cell transistor terminated at the latest is arranged in fin-type structure 24, and be the memory cell transistor MT being written with " C " level.Such memory cell transistor MT is called Unit the 3rd.And, other memory cell transistors MT is called second unit.

Then, use Fig. 9 to Figure 11 that the wiring method of data is described.Figure 10 is the process flow diagram of wiring method, is applied to the sequential chart of the voltage selected on wordline WL when Figure 11 is write.

First, respond the order of control part 15, row decoder 11 selects arbitrary wordline WL, selection wordline WL applies program voltage VPGM and programmes to data.In the example of figure 9, select wordline WL1, in string group GR1-1 and GR1-2, in 6 the memory cell transistor MT be connected with wordline WL1, be programmed data (step S10).

Now, as shown in figure 11, row decoder 11 applies program voltage VPGM1, VPGM2 and VPGM3 successively on selection wordline WL1.Voltage VPGM1 ~ VPGM3 is the programming voltage for Unit the first ~ three respectively, has the relation of VPGM1<VPGM2<VPGM3.In addition, row decoder 11 applies voltage VPASS on non-selection wordline WL2 ~ WL4.No matter voltage VPASS is the voltage keeping data how to make memory cell transistor MT conducting, is the voltage lower than program voltage VPGM1 ~ VPGM3.In addition, row decoder 11 applies voltage VSG to selection grid line GSL1, and applies such as 0V on selection grid line GSL2.Voltage VSG is the selection transistor ST1 conducting of the NAND string SR making to become programming object, and the voltage that the selection transistor ST1 making the NAND becoming non-programmed object go here and there SR ends.In addition, by providing low level to control signal wire SSL2 ~ SSL4, non-selected string group GR2 ~ GR4 and bit line BL is electrically separated.

During row decoder 11 is applied with voltage VPGM1 to selection wordline WL1, sensor amplifier module 12 applies 0V to the bit line BL (being BL1 in the example of figure 9) being connected with first module.Thus, go here and there in SR1 at the NAND comprising first module, select transistor ST1 conducting, be programmed data in first module.In addition, row decoder 11 applies voltage V1 (>0V) to the bit line BL (being BL2 ~ BL6 in the example of figure 9) being connected with second unit and Unit the 3rd.Thus, go here and there in SR at the NAND comprising second unit and Unit the 3rd, select transistor ST1 to be cut off, prohibit the programming to second unit and Unit the 3rd.

Then, during row decoder 11 is applied with voltage VPGM2 to selection wordline WL1, sensor amplifier module 12 applies 0V to the bit line BL (being BL2 ~ BL5 in the example of figure 9) being connected with second unit.Thus, go here and there in SR at the NAND comprising second unit, select transistor ST1 conducting, data programing is carried out to second unit.In addition, row decoder 11 applies voltage V1 to the bit line BL (being BL1 and BL6 in the example of figure 9) being connected with first module and Unit the 3rd.Thus, the programming to first module and Unit the 3rd is prohibited.

Then, during row decoder 11 is applied with voltage VPGM3 to selection wordline WL1, sensor amplifier module 12 applies 0V to the bit line BL (being BL6 in the example of figure 9) being connected with Unit the 3rd.Thus, data programing is carried out to Unit the 3rd.In addition, row decoder 11 applies voltage V1 to the bit line BL (being BL1 ~ BL5 in the example of figure 9) being connected with first module and second unit.Thus, the programming to first module and second unit is prohibited.

By above three steps, be programmed data successively to the first module be connected with wordline WL1 ~ Unit the 3rd.Can judge which of first module ~ Unit the 3rd memory cell transistor MT be equivalent to according to the address of memory cell transistor MT.That is, control part 15 and row decoder 11 can according to becoming the address of memory cell transistor MT of write object and the data that should write to this memory cell transistor MT, and which of the 3rd program voltage decision be applying first to.

Then, control part 15, after the programming of step S10, verifies the data (step S11) of programming in memory cell transistor MT.

Now, row decoder 11, in response to the order of control part 15, as shown in figure 11, applies verifying voltage Vfy_A, Vfy_B and Vfy_C to selection wordline WL1 successively.In addition, row decoder 11 applies voltage VREAD to non-selection wordline WL2 ~ WL4.No matter voltage VREAD is the voltage keeping data how to make memory cell transistor MT conducting.In addition, row decoder 11 applies high level to selection grid line GSL1 and GSL2, and makes selection transistor ST1 and ST2 conducting.In addition, by providing low level to control signal wire SSL2 ~ SSL4, non-selected string group GR2 ~ GR4 and bit line BL is electrically separated.

At checking duration of work, sensor amplifier module 12 applies pre-charge voltage to bit line BL1 ~ BL6, reads and is amplified in the electric current flowed in bit line BL1 ~ BL6.Thus, the data obtained of programming in memory cell transistor MT are differentiated.

When being applied with verifying voltage Vfy_A, if flowed in the bit line BL that electric current connects at the memory cell transistor MT that should write " A " level, so because the threshold value of this memory cell transistor MT does not rise to " A " level, so the known programming to this memory cell transistor MT does not complete (being referred to as authentication failed).On the other hand, if current flowing, so because the threshold value of this memory cell transistor MT rises to " A " level, so the known programming to this memory cell transistor MT completes (be referred to as and be verified).Like this too to the programming of " B " level and " C " level.

After step S11, if complete (step S12 to the programming of first module, be), (step S13 is completed to the programming of Unit the 3rd, be), the programming of second unit is completed (step S14, yes), then control part 15 is judged as normally completing the programming of the expected data selecting page, terminates write work.

If after step S11, (step S12 is completed to the programming of first module, be), (step S13 is not completed to the programming of Unit the 3rd, no), then control part 15 omits the applying of voltage VPGM1, and is boosted (step S15) by voltage VPGM2 and VPGM3, repeatedly carries out the process of step S10 simultaneously.

If after step S11, (step S12 is not completed to the programming of first module, no), (step S16 is not completed yet to the programming of Unit the 3rd, no), then control part 15 couples of voltage VPGM1 ~ VPGM3 boost (step S17), repeatedly carry out the process of step S10 simultaneously.If completed (step S16, yes) the programming of Unit the 3rd, then control part 15 omits the applying of voltage VPGM3, and boosts (step S18) to voltage VPGM1 and VPGM2, repeatedly carries out the process of step S10 simultaneously.

If after step S11, to first and the 3rd the programming of unit complete that (step S12, is; Step S13, yes), (step S14 is not completed to the programming of second unit, no), then control part 15 omits the applying of voltage VPGM1 and VPGM3, and boosts (step S19) to voltage VPGM2, repeatedly carries out the process of step S10 simultaneously.

In the example of Figure 11, after second time programming, first module is by checking (moment t4).Therefore, control part 15 omits the applying of voltage VPGM1 in third time programming.In addition, after third time programming, Unit the 3rd is by checking (moment t6).Therefore, control part 15 omits the applying of voltage VPGM3 further in the 4th programming.

1.3 about the effect of present embodiment

If formation of the present embodiment, the writing speed of data can be improved.Below this effect is described.

Figure 12 is the sequential chart of the word line voltage in the common wiring method of NAND flash memory.As shown in the figure, when the programming of data, apply program voltage VPGM to selection wordline, the memory cell transistor MT of corresponding write " A " ~ " C " level carries out data programing in the lump, afterwards, performs checking work.That is, form one-time programming by the applying of one-time programming voltage VPGM and checking work and circulate, this program cycles is repeatedly carried out while boosting to program voltage.

But when such wiring method being applied to the flash memory using Fig. 2 to Fig. 6 to illustrate, the time required for write likely becomes very long.As Fig. 2 to Fig. 6, the memory cell transistor MT be connected in series in NAND goes here and there SR and semiconductor substrate face configured in parallel, further in the vertical direction relative to semiconductor substrate face stacked NAND go here and there SR, the width of the current path of the memory cell transistor MT that one page comprises is different, and writing speed produces deviation.That is, in same one page, write fast memory cell transistor MT and slow memory cell transistor MT and deposit.Its reason is caused by the manufacturing process of memory cell array 10.That is, semiconductor substrate 20, after stacked dielectric film 22-1 ~ 22-4 and semiconductor layer 23-1 ~ 23-4, by these layer of 22-1 ~ 22-4 and 23-1 ~ 23-4 in the lump patterning, thus forms memory cell array 10.Its result, as shown in Figure 5, fin-type structure 24 creates cone angle.

Therefore, when writing data, should be noted that the not highest to the writing speed of data memory cell transistor MT excessively programmes.That is, the voltage VPGM used in the initial program cycles of Figure 12 is set to can not to being positioned at undermost layer and the memory cell transistor MT of write " A " level carries out the fully low value that excessively programming is such.

So, as shown in figure 12, the programing work of the first half in write work in fact only contributes to the high memory cell transistor MT (i.e. first module) of writing speed, and programming pulse during this period can not bring impact to the threshold voltage of the low Unit the 3rd of writing speed substantially.Then, become the programing work of the latter half in write work, finally start to programme to the substance of Unit the 3rd.

That is, although data programing performs in the lump in units of page, first in page is programmed successively to Unit the 3rd in fact.Therefore, program cycles number of times is very many, causes write time needs long-time.

In contrast, in the present embodiment, by preparing multiple program voltage in one-time programming circulation, also can carry out programming to the substance of Unit the 3rd in initial program cycles, and can the write time be shortened.

That is, in the present embodiment, program voltage VPGM is separated into following three pulses.

(1) to being positioned at the fast layer of write and the pulse that applies of unit (first module) of write " A " level: VPGM1

(2) to being positioned at the slow layer of write and the pulse that applies of unit (Unit the 3rd) of write " C " level: VPGM3

(3) to the pulse that the unit (second unit) beyond above-mentioned (1) and (2) applies: VPGM2.

And, in one-time programming circulation, apply the pulse of above-mentioned (1) to (3) successively.The initial value of these pulses is according to utilizing the writing speed of the memory cell transistor MT of these pulse program and writing data and be set as best value.That is, as long as the value excessively can not programmed to Unit the 3rd, then the initial value of voltage VPGM3 can be the value of excessively programming to first module or second unit.Certainly, the initial value of voltage VPGM1 is set to the value that first module excessively can not be programmed in one-time programming work.

Thereby, it is possible to from initial program cycles, substantive programming is all performed to first module to Unit the 3rd.In other words, in initial program cycles, the threshold voltage of Unit the 3rd also can be made effectively to increase.Its result, can significantly cut down program cycles number of times, and improve writing speed.

In addition, figure 11 illustrates and omit VPGM1 at first, then omit the example of VPGM3, but also can obtain contrary situation, or also can be eliminated the situation of VPGM1 and VPGM3 simultaneously.

As the result that have employed above-mentioned wiring method, in any one program cycles, row decoder 11 applies M (M is the natural number of more than 1) program voltage (t5 ~ t6 of Figure 11 successively to selection wordline WL, t7 ~ t8), then N (N is larger than M and the natural number of more than 3) verifying voltage Vfy (t6 ~ t7 of Figure 11, after t7) is applied successively to selection wordline WL.Then, in any one program cycles, the applying number of times of program voltage is all identical with the applying number of times of verifying voltage, or is less than the applying number of times of verifying voltage, and is no more than the applying number of times of verifying voltage.

Further, in other words, to the write of the data of storage unit by repeatedly carrying out repeatedly program cycles to perform, described program cycles comprise to select wordline WL apply program voltage programing work and to the checking work selecting wordline to apply verifying voltage.In this program cycles of repeatedly repeatedly carrying out, continuous print twice program cycles (t3 ~ t5 of Figure 11 and t5 ~ t6) period, the applying number of times of verifying voltage Vfy is set to constant by row decoder 11, makes the applying number of times (3 times: VPGM1-VPGM3) of the program voltage in second time program cycles (t5 ~ t6 of Figure 11) reduce (twice: VPGM2, VPGM3) than first time program cycles (t3 ~ t5 of Figure 11) simultaneously.

Such as, row decoder 11 applies M program voltage successively to described selection wordline in certain program cycles.When any one program voltage (VPGM1 of Figure 11 and Figure 16) in this M time is applied to and selects wordline WL, undermost first storage unit will be positioned at and be set to programming object, the 3rd storage unit being at least positioned at the superiors will be set to non-programmed object.Further, row decoder 11, in next program cycles, omits and applies described any one program voltage (VPGM1 of Figure 11 and Figure 16) (after the t5 of t5-t6 and Figure 16 of Figure 11) to described selection wordline.This example is the situation of the applying stopping VPGM1 before VPGM3.

On the other hand, when another program voltage (VPGM3 of Figure 11 and Figure 14) in M time is applied to and selects wordline WL, the 3rd storage unit being positioned at the superiors is set to programming object, at least will be positioned at undermost first storage unit and be set to non-programmed object.Further, row decoder 11, in next program cycles, omits the applying (after the t5 of Figure 14) of described any one program voltage (VPGM3 of Figure 11 and Figure 14).This example is the situation of the applying stopping VPGM3 before VPGM1.

Certainly, in next program cycles, also can be the situation of the applying simultaneously stopping multiple program voltage.

In the example in figure 12, in one-time programming circulation, also repeatedly program voltage can be applied.But, in case of fig .12, these program voltages are associated with write level.Therefore, the applying of program voltage reduction and to certain level write complete completely the same.In other words, when stopping the applying of certain program voltage, also stop the applying of certain verifying voltage simultaneously.

In contrast, according to the present embodiment, program voltage not only also associates with the position of storage unit with write level.Therefore, even if stopped the applying of certain program voltage, the applying of verifying voltage is also not necessarily stopped.

2. the second embodiment

Then, the semiconductor storage that the second embodiment relates to is described.In present embodiment, in the method for writing data that above-mentioned first embodiment illustrates, by comprising program voltage VPGM1 in VPGM2, the programming pulse number used can be reduced to 2 in one-time programming circulation.The following describes only the difference with the first embodiment.

2.1 about the write work of data

Use Figure 13 and Figure 14 that the write work of data of the present embodiment is described.Figure 13 is the process flow diagram of wiring method, puts on the sequential chart of the voltage selecting wordline WL when Figure 14 is write.

First, in response to the order of control part 15, row decoder 11 selects arbitrary wordline WL, applies program voltage VPGM and programme (step S20) to data to selection wordline WL.

Now, row decoder 11 applies program voltage VPGM2a and VPGM3 to selection wordline WL successively.Voltage VPGM2a is the program voltage for first module and second unit, has the relation of VPGM2a<VPGM3.In addition, although to be such as VPGM1≤VPGM2a≤VPGM2, VPGM2a be such as in one-time programming can not the first module value of excessively programming.

During row decoder 11 is applied with voltage VPGM2a to selection wordline WL, sensor amplifier module 12 applies 0V to the bit line BL (being BL1 ~ BL5 in the example of figure 9) being connected with first module and second unit.Thus, go here and there in SR at the NAND comprising first module and second unit, select transistor ST1 conducting, data are programmed to first module and second unit.In addition, row decoder 11 applies voltage V1 to the bit line BL (being BL6 in the example of figure 9) being connected with Unit the 3rd.Thus, the programming to Unit the 3rd is prohibited.

By above two steps, be programmed data successively to selecting the first module that is connected of wordline WL and second unit and Unit the 3rd.

Then, control part 15 verifies the data (step S21) of programming to memory cell transistor MT.Step S21 is identical with the step S11 illustrated in the first embodiment.

After step S21, if completed (step S22, yes) the programming of first module and second unit, (step S23 is also completed to the programming of Unit the 3rd, be), then control part 15 is judged as that the programming of the data of the expectation to selection page normally completes, and terminates write work.

If after step S21, (step S22 is completed to the programming of first module and second unit, be), (step S23 is not completed to the programming of Unit the 3rd, no), then control part 15 omits the applying of voltage VPGM2a, and boosts (step S24) to voltage VPGM3, repeatedly carries out the process of step S20 simultaneously.

If after step S21, (step S22 is not completed at least any one the programming of first module and second unit, no), (step S25 is not completed yet to the programming of Unit the 3rd, no), then control part 15 couples of voltage VPGM2a and VPGM3 boost (step S26), repeatedly carry out the process of step S20 simultaneously.If completed (step S25, yes) the programming of Unit the 3rd, then control part 15 omits the applying of voltage VPGM3, and boosts (step S27) to voltage VPGM2a, repeatedly carries out the process of step S20 simultaneously.

The effect of 2.2 present embodiments

According to the present embodiment, use program voltage VPGM2a, carry out the programming to first module and second unit simultaneously.Therefore, in the same manner as the first embodiment, program cycles number of times can be cut down, cut down the kind of program voltage simultaneously, and simplify circuit formation.

3. the 3rd embodiment

Then, the semiconductor storage that the 3rd embodiment relates to is described.In present embodiment, in the method for writing data that above-mentioned first embodiment illustrates, by comprising program voltage VPGM3 in VPGM2, the programming pulse number used can be reduced to 2 in one-time programming circulation.The following describes only the difference with the first embodiment.

3.1 about the write work of data

Use Figure 15 and Figure 16 that the write work of data of the present embodiment is described.Figure 15 is the process flow diagram of wiring method, to the sequential chart of the voltage selecting wordline WL to apply when Figure 16 is write.

First, in response to the order of control part 15, row decoder 11 selects arbitrary wordline WL.Then, row decoder 11 applies program voltage VPGM and by data programing (step S30) to selection wordline WL.

Now, row decoder 11 applies program voltage VPGM1 and VPGM2b to selection wordline WL successively.Voltage VPGM2b is the program voltage for second unit and Unit the 3rd, has the relation of VPGM2b>VPGM1.In addition, such as VPGM2≤VPGM2b≤VPGM3.VPGM2b is such as can not the second unit value of excessively programming in one-time programming.During row decoder 11 is applied with voltage VPGM2b to selection wordline WL, sensor amplifier module 12 applies 0V to the bit line BL (being BL2 ~ BL6 in the example of figure 9) being connected with second unit and Unit the 3rd.Thus, go here and there in SR at the NAND comprising second unit and Unit the 3rd, select transistor ST1 conducting, data are programmed to second unit and Unit the 3rd.In addition, row decoder 11 applies voltage V1 to the bit line BL (being BL1 in the example of figure 9) being connected with first module.Thus, the programming to first module is prohibited.

Then, control part 15 verifies the data (step S31) of programming to memory cell transistor MT.Step S31 is identical with the step S11 illustrated in the first embodiment.

After step S31, if completed (step S32, yes) the programming of first module, (step S33 is also completed to the programming of second unit and Unit the 3rd, be), then control part 15 is judged as that the programming of the data of the expectation to selection page normally completes, and terminates write work.

If after step S31, (step S32 is completed to the programming of first module, be), (step S33 is not completed to the programming of at least one of second unit and Unit the 3rd, no), then control part 15 omits the applying of voltage VPGM1, and boosts (step S34) to voltage VPGM2b, repeatedly carries out the process of step S30 simultaneously.

If after step S31, (step S32 is not completed to the programming of first module, no), (step S35 is not completed yet to the programming of at least one of second unit and Unit the 3rd, no), then control part 15 couples of voltage VPGM1 and VPGM2b boost (step S36), repeatedly carry out the process of step S30 simultaneously.If completed (step S35, yes) the programming of second unit and Unit the 3rd, then control part 15 omits the applying of voltage VPGM2b, and boosts (step S37) to voltage VPGM1, repeatedly carries out the process of step S30 simultaneously.

The effect of 3.2 present embodiments

According to the present embodiment, use program voltage VPGM2b, carry out the programming to second unit and Unit the 3rd simultaneously.Therefore, it is possible to obtain the effect same with the second embodiment.

4. the 4th embodiment

Then, the semiconductor storage that the 4th embodiment relates to is described.In present embodiment, in the method for writing data that above-mentioned first embodiment illustrates, by making when the applying of program voltage VPGM2 the channel potential of first module rise, the applying of VPGM1 can be omitted, and the programming pulse number used in one-time programming circulation is reduced to 2.The following describes only the difference with the first embodiment.

4.1 about the write work of data

Use Figure 17 and Figure 18 that the write work of data of the present embodiment is described.Figure 17 is the process flow diagram of wiring method, and Figure 18 is the sequential chart when programming to the voltage selecting wordline WL and bit line BL to apply.

First, in response to the order of control part 15, row decoder 11 selects arbitrary wordline WL, to selection wordline WL applying program voltage VPGM by data programing (step S40).

Now, row decoder 11 applies program voltage VPGM2 and VPGM3 to selection wordline WL successively.As illustrated in the first embodiment, voltage VPGM2 is to the optimized voltage of the programming of second unit.Do not apply voltage VPGM1.

Figure 19 is the circuit diagram of the memory cell array 10 when applying voltage VPGM2.In the present embodiment, when applying voltage VPGM2, being not only second unit, also performing the programming to first module.Now, sensor amplifier module 12 applies voltage V to the bit line BL (being BL1 in the example of Figure 19) being connected to first module _qPW.Voltage V _qPWthe voltage larger than the voltage putting on the bit line BL (being BL2 ~ BL5 in the example of Figure 19) being connected to second unit, such as V _qPW>0V.In addition, V _qPWalso be the voltage that the selection transistor ST1 that can be applied in voltage VSG by grid transmits.

Therefore, during being applied with voltage VPGM2, first module and second unit have been applied in V respectively at each raceway groove _qPWbe programmed with under the state of 0V.

Process is afterwards identical with the process in the explanation that use Figure 13 of the second embodiment carries out, VPGM2a being replaced with VPGM2.Then, the step S21 ~ S27 of step S41 ~ S47 and Figure 13 of Figure 17 is corresponding.

The effect of 4.2 present embodiments

According to the present embodiment, in the same manner as the second embodiment, program cycles number of times can be cut down, cut down the kind of program voltage simultaneously, and simplify circuit formation.In addition, due to the initial value optimization of program voltage VPGM2 can be made in second unit, so compared with the second embodiment, write high speed can be made.Use Figure 20 that this effect is described.Figure 20 is the chart of the change of the threshold voltage of first module when representing programming and second unit.

As shown in the figure, due to program voltage VPGM2 optimization in the programming of second unit, so the threshold value of second unit rises with the increment (step) (Δ Vth1) expected.But VPGM2 is excessive voltage concerning first module.Therefore, when by VPGM2, in statu quo (at that) is applied to first module, its threshold value rises with the increment (Δ Vth2) larger than the increment expected.Difference according to circumstances, likely causes threshold value in one-time programming to rise too much.

Therefore, in the present embodiment, voltage V is applied to the bit line BL being connected to first module _qPW.That is, by applying voltage V _qPW, reduce the potential difference (PD) between control gate and raceway groove.Thus, control the threshold variation amplitude (reduction amplitude of fluctuation) of first module, make it to rise with the increment of the best (Δ Vth3).

That is, even if omit the applying of VPGM1, not only to second unit, also can perform best programming to first module, the high speed writein to these unit can be carried out.

5. the 5th embodiment

Then, the semiconductor storage that the 5th embodiment relates to is described.Present embodiment relates to formation and the work of the row system peripherals circuit in above-mentioned first embodiment.

5.1 about the formation of row system peripherals circuit

Figure 21 is the block diagram of sensor amplifier module 12 of the present embodiment, computing module 13 and latches data module 14.

As shown in the figure, sensor amplifier module 12 possesses the latch cicuit SDL associated with each bit line BL.In the drawings, " _ the B ", " _ M " and " _ T " of remarks after " SDL " represent respectively each latch cicuit SDL and fin-type construct the undermost unit of 24, the unit in middle layer and the superiors unit corresponding.Signal from control part 15 to each latch cicuit SDL SEL_BOT, SEL_MID and SEL_TOP of such as providing expression corresponding with which unit by.That is, provide SEL_BOT=" H " to latch cicuit SDL_B, provide SEL_MID=" H " to latch cicuit SDL_M, provide SEL_TOP=" H " to latch cicuit SDL_T.In addition, similarly, when reading, be provided for each latch cicuit SDL signal CLAMP_BOT, CLAMP_MID and CLAMP_TOP of controlling bit line pre-charge voltage by layer.That is, provide CLAMP_BOT=" H " to latch cicuit SDL_B, provide CLAMP_MID=" H " to latch cicuit SDL_M, provide CLAMP_TOP=" H " to latch cicuit SDL_T.

Latch cicuit SDL keeps the write data sent from computing module 13 when the write of data.Further, latch cicuit SDL is according to write data, and the bit line BL to correspondence applies predetermined voltage.In addition, bit line BL, when the reading of data, is precharged to the voltage corresponding with signal CLAMP_BOT, CLAMP_MID and CLAMP_TOP by latch cicuit SDL.That is, latch cicuit SDL is when the reading of data, is positioned at which layer according to reading object unit, controls the precharge potential being applied to bit line BL.

Computing module 13 possesses the computing circuit 40 associated with each bit line BL.In addition, computing circuit 40 also receives any one of corresponding signal SEL (SEL_TOP, SEL_MID and SEL_BOT).Further, each computing circuit 40, when the write of data, generates write data by the computing employing data and the corresponding signal SEL provided from latches data module 14.Further, the write data of generation are sent to corresponding latch cicuit SDL.

Latches data module 14 possesses the set (set) of latch cicuit DL0 and DL1, and this set is associated with each bit line BL.When the write of data, everybody of the two bits such as provided from external device (ED)s such as main process equipments via data line DAT remains on latch cicuit DL0 and DL1.Further, these data send computing circuit 13 to.When reading, everybody of two bits read from memory cell transistor MT remains on latch cicuit DL0 and DL1.Further, everybody of two bits, via data line DAT, is exported to external device (ED) by latch cicuit DL0 and DL1.

5.2 about work during write

Then, the work of above-mentioned row system peripherals circuit when using Figure 22 and Figure 23 to illustrate that data write.Figure 22 is the sequential chart of the change of word line voltage when representing write, and Figure 23 is the sequential chart of the change of wordline when representing programming and bit-line voltage.

When writing, first, write data send latch cicuit DL0 and DL1 to.The relation writing the data in data and latch cicuit DL0 and DL1 is as follows.

Data: (DL0, DL1)

" Ep " level (write-not): (1,1)

" A " level: (1,0)

" B " level: (0,0)

" C " level: (0,1)

In addition, the data in latch cicuit SDL have following relation.

SDL=1: write-not unit (BL=V1)

SDL=0: writing unit (BL=0V)

Below, treatment step during write is described in order.

(1) step 1

When transmitting data to latch cicuit DL0 and DL1, each computing circuit 40 performs the data being used for the first programming and arranges (dataset).First programming is only to the programming that first module is carried out.When data are arranged, computing circuit 40 performs following logical operation.That is,

/(DL0&/DL1&SEL_BOT)→SDL

In arithmetic expression, "/" represents reversion, " & " presentation logic with.By this computing, DL0=1 and DL=0, and be only provided with " 0 " at the latch cicuit SDL corresponding with undermost storage unit.Be provided with " 1 " at other latch cicuits SDL.Its result, is not only applied with 0V by the bit line BL of first module of checking to being connected to, and is connected to the bit line BL that second unit, Unit the 3rd, write-not object unit and write complete unit is applied with voltage V1 to other.Further, apply voltage VPGM1 to selection wordline WL, only " A " level data is programmed to first module.

(2) step 2

Then, each computing circuit 40 performs the data setting being used for the second programming.Second programming is only to the programming that second unit carries out.When data are arranged, computing circuit 40 performs following logical operation.That is,

(DL0&DL1)|(DL0&/DL1&SEL_BOT)|(/DL0&DL1&SEL_TOP)→SDL

In arithmetic expression, " | " presentation logic or.By this computing, the latch cicuit SDL corresponding with first module, Unit the 3rd and write-not object unit is provided with " 1 ".In other words, only the latch cicuit SDL corresponding with second unit is provided with " 0 ".Its result, not only being applied with 0V by the bit line BL of the second unit of checking to being connected to, being applied with voltage V1 to other bit lines BL.Further, apply voltage VPGM2 to selection wordline WL, only data are programmed to second unit.

(3) step 3

Then, each computing circuit 40 performs the data setting being used for the 3rd programming.3rd programming is only to the programming that Unit the 3rd carries out.When data are arranged, computing circuit 40 performs following logical operation.That is,

/(/DL0&DL1&SEL_TOP)→SDL

By this computing, DL0=0 and DL=1, and only the latch cicuit SDL corresponding with the storage unit of the superiors is provided with " 0 ".Other latch cicuits SDL is provided with " 1 ".Its result, is not only applied with 0V by the bit line BL of Unit the 3rd of checking to being connected to, and is connected to the bit line BL that first module, second unit, write-not object unit and write complete unit is applied with voltage V1 to other.Further, apply voltage VPGM3 to selection wordline WL, only " C " level data is programmed to Unit the 3rd.

(4) step 4

Then, the checking work to " A " level is performed.That is, under the state selecting wordline WL to be applied with checking level Vfy_A, from memory cell transistor MT sense data.Further, if memory cell transistor MT ends, namely threshold value reaches " A " level, then in latch cicuit SDL, preserve " 1 ".On the other hand, if memory cell transistor MT conducting, namely threshold value does not arrive " A " level, then in latch cicuit SDL, preserve " 0 ".

Then, computing circuit 40 performs following logical operation.That is,

(SDL&DL0&/DL1)|DL1→DL1

In the equation above, (DL0 &/DL1) only becomes " 1 " in the bit line BL of write " A " level.Therefore, (SDL & DL0 &/DL1) is only " A " level and the bit line BL be verified becomes " 1 " for write data.Afterwards, carry out the logical OR computing of this operation result and DL1 originally, and be re-set as DL1.Its result, the data of latch cicuit DL0 and DL1 are as follows.

" Ep " level (write-not): (1,1)

" A " level: (1,0/1)

" B " level: (0,0)

" C " level: (0,1)

That is, by last logical OR computing, the data of not corresponding with " A " level latch cicuit DL0 and DL1 are set to original value.

Then, computing circuit 40 performs the logical operation of following (1) formula.That is,

(DL0&/DL1&SEL_BOT)(1)

Thereby, it is possible to obtain corresponding with " A " level and be positioned at the result of undermost memory cell transistor MT.That is, if this operation result becomes " 0 ", then the known first module corresponding with these row have passed checking.On the other hand, only corresponding with first module and corresponding with the row of authentication failed operation result becomes " 1 ".

Therefore, the figure place that such as control part 15 pairs of operation results become " 1 " counts, if this number below certain reference value (such as, by ECC circuit can error correction figure place determine), be then judged as that first module is verified.In this case, control part 15 issues signal COMP_A_BOT (COMP_A_BOT=" H "), from next program cycles, do not apply voltage VPGM1.

Then, computing circuit 40 performs the logical operation of following (2) formula.That is,

(DL0&/DL1&(SEL_MID|SEL_TOP))(2)

Thereby, it is possible to obtain corresponding with " A " level and be positioned at the result of the memory cell transistor MT of the layer beyond orlop.That is, if this operation result becomes " 0 ", then the known memory cell transistor corresponding with these row have passed checking.On the other hand, only corresponding with " A " level and be arranged in the memory cell transistor MT of the layer beyond orlop, the operation result corresponding with the memory cell transistor MT of authentication failed become " 1 ".

Therefore, the figure place that such as control part 15 pairs of operation results become " 1 " counts, if this number is below certain reference value, is then judged as the layer that is positioned at beyond orlop and the memory cell transistor MT that should write " A " level is verified.

If the result based on above-mentioned (1) formula and (2) formula all becomes pass through, then the programming to whole memory cell transistor MT that should write " A " level completes.Therefore, control part 15 issues signal COMP_A_MIDTOP (COMP_A_MIDTOP=" H ").Further, when control part 15 has issued this two side of signal COMP_A_BOT and COMP_A_MIDTOP, from next program cycles, the checking work of " A " level has not been carried out.

(5) step 5

Then, the checking work to " B " level is performed.That is, under the state being applied with checking level Vfy_B to selection wordline WL, sense data from memory cell transistor MT.Further, if memory cell transistor MT ends, namely threshold value reaches " B " level, then in latch cicuit SDL, preserve " 1 ".On the other hand, if memory cell transistor MT conducting, namely threshold value does not arrive " B " level, then in latch cicuit SDL, preserve " 0 ".

Further, computing circuit 40 performs following logical operation simultaneously.That is,

(SDL&/DL0&/DL1)|DL0→DL0

(SDL&/DL0&/DL1)|DL1→DL1

In the equation above, (/DL0 &/DL1) only becomes " 1 " in the bit line BL of write " B " level.Therefore, (SDL & DL0 &/DL1) is only " B " level and the bit line BL be verified becomes " 1 " for write data.Afterwards, carry out these operation results and carry out logical OR computing with DL0 and DL1 originally, and be re-set as DL0 and DL1.As a result, the data of latch cicuit DL0 and DL1 are as following.

" Ep " level (write-not): (1,1)

" A " level: (1,0/1)

" B " level: (0,0/1)

" C " level: (0,1)

In addition, the value of corresponding with " A " level latch cicuit DL0 is re-set as " 0 " or " 1 " in above-mentioned steps (4).

Then, computing circuit 40 performs the logical operation of following (3) formula.That is,

(/DL0&/DL1)(3)

Known, if this operation result becomes " 0 ", then the memory cell transistor MT that should write " B " level is verified, if become " 1 ", then and authentication failed.

Therefore, the figure place that such as control part 15 pairs of operation results become " 1 " counts, if this number is below certain reference value, is then judged as that " B " level program verification passes through.In this case, control circuit distribution signal COMP_B (COMP_B=" H "), does not carry out the checking work of " B " level from next program cycles.

(6) step 6

Then, the checking work to " C " level is performed.That is, under the state selecting wordline WL to be applied with checking level Vfy_C, from memory cell transistor MT sense data.Further, if memory cell transistor MT ends, namely threshold value reaches " C " level, then in latch cicuit SDL, preserve " 1 ".On the other hand, if memory cell transistor MT conducting, namely threshold value does not arrive " C " level, then in latch cicuit SDL, preserve " 0 ".The work of step 6 is substantially identical with step 4, only reads object data different.

First, computing circuit 40 performs following logical operation.That is,

(SDL&/DL0&DL1)|DL0→DL0

In the equation above, (/DL0 & DL1) only becomes " 1 " in the bit line BL of write " C " level.Therefore, (SDL &/DL0 & DL1) is only " C " level in write data and becomes " 1 " in the bit line BL be verified.Afterwards, carry out the logical OR computing of this operation result and DL0 originally, and be re-set as DL0.Its result, the data of latch cicuit DL0 and DL1 are as follows.

" Ep " level (write-not): (1,1)

" A " level: (1,0/1)

" B " level: (0/1,0/1)

" C " level: (0/1,1).

Then, computing circuit 40 performs the logical operation of following (4) formula.That is,

(/DL0&/DL1&SEL_TOP)(4)

Thereby, it is possible to obtain corresponding with " C " level and be positioned at the result of the memory cell transistor MT (Unit the 3rd) of the superiors.That is, if this operation result becomes " 0 ", then known Unit the 3rd corresponding with these row have passed checking.On the other hand, only corresponding with Unit the 3rd and corresponding with the row of authentication failed operation result becomes " 1 ".

Therefore, the figure place that such as control part 15 pairs of operation results become " 1 " counts, if this number is below certain reference value, is then judged as that Unit the 3rd is verified.In this case, control circuit distribution signal COMP_C_TOP (COMP_C_TOP=" H "), does not apply voltage VPGM3 from next program cycles.

Then, computing circuit 40 performs the logical operation of following (5) formula.That is,

(/DL0&DL1&(SEL_MID|SEL_BOT))(5)

Thereby, it is possible to obtain corresponding with " C " level and be positioned at the result of the memory cell transistor MT of the layer beyond the superiors.That is, if this operation result becomes " 0 ", then the known memory cell transistor corresponding with these row have passed checking.On the other hand, only corresponding with " C " level and be arranged in the memory cell transistor MT of the layer beyond the superiors, the operation result corresponding with the memory cell transistor MT of authentication failed become " 1 ".

Therefore, the figure place that such as control part 15 pairs of operation results become " 1 " counts, if this number is below certain reference value, is then judged as that the memory cell transistor MT being positioned at the layer beyond the superiors is verified.

If the result based on above-mentioned (4) formula and (5) formula becomes pass through, then the programming to whole memory cell transistor MT that should write " C " level completes.Therefore, control part 15 issues signal COMP_C_MIDBOT (COMP_C_MIDBOT=" H ").Further, when control part 15 has issued this two side of signal COMP_C_TOP and COMP_C_MIDBOT, from next program cycles, the checking work of " C " level has not been carried out.

(7) step 7

Control part 15 carries out above work repeatedly, when five control signal COMP_A_BOT, COMP_A_MIDTOP, COMP_B, COMP_C_TOP and COMP_C_MIDTOP all become " H " level, programming normally completes (programming is passed through), and write work is completed.When any one control signal keep the state of " L " level and program cycles count to reach maximal value time, programming is inenough normally to be completed (program fail), and control part 15 makes write work complete.

The effect of 5.3 present embodiments

The wiring method illustrated in the above-described first embodiment such as can by of the present embodiment form realize.In addition, the second to the 4th embodiment is like this too, by employing the computing of control signal SEL_BOT, SEL_MID, SEL_TOP, DL0 and DL1, suitably can control the current potential of bit line BL.

6. the 6th embodiment

Then, the semiconductor storage that the 6th embodiment relates to is described.Present embodiment relates to the storage system of the semiconductor storage 1 of any one possessing the above-mentioned first to the 5th embodiment.

6.1 about the formation of storage system

Figure 24 is the block diagram of storage system of the present embodiment.As shown in the figure, storage system possesses the semiconductor storage 1 illustrated in the first to the 5th embodiment and the controller 2 controlling semiconductor storage 1.

Controller 2, in response to the order from not shown main process equipment, sends the orders such as reading, write and erasing to NAND flash memory 1.In addition, the storage space of NAND flash memory 1 is managed.Controller 2 and NAND flash memory 1 such as also can form same semiconductor device.In addition, storage system 1 also can be a device, as its example, can enumerate SD ^tMblock such storage card, SSD (solidstatedrive: solid state hard disc) etc.In addition, storage system 1 also can be the built-in formation of NAND flash memory 1 and controller 2 in personal computer, as long as be equipped with the application of NAND flash memory 1, does not then limit.

Controller 2 possesses host interface circuit 210, internal memory (RAM) 220, processor (CPU) 230, memory buffer 240, NAND interface circuit 250 and ECC circuit 260.

Host interface circuit 210 is connected with main process equipment via controller bus, and controls the communication with main process equipment.Further, the order and data that receive from main process equipment is transmitted respectively to CPU230 and memory buffer 240.In addition, in response to the order of CPU230, transmit the data in memory buffer 240 to main process equipment.

NAND interface circuit 250 is connected with NAND flash memory 1 via NAND bus, and controls the communication with NAND flash memory 1.Further, transmitting the order received from CPU230 to NAND flash memory 1, in addition, when writing, transmitting the write data in memory buffer 240 to NAND flash memory 1.Further, when reading, transmit the data read from NAND flash memory 1 to memory buffer 240.

CPU230 controls the work of controller 2 entirety.Such as, when receiving write read-out command from main process equipment, in response to this, the write order based on NAND interface is issued.Like this too when reading and wipe.In addition, CPU230 performs the various process for managing NAND flash memory 1 such as wear leveling (wearleveling).Further, CPU230 performs various computing.Such as, the encryption of data and/or randomization etc. are performed.ECC circuit 260 performs error correction (ECC:ErrorCheckingandCorrecting) process of data.That is, ECC circuit 260 is when the write of data based on the parity checking of write data genaration, generating syndrome, detecting mistake and correcting this mistake when reading according to parity checking.In addition, CPU230 also can have the function of ECC circuit 260.

Internal memory 220 is such as the semiconductor memories such as DRAM, and uses as the operating area of CPU230.Further, internal memory 220 is kept for managing the firmware of NAND flash memory 1 and/or various admin tables etc.

6.2 about the work of controller

Then, the work of controller 2 of the present embodiment is described, particularly writes work.Controller 2 can use first mode and these two kinds of write modes of the second pattern, writes data to NAND flash memory 1.

Figure 25 is the sequential chart with the signal received and dispatched between NAND flash memory 1 and controller 2 during first mode write data.Controller 2 sends chip enable (enable, enable) signal/CE, address latch enabling signal ALE to NAND flash memory 1, enabling signal CLE, write-enable signal/WE are latched in order and read enabling signal/RE.In addition, NAND flash memory 1 is to controller 2 readys for sending/busy signal/R/B.Input/output signal I/O1 ~ I/O8 is the data of such as 8 that receive and dispatch between controller 1 and NAND flash memory.

Chip start signal/CE is the signal for starting NAND flash memory 1, and comes into force (assert) by low level.Address latch enabling signal ALE represents that input/output signal I/O1 ~ I/O8 is the signal of address, and utilizes high level to come into force.Order is latched enabling signal CLE and is represented that input/output signal I/O1 ~ I/O8 is the signal of order, and utilizes high level to come into force.Write-enable signal/WE is the signal for writing each data to NAND flash memory 1, and utilizes low level to come into force.Reading enabling signal/RE is the signal for reading each data from NAND flash memory 1, and utilizes low level to come into force.Ready/Busy signal/R/B represents that whether NAND flash memory 1 is the signal of the busy condition state of Received signal strength (whether can), becomes low level when busy condition.

As shown in the figure, controller 1 is when by first mode write data, and 80H is ordered in distribution first write, and is write the not shown command register of NAND flash memory 1.Order 80H is the order for notifying to perform from now on write work.Afterwards, by column address (specifying the address of bit line) and row address (specifying the address of wordline (page)) writing address register.Afterwards, the data D0 ~ D527 that should programme is transmitted.Finally, controller 2 will order 10H to write command register.In response to this order, the control part 15 of NAND flash memory 1 utilizes the method write data illustrated in the first to the 5th embodiment.

Figure 26 is the sequential chart of the signal received and dispatched between NAND flash memory 1 and controller 2 when utilizing the second pattern write data.Be with the difference of first mode: before first writes and order 80H, prefix order (prefixcommand) issued by controller 2, and write command register.By receiving prefix order, NAND flash memory the second pattern write data.The write of the data of the second pattern is utilized to be performed by the method for the Figure 12 illustrated in the first embodiment.

In a second mode, program voltage VPGM performs programming to the whole storage unit at page planted agent write " A " ~ " C " level, and does not classify according to first module ~ Unit the 3rd.That is, as shown in figure 12, VPGM is only merely boosted.In case of fig .12, only to apply the situation of a VPGM for exemplifying in one-time programming circulation, but also more than twice can be applied continuously.But, this VPGM being applied with more than twice not with the position (address) of storage unit, to write data corresponding, but in order to use to whole write object unit programming datas.That is, if the second pattern, then the applying number of times of the VPGM in one-time programming circulation is identical with the applying number of times of verifying voltage, or is less than the applying number of times of verifying voltage.

That is, as illustrated at the first embodiment, when the applying that stopped certain program voltage, also stop the applying of verifying voltage corresponding with it simultaneously.

The effect of 6.3 present embodiments

If formation of the present embodiment, then can change writing speed and power consumption according to the demand of user.

That is, if first mode, then the booster circuit in NAND flash memory 1 produces low-voltage VPGM1 after generating high voltage VPGM3.Therefore, at checking duration of work, need the electric discharge of booster circuit, after discharge, need the boosting work again from low voltage VPGM1.That is, owing to repeatedly carrying out discharge and recharge in booster circuit, so current sinking increases.Instead, as illustrated at the first to the 5th embodiment, write work at a high speed can be carried out.

On the other hand, if the second pattern, then VPGM merely boosts by booster voltage, without the need to the electric discharge in booster voltage, at checking duration of work, voltage wiring is set to unfixed (floating).Therefore, although writing speed is poor compared with first mode, current sinking can be reduced.

And, in the present embodiment, according to the order carrying out self-controller 2, first mode and the second pattern can be switched.Such as, for the NAND flash memory 1 of product export of data (MLC:multi-levelcell) keeping more than two as storage unit, wanting to make it as temporary buffer SLC (single-levelcell: storage unit keeps a data) work, or in order to write under important data want to make it to carry out the situations such as SLC work with high reliability, preferably adopt the second pattern.

Like this, if present embodiment, although although then can switch can the higher pattern of high speed operation power dissipation ratio and tick-over low-power consumption pattern and use NAND flash memory 1.

7. variation etc.

As mentioned above, the semiconductor storage 1 that embodiment relates to possesses multiple storage unit MT, wordline WL, bit line BL and row decoder 11.Storage unit is layered on semiconductor substrate.Wordline WL is connected with the grid of storage unit.Bit line BL is electrically connected with the current path of storage unit, and can transmit data.Row decoder 11 applies voltage to wordline.Write data to storage unit MT to be performed (Figure 11) by the program cycles repeatedly repeatedly comprising programing work and checking work.In one-time programming circulation, described row decoder applies M (M is the natural number of more than 1) program voltage (t5 ~ t6 of Figure 11 successively to selection wordline, t7 ~ t8), then N (N is larger than M and the natural number of more than 2) verifying voltage (t6 ~ t7 of Figure 11, after t7) is applied successively to described selection wordline.

In other words, to storage unit write data by repeatedly carrying out repeatedly program cycles to perform, described program cycles comprises to selecting wordline apply the programing work of program voltage and apply the checking work of verifying voltage.Row decoder 11 is in continuous print twice program cycles (t3 ~ t5 of Figure 11 and t5 ~ t6) period, the applying number of times of verifying voltage is set to constant, makes the applying number of times (3 times: VPGM1-VPGM3) of the program voltage in second time program cycles (t5 ~ t6 of Figure 11) reduce (twice: VPGM2, VPGM3) than first time program cycles (t3 ~ t5 of Figure 11) simultaneously.

By this formation, program cycles number of times can be cut down, and improve the writing speed of data.But embodiment is not limited to the mode of above-mentioned explanation, various distortion can be carried out.Such as, in the above-described embodiment, for VPGM1 and VPGM3 be applied to the applying of VPGM2 before situation about terminating be illustrated, but also can be VPGM2 be applied to the applying of VPGM1 and/or VPGM3 before situation about terminating.

In addition, in the above-described embodiment, first module is defined as is positioned at undermost layer and the unit being programmed to " A " level.But first module also can be the layer that the is positioned at ground floor unit to n-th layer (N is the natural number of more than 2).In addition, storage unit can keep more than 4 data (" Ep ", " A ", " B ", " C ", " D " ... " O " level these 16 values) when, first module also can be programmed unit in the scope of " A " level to such as " C " level.Unit the 3rd is like this too.Namely, Unit the 3rd also can be the layer that is positioned at N+M layer (M is the natural number of more than the 4) unit to L layer (L is the natural number of more than 6), in addition, also can be such as programmed unit in " L " level to the scope of " O " level.

Further, in the above-described first embodiment, be illustrated (VPGM1 ~ VPGM3) for situation programming pulse being categorized as three kinds.But, also can be categorized as more than 4 kinds, in one-time programming circulation, apply this pulse of more than 4 kinds successively.

Further, the concept of above-mentioned 4th embodiment also can be applied to the 3rd embodiment.That is, in the Figure 16 illustrated in the third embodiment, also can apply VPGM3 to replace voltage VPGM2b, apply V to the bit line being connected to second unit simultaneously _qPW.

Further, the structure of memory cell array 10 is not limited at Fig. 2 to formation illustrated in fig. 6.In the above-described embodiment, as shown in Figure 4, be gathered in the left side of memory cell array 10 with the bit line contact BC of odd number string group GR1, the bit line contact BC of even number string group GR2 is gathered in the right side of memory cell array 10 and situation about configuring is that example is illustrated.But these bit line contact BC also all can be gathered in right side or left side and configuring.

Further, above-mentioned embodiment can be applied to the writing speed of data in page and have uneven formation, and be not limited to NAND flash memory, can overall application in memory storage, described page is the set of the storage unit be selected simultaneously when the write of data.

Be explained above several embodiment of the present invention, but these embodiments just proposing as an example, is not be intended to limit scope of invention.These embodiments can be implemented in other various modes, in the scope of main idea not departing from invention, can carry out various omission, replacement and change.These embodiments or its distortion are included in scope of invention or main idea, are comprised in equally in invention described in claims and scope equivalent with it.

Label declaration

10 ... memory cell array, 11 ... row decoder, 12 ... sensor amplifier module, 13 ... computing module, 14 ... latches data module, 15 ... control part, 20 ... semiconductor substrate, 21,22-1 ~ 22-4,25 ~ 27 ... dielectric film, 23-1 ~ 23-3,28 ... semiconductor layer, 24 ... fin-type lit-par-lit structure

Claims

1. a semiconductor storage, is characterized in that, possesses:

Multiple storage unit, it is on a semiconductor substrate stacked;

Wordline, it is connected with the grid of described storage unit;

Bit line, it is electrically connected with the current path of described storage unit, and can transmit data; And

Row decoder, it applies voltage to described wordline,

Write to the data of described storage unit is performed by the program cycles repeatedly repeatedly comprising programing work and checking work,

In one-time programming circulation, described row decoder applies M program voltage successively to selection wordline, and then apply N verifying voltage successively to described selection wordline, wherein, M is the natural number of more than 1, and N is larger than M and the natural number of more than 2.

2. semiconductor storage according to claim 1, is characterized in that,

In once described program cycles, the multiple storage unit be laminated on semiconductor substrate are programmed described data in the lump.

3. semiconductor storage according to claim 2, is characterized in that,

When any one program voltage in described M time is put on described selection wordline, be set to programming object by being positioned at undermost storage unit in described stacked multiple storage unit, the storage unit being at least positioned at the superiors is set to non-programmed object.

4. semiconductor storage according to claim 2, is characterized in that,

When any one program voltage in described M time is put on described selection wordline, the storage unit being positioned at the superiors is set to programming object, is positioned at undermost storage unit to major general and is set to non-programmed object in described stacked multiple storage unit.

5. semiconductor storage according to claim 2, is characterized in that,

When any one program voltage in described M time is put on described selection wordline, the first storage unit and this two side of the second storage unit are set to programming object,

Raceway groove to described first storage unit, described second storage unit provides the first voltage different from each other and the second voltage respectively.

6. a storage system, is characterized in that, possesses:

Semiconductor storage according to claim 1; With

Control the controller of described semiconductor storage,

Described semiconductor storage possesses the first write mode and the second write mode,

In described first write mode, in any one program cycles, described row decoder applies M program voltage successively to selection wordline, then applies N verifying voltage successively to described selection wordline,

In described second write mode, in any one program cycles, the applying number of times of verifying voltage is all identical with the applying number of times of described program voltage or be all less than the applying number of times of described program voltage.

7. the method for writing data of the semiconductor storage of multiple storage unit that a method for writing data has been stacked on a semiconductor substrate, is characterized in that, comprising:

Apply M program voltage successively to selection wordline, wherein, M is the natural number of more than 1; With

After the described program voltage of applying, apply N verifying voltage successively to described selection wordline, wherein, N is larger than M and the natural number of more than 2.

8. method for writing data according to claim 7, is characterized in that,

By applying M described program voltage and applying N described verifying voltage, in the lump data are write to the multiple storage unit be laminated on semiconductor substrate.

9. method for writing data according to claim 8, is characterized in that,

When any one program voltage in described M time is put on described selection wordline, be set to programming object by being positioned at undermost storage unit in described stacked multiple storage unit, the storage unit being positioned at the superiors to major general is set to non-programmed object.

10. method for writing data according to claim 8, is characterized in that,

11. 1 kinds of semiconductor storages, is characterized in that possessing:

Multiple storage unit, it is on a semiconductor substrate stacked;

Wordline, it is connected with the grid of described storage unit;

Row decoder, it applies voltage to described wordline,

To the write of the data of described storage unit by repeatedly carrying out repeatedly program cycles to perform, described program cycles comprises to selecting wordline apply the programing work of program voltage and apply the checking work of verifying voltage to described selection wordline,

Described row decoder is between continuous print twice program cycles, the applying number of times of described verifying voltage is set to constant, and the applying number of times of the described program voltage in the applying number of times ratio first time program cycles of the described program voltage in second time program cycles is reduced.

12. semiconductor storages according to claim 11, is characterized in that,

In one-time programming circulation, the multiple storage unit be laminated on described semiconductor substrate are programmed described data in the lump.

13. semiconductor storages according to claim 12, is characterized in that,

Described row decoder applies M described program voltage successively to described selection wordline in described first time program cycles,

When any one program voltage in described M time is put on described selection wordline, be set to programming object by being positioned at undermost storage unit in described stacked multiple storage unit, the storage unit being positioned at the superiors to major general is set to non-programmed object,

In described second time program cycles, omit and apply any one program voltage described to described selection wordline.

14. semiconductor storages according to claim 12, is characterized in that,

When any one program voltage in described M time is put on described selection wordline, the storage unit being positioned at the superiors is set to programming object, is positioned at undermost storage unit to major general and is set to non-programmed object in described stacked multiple storage unit,

15. semiconductor storages according to claim 12, is characterized in that,

Raceway groove to described first storage unit, the second storage unit provides the first and second voltages different from each other respectively.

16. semiconductor storages according to claim 5 or 15, is characterized in that,

Described first storage unit is positioned at undermost storage unit,

Described in described first voltage ratio, the second voltage is high.

17. 1 kinds of storage systems, is characterized in that possessing:

Semiconductor storage according to claim 11; With

Control the controller of described semiconductor storage,

In described first write mode, described row decoder is between continuous print twice program cycles, the applying number of times of described verifying voltage is set to constant, and the applying number of times of the described program voltage in the applying number of times ratio first time program cycles of the described program voltage in second time program cycles is reduced

In described second write mode, described row decoder, in continuous print twice program cycles, when making the applying number of times of described program voltage decrease, also makes the applying number of times of described verifying voltage reduce.

18. storage systems according to claim 6 or 17, is characterized in that,

According to the order provided from described controller, described semiconductor storage with described first write mode, the second write mode any one carry out work.

The method for writing data of the semiconductor storage of multiple storage unit that 19. 1 kinds of method for writing data have been stacked on a semiconductor substrate, is characterized in that, comprising:

Apply M program voltage successively to selection wordline, then apply N verifying voltage successively to described selection wordline, perform the first program cycles thus, wherein M is the natural number of more than 2, and N is the natural number of more than 2;

Apply L program voltage successively to described selection wordline, then apply N verifying voltage successively to described selection wordline, perform the second program cycles thus, wherein L be more than 1 natural number and L<M.

20. method for writing data according to claim 19, is characterized in that,

By described first program cycles and described second program cycles, in the lump data are write to the multiple storage unit be layered on described semiconductor substrate.

21. method for writing data according to claim 20, is characterized in that,

When any one program voltage in described M time of described first program cycles is put on described selection wordline, programming object is set to by being positioned at undermost storage unit in described stacked multiple storage unit, the storage unit being positioned at the superiors to major general is set to non-programmed object

In described second program cycles, eliminate and apply any one program voltage described to described selection wordline.

22. method for writing data according to claim 20, is characterized in that,

When any one program voltage in described M time of described first program cycles is put on described selection wordline, the storage unit being positioned at the superiors in described stacked multiple storage unit is set to programming object, be positioned at undermost storage unit to major general and be set to non-programmed object

23. method for writing data according to claim 7 or 20, is characterized in that,

24. method for writing data according to claim 23, is characterized in that,

Described first storage unit is positioned at undermost storage unit,

Described in described first voltage ratio, the second voltage is high.