CN105515348B - One kind realizes phase locked method in frequency converter synchronous modulation - Google Patents

Abstract

One kind realizes phase locked method in frequency converter synchronous modulation, belongs to the control field of big-power transducer.Step includes：The preferable setting link of Phase synchronization algorithm, the comparing element of actual phase angle signal link, actual phase angle signal and 15 ° of desired angle signals is obtained to sample point signal transacting in each cycle；Ratio controlling unit is done according to angular deviation signal, amplitude limit is done to counter revise signal and rounds link, superposition revise signal generation actual counter signal link, by counter revise signal and preferable counter signals N₀Superposition, generates actual counter signals.Realize Phase synchronization in synchronous modulation, it is ensured that frequency converter output voltage, current waveform are more symmetrical, and harmonic wave is smaller.

Description

One kind realizes phase locked method in frequency converter synchronous modulation

Technical field

The invention belongs to the control technology field of big-power transducer, in particular, provides one kind and realizes the same step of frequency converter Phase locked method in system.Realize Phase synchronization in synchronous modulation, it is ensured that frequency converter output voltage, current waveform are more Symmetrically, harmonic wave is smaller.

Background technology

In big-power transducer, particularly in heavy-duty rectifier, because power is big, the loss of power device is very big, So carrier frequency is than relatively low, it is general to send out method of the ripple using synchronous modulation.

In order that the voltage current waveform of output is symmetrical, harmonic wave is small, and general carrier frequency is 3 integral multiple.With high-power Exemplified by rectifier, power network fundamental frequency is 50Hz, and carrier frequency elects 600Hz, carrier wave ratio 12 as.Carrier frequency is 3 integer Times, output waveform is symmetrical.Under ideal conditions, ripple mode is sent out using SVPWM, there are 12 samplings in each 360 ° of sampling period Point, every 30 ° of points.If the vector initial angle of SVPWM outputs is 0 °, 12 vectors of output are 0 ° successively, 30 °, 60 °, 90 °, 120 °, 150 °, 180 °, 210 °, 240 °, 270 °, 300 °, 330 °, if phase keeps constant, in each cycle The vector angle of output is all constant, is all this 12 vector angles.

In the controls in order that waveform symmetry, it is intended that the vector angle of each cycle output is identical, that is, reaches Phase synchronization, but there are some reasons to prevent phase from synchronous, the vector angle of output constantly changes.First reason is power network Harmonic wave, interference etc. can be mutated vector angle, be exported by 30 ° of vectors, such as previous vector angle is 30 °, and Current vector becomes for 120 °, and big saltus step occurs.The cycle of Another reason carrier wave is 1.666mS, the control system of frequency converter System is controlled with microprocessors such as DSP, and the output of carrier wave is exported by the way of timer timing.Due to determining for microprocessor When limited precision, the carrier frequency of output is not just 600HZ, for example, 598Hz, and phase shift is all in a primitive period 1 ° or smaller is not reached, but this error is constantly accumulated, and is caused phase constantly to be moved toward a direction, can not be done To Phase synchronization.And control system wishes, in each primitive period, all in identical approximate angle, to have error, but error is not It can accumulate, reach Phase synchronization.

To solve problem above, it is proposed that in a kind of synchronous modulation, reach phase locked method, even if due to harmonic wave etc. After reason causes SPA sudden phase anomalies, original default initial phase can be also gradually returned to by control.

The content of the invention

It is an object of the invention to propose that one kind realizes phase locked method in frequency converter synchronous modulation, applied to NPC During the synchronous modulation of type three-level converter control system, Phase synchronization is realized.Using this method, it is ensured that output Voltage current waveform is symmetrical, makes harmonic content smaller, and can realize the grab sampling in a cycle, avoids because of DSP The precision limitation of timer, caused error accumulation, makes error increasing.

The present invention value of each period vernier counter, is come by introducing a P adjuster in SVPWM synchronous modulations Realize Phase synchronization in synchronous modulation, it is ensured that frequency converter output voltage, current waveform are more symmetrical, and harmonic wave is smaller.Specifically Comprise the following steps：

(1), the preferable setting link of Phase synchronization algorithm

By selecting the initial samples phase angle in each cycle, obtain 6 sector numbers and determine, the sampling phase that position is fixed Angle, the Phase synchronization phase angle formed in ideal；

(2) actual phase angle signal link, is obtained to sample point signal transacting in each cycle

By the angle values and 30 ° of modulus the obtained sample point, it is converted near 15 ° of the first sector, obtains Actual phase angle signal；

(3), the comparing element of actual phase angle signal and 15 ° of desired angle signals

Actual phase angle signal is subtracted by 15 ° of preferable phase angle signals, obtains phase angle deviation signal；

(4) ratio controlling unit, is done according to angular deviation signal

By the size (2≤p≤4) of the proportional controller of reasonable set angular deviation signal, phase angle amendment can be set Speed；

(5) amplitude limit, is done to counter revise signal and rounds link

Output signal by contrasting csr controller is done amplitude limit and rounded, and obtains only -1,0 ,+1 counter amendment of grade three Signal；

(6), it is superimposed revise signal generation actual counter signal link

By counter revise signal and preferable counter signals N₀Superposition, generates actual counter signals.

600Hz carrier frequency, there are 12 sampled points within each cycle.If first sampled point is set to 15 °, connect down The each sampled point come adds 30 ° point by point, then can be scaled to the sampled point of each sector (with 30 ° of modulus) by conversion 15 ° or so of first sector.If it is 15 ° of (θ in sampled point₀) when counter as standard value N₀.Then, every The angle that each sample point in the individual cycle is calculated is scaled to 15 ° of the first sector nearby (error being present), is designated as θ_f.This When, θ₀With θ_fDo deviation and obtain Δ θ, by being handled Δ θ to N₀Correct, obtain revised rolling counters forward letter Number N.

In the synchronous modulation algorithm of frequency converter, in order that the voltage current waveform of output is symmetrical, harmonic wave is small, general carrier wave Frequency is 3 integral multiple, by taking 600Hz as an example.So the sampling period is：That is T_sInherently there is rounding-off to miss Difference.Because SVPWM modulation is using seven segmentations hair ripple mode, i.e. T_sAlso to divide 7 sections of t₁~t₇, ripple is sent out by Timer Controlling paragraph by paragraph. There is the rounding error of time again equally when dividing 7 time.Meanwhile the precision problem of timer in itself is considered further that, In the presence of this system accuracy error.Do not processed if let alone, these time errors can be with the operation of control system, gradually It is cumulative, it will be unable to keep the phase of reference vector to be fixed on specific phase angle within each sampling period, i.e., can not realize Phase synchronization.

In this way, each sampled point in each cycle is modified to the phase angle signal being calculated, you can to ensure Each sampled point in each cycle can sample in specific phase angle, so as to realize phase angle synchronization.

Brief description of the drawings

Fig. 1 is the simple double closed-loop control system figure of NPC type three-level converter rectification sides, wherein, input to PWM hair ripples The reference voltage vector amplitude of moduleAnd phase angleIt is by the current inner loop of rectification side given (being realized by dsp software)；

Fig. 2 be fundamental frequency be 50Hz, carrier frequency is when being 600Hz, using a week of the Phase synchronization modulator approach 12 sampled points (initial samples point is 15 °) figure in phase.

Fig. 3 is the counting to counter by the angular deviation of each sample point (being transformed into first quartile to handle) Number N₀It is modified figure.

Embodiment

Fig. 1~Fig. 3 is a kind of embodiment of the present invention.

As shown in figure 1, inside the two close cycles loop of rectification side, outer voltage is responsible for maintaining the DC bus-bar voltage of output It is maintained at set-point.Current inner loop is responsible for calculating the amplitude and phase angle of reference voltage vector, and exports and send out ripple module to SVPWM, Produce 12 road pwm signals.

In fig. 2, be the carrier frequency 600Hz using fundamental frequency as 50Hz, initial samples o'clock in the case of 15 ° 12 Phase Angle Position of the individual sampled point in 6 sectors.This phase angle is the position in the case of preferable Phase synchronization, it is contemplated that often Under cycle each sampled point, the calculation error of caused fixation and the trueness error of counter, if not doing Phase synchronization processing, this A little preferably phase angles can gradual rotation offset, with accumulated time, offset can be increasing, will be unable to holding Phase synchronization, draws Enter harmonic wave.

By introducing Phase synchronization processing method in figure 3, in each sample point, sampling angle and 30 ° of modulus, change Calculate to the first sector, then compare with 15 ° of preferable phase angles, obtain phase angle deviation signal Δ θ.Phase angle deviation delta θ controls through a P Device, it is input to an amplitude limit and rounds link, form counter revise signal Δ N.The revise signal takes according to phase angle deviation delta θ's Value is different, after amplitude limit rounds, can only value -1,0 ,+1 three value.

Δ N revise signals and standard counter counter value signal N₀Superposition, form actual counter signal.So as to ensure that Caused actual counter signal is corrected in each sample point, without with error accumulation, it is achieved that The Phase synchronization of each sample point of each cycle.

Claims (1)

1. one kind realizes phase locked method in frequency converter synchronous modulation, it is characterised in that by SVPWM synchronous modulations Introduce a P adjuster, the value of each period vernier counter, to realize Phase synchronization in synchronous modulation；Specifically include as follows Step：

(1), the preferable setting link of Phase synchronization algorithm

By selecting the initial samples phase angle in each cycle, the sampling phase angle that 6 sector numbers determinations, positions are fixed, shape are obtained Into the Phase synchronization phase angle in ideal；

(2) actual phase angle signal link, is obtained to sample point signal transacting in each cycle

By the angle values and 30 ° of modulus the obtained sample point, it is converted near 15 ° of the first sector, obtains reality Phase angle signal；

(3), the comparing element of actual phase angle signal and 15 ° of desired angle signals

Actual phase angle signal is subtracted by 15 ° of preferable phase angle signals, obtains phase angle deviation signal；

(4) ratio controlling unit, is done according to angular deviation signal

Pass through size 2≤p≤4 of the proportional controller of set angle deviation signal, the speed of setting phase angle amendment；

(5) amplitude limit, is done to counter revise signal and rounds link

Output signal by contrasting csr controller is done amplitude limit and rounded, and obtains only -1,0 ,+1 three counter revise signal；

(6), it is superimposed revise signal generation actual counter signal link

By counter revise signal and preferable counter signals N₀Superposition, generates actual counter signals.