CN105512075B

CN105512075B - Speedy carding process, input interface circuit and data transmission method

Info

Publication number: CN105512075B
Application number: CN201510870041.0A
Authority: CN
Inventors: 向声宁
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2015-12-01
Filing date: 2015-12-01
Publication date: 2018-09-07
Anticipated expiration: 2035-12-01
Also published as: CN105512075A

Abstract

A kind of speedy carding process of offer of the embodiment of the present invention, input interface circuit and data transmission method, the speedy carding process, input interface circuit are arranged in high speed input/output interface, the speedy carding process, input interface circuit are applied to rapidly input the protocol stack of output transmission, and protocol stack includes link layer, logical layer, transport layer and physical layer.Link layer circuit in speedy carding process interface circuit encapsulates link layer information into data, and package module further encapsulates data, and the message that encapsulation is completed is sent to receiving terminal by speedy carding process interface；High speed input interface in high speed input interface circuit receives the message that transmitting terminal is sent, decapsulation module decapsulates the message, and link layer circuit decapsulates the message into downlink layer, obtains link layer information, the recombination that message is carried out according to link layer information, obtains complete data packet.This embodiment reduces the software overheads of data packet receiving terminal and transmitting terminal, improve the treatment effeciency of processor.

Description

Speedy carding process, input interface circuit and data transmission method

Technical field

The present embodiments relate to a kind of communication technology more particularly to speedy carding process, input interface circuit and data transmissions Method.

Background technology

High speed input and output agreement (hereinafter referred to as RapidIO) is a kind of high-performance, low pin count, is based on packet-switching Interconnection architecture, be a kind of open system interconnection designed to meet the present and following high performance embedded system demand Technical standard.RapidIO is mainly used in embedded system intraconnection, supports chip to chip, plate to the communication between plate, can Slave board for embedded device connects.

In the prior art, the messaging mode for being typically based on RapidIO carries out data transmission.The message of RapidIO The message maximum of transfer mode supports the transmission of 4KB (kilobit), if the data that a data are surrounded by big flow need to transmit, Processor first, as central processing unit (CPU) needs the granularity for calling the software stored in memory by data packet according to 4KB It is split, obtains multiple messages, the domain mark (ID) field configuration that then will belong to the message of the same data packet is identical Ident value, and by multiple messages form a chained list, be configured in messaging controller.Messaging controller is according to chained list by suitable Sequence sends each message successively by high speed input/output interface.It is stored in receiving terminal, processor calling memory soft Part distinguishes processing, to the message with like-identified value using the reception mode of chained list, and according to the ident value in message It is managed using same chained list, is one by the Packet reassembling after fractionation after receiving whole messages split by data packet A data packet.

However, messaging mode in the prior art, due to needing to be carried out to data packet by processor runs software It splits and recombinates, the software overhead of receiving terminal and transmitting terminal is big, causes processor treatment effeciency low.

Invention content

A kind of speedy carding process of offer of the embodiment of the present invention, input interface circuit and data transmission method, need not pass through place Reason device runs software is split and is recombinated to data packet, and the software overhead of data packet receiving terminal and transmitting terminal is reduced, and is improved The treatment effeciency of processor.

In a first aspect, the embodiment of the present invention provides a kind of speedy carding process interface circuit, the speedy carding process interface circuit is set It sets in high speed input/output interface, the speedy carding process interface circuit is applied to rapidly input the protocol stack of output transmission, institute It includes link layer, logical layer, transport layer and physical layer to state protocol stack；The speedy carding process interface circuit includes：Link layer electricity Road, package module and speedy carding process interface, wherein the package module is defeated with the link layer circuit, the high speed respectively Outgoing interface connects；

The link layer circuit, the number to be sent for obtaining the processor configuration except speedy carding process interface circuit According to packet, link layer packaging is carried out to the partial data in the data packet to be sent, obtains including the data and link The message of layer information, and the message is sent to package module, the link layer information includes the corresponding report of the data packet The mark of sequence number in sequence of message of literary sum, the message, the corresponding data packet of the message；

The package module, the message sent for receiving the link layer circuit, carries out the message successively Logical layer, transport layer and physical layer encapsulation, the message for obtaining completing the message of encapsulation, and completion being encapsulated send supreme Fast output interface；

The speedy carding process interface, the message for receiving the completion encapsulation that the package module is sent, will complete The message of encapsulation is sent to receiving terminal.

In the present embodiment, processor only needs to configure data packet to be sent, and link layer circuit can be to the data Packet is split, and during fractionation, link layer information is encapsulated into data, so that receiving terminal can be believed according to link layer Breath recombinates data packet, is then further encapsulated by package module, and speedy carding process interface will directly complete the data of encapsulation It is sent to receiving terminal, data packet need not be split by processor runs software, reduce the expense of software, Bu Huiying Ring the treatment effeciency of general processor.

Further, the speedy carding process interface circuit further includes：Software interface and chained list module, the software interface It is connect with the chained list module, the chained list module is connect with the link layer circuit；

The software interface, the descriptor for obtaining processor configuration, and the descriptor is sent to described Chained list module, the descriptor include the memory address of the data packet and the mark of the receiving terminal；

The chained list module, the descriptor sent for receiving the software interface, and the descriptor is added to and is appointed It is engaged in table, in the speedy carding process interface free time, the descriptor in the task list is sent to the link layer circuit；

The link layer circuit is specifically used for, and the descriptor that the chained list module is sent is received, according to the data The memory address of packet obtains the data packet to be sent of the processor configuration, in the data packet to be sent from memory Data carry out link layer packaging, obtain include the data and link layer information message, and by the message and institute The mark for stating receiving terminal is sent to package module；

The package module is additionally operable to, and receives the mark for the receiving terminal that the link layer circuit is sent, and will be described The mark of receiving terminal is sent to the speedy carding process interface；

The speedy carding process interface is specifically used for, receive the completion encapsulation that the package module is sent the message and The message for completing encapsulation is sent to receiving terminal by the mark of the receiving terminal according to the mark of the receiving terminal.

Further, further include the size of the data packet in the descriptor, the link layer circuit is additionally operable to, root According to the mark of other data packets, the mark of the data packet different from the mark of other data packets is generated；According to the data The size of the size of packet and the data obtains the message total, according to reading of the data in the data packet Sequentially, sequence number of the message in sequence of message is determined；According to the message total, the message in sequence of message The mark of sequence number and the data packet generates the link layer information.

The present embodiment obtains the descriptor that processor is configured according to data packet by software interface, and chained list module is according to high speed The idle state of output interface sends the corresponding descriptor of data packet for not being sent to receiving terminal, link layer to link layer module Link layer packaging of the module to data so that the transmission of data packet is determined by the state of speedy carding process interface so that the hair of message It send and is not limited by identification field, available bandwidth is utilized to greatest extent.Package module is to the further encapsulation of data and height The message that encapsulation is completed is sent to receiving terminal by fast output interface, need not be by processor runs software to sent data Packet is split in advance, as long as reading data in the packet, after data progress link layer packaging, you can by the data It sends, reduces the expense of software, do not interfere with the treatment effeciency of processor.

The embodiment of the present invention also provides a kind of communication equipment, including speedy carding process interface circuit as described above and processing Device, memory；

The memory includes drive software；

The processor, for from the memory read the drive software and under the driving of the drive software to The speedy carding process interface circuit provides data packet to be sent.

Second aspect, the present invention provide a kind of high speed input interface circuit, and the high speed input interface circuit is arranged in height In fast input/output interface, the high speed input interface circuit is applied to rapidly input the protocol stack of output transmission, the agreement Stack includes link layer, logical layer, transport layer and physical layer；The high speed input interface circuit includes：High speed input interface, solution Package module and link layer circuit, wherein the decapsulation module respectively with the high speed input interface and the link Layer circuit connection；

The high speed input interface, the message for receiving transmitting terminal transmission, and the message is sent to the deblocking Die-filling piece；

The decapsulation module, the message sent for receiving the high speed input interface, carries out the message successively The decapsulation of physical layer, transport layer and logical layer, obtain include link layer information message, and will described include that link layer is believed The message of breath is sent to the link layer circuit, and the link layer information includes message total, the message in sequence of message Sequence number, the corresponding data packet of the message mark；

The link layer circuit, the message for including link layer information sent for receiving the decapsulation module, The message including link layer information is decapsulated into downlink layer, is obtained in the link layer information and the message Data, according to the identifying of the data packet, the sequence number of the message total and the message in sequence of message, to described Data in message and the data in other messages are recombinated to obtain the corresponding data packet of the message.

The present embodiment by high speed input interface circuit receive transmitting terminal send message, decapsulation module to the message according to The secondary decapsulation for carrying out physical layer, transport layer and logical layer, link layer circuit carry out the recombination of message according to link layer information, Complete data packet is obtained, message need not be recombinated by processor runs software, reduce the expense of software, it will not Influence the treatment effeciency of general processor.

Further, the link layer circuit is specifically used for,

The message for including link layer information that the decapsulation module is sent is received, to described including link layer information Message into downlink layer decapsulate, obtain the link layer information and the data；

The matched list item of mark existed with the data packet is determined in recombinating table, the list item includes the data Mark, cache information and the message total of packet, the cache information include initial position and the size of link layer buffer area, with And initial position and the size of data buffer area；

According to sequence number of the message in sequence of message and the cache information, the data in the message are deposited In storage to the data buffer storage, the link layer information of the corresponding first message of the data packet is stored to the link layer and is cached In.

According to the mark of the data packet, message total, determine whether data packet corresponding with the message recombinates success.

Further, the high speed input interface circuit further includes：Software interface and cached configuration module；It is described slow Configuration module is deposited to connect with the software interface and the link layer circuit respectively；

The software interface, the caching letter for obtaining the processor configuration except the high speed input interface circuit Breath, the cached configuration module is sent to by the cache information；

The cached configuration module, the cache information sent for receiving the software interface, believes the caching Breath is stored, and sends the cache information to the link layer circuit.

The present embodiment obtains the cache information of the processor configuration except high speed input interface circuit by software interface, will Cache information is sent to cached configuration module, and cached configuration module stores the cache information, and the cache information is sent out It send to link layer circuit.Link layer circuit decapsulates message into downlink layer, obtains link layer information, corresponding according to message The mark of data packet, in recombinating table determine exist and the matched list item of package identification, according in list item cache information and Sequence number of the message in sequence of message, the data in message are stored into data buffer storage, and the link layer of first message is believed Breath is stored into link layer caching, is directly recombinated while storing data, need not pass through processor runs software Message is recombinated, the expense of software is reduced, does not interfere with the treatment effeciency of processor.

The embodiment of the present invention also provides a kind of communication equipment, including high speed input interface circuit as described above and processing Device, memory；

The memory includes drive software；

The processor, for from the memory read the drive software and under the driving of the drive software from The high speed input interface circuit receives the data packet after recombination.

The third aspect, the present invention provide a kind of transmission side data carried out data transmission using speedy carding process interface circuit Method, the speedy carding process interface circuit are arranged in high speed input/output interface, and the speedy carding process interface circuit is applied to fast The protocol stack of fast input and output transmission, the protocol stack includes link layer, logical layer, transport layer and physical layer；The high speed Output interface circuit includes：Link layer circuit, package module and speedy carding process interface, the method includes：

The number to be sent of the processor being located at except speedy carding process interface circuit configuration is obtained by the link layer circuit According to packet, link layer packaging is carried out to the partial data in the data packet to be sent, obtains including the data and link The message of layer information, and the message is sent to package module, the link layer information includes the corresponding report of the data packet The mark of sequence number in sequence of message of literary sum, the message, the corresponding data packet of the message；

The message that the link layer circuit is sent is received by the package module, the message is patrolled successively Layer, transport layer and physical layer encapsulation are collected, obtains the message for completing encapsulation, and the message for completing to encapsulate is sent to high speed Output interface；

By the message for the completion encapsulation that package module described in the speedy carding process interface is sent, will complete to seal The message of dress is sent to receiving terminal.

Further, the speedy carding process interface circuit further includes：Software interface and chained list module,

Before receiving the message that the link layer circuit is sent by the package module, further include：

The descriptor of the processor configuration is obtained by the software interface, and the descriptor is sent to the chain Table module, the descriptor include the memory address of the data packet and the mark of the receiving terminal；

The descriptor that the software interface is sent is received by the chained list module, and the descriptor is added to task In table, in the speedy carding process interface free time, the descriptor in the task list is sent to the link layer circuit；

The descriptor that the chained list module is sent is received by the link layer circuit；

It is described that the pending of the processor being located at except speedy carding process interface circuit configuration is obtained by the link layer circuit Data packet is sent, including：

By the link layer circuit, according to the memory address of the data packet, the processor is obtained from memory and is matched The data packet to be sent set；

It is described the message is sent to the package module to include：The mark of the message and the receiving terminal is sent out It send to the package module；

The method further includes：The mark for the receiving terminal that the link layer circuit is sent is received by the package module Know, and the mark of the receiving terminal is sent to the speedy carding process interface；

The message of the completion encapsulation sent by package module described in the speedy carding process interface, will be complete It is sent to receiving terminal at the message of encapsulation, including：

Pass through the message and described for the completion encapsulation that package module described in the speedy carding process interface is sent The message for completing encapsulation is sent to receiving terminal by the mark of receiving terminal according to the mark of the receiving terminal.

Further, further include the size of the data packet in the descriptor, the method further includes：

By the link layer circuit according to the mark of other data packets, generate different from the mark of other data packets Data packet mark；

By the link layer circuit according to the size of the data packet and the size of the data, the message is obtained Sum；

Reading order by the link layer circuit according to the data in the data packet determines that the message exists Sequence number in sequence of message；

By the link layer circuit according to sequence number in sequence of message of the message total, the message and institute The mark for stating data packet generates the link layer information.

Data transmission method provided in this embodiment is carried out data transmission using speedy carding process interface circuit, is realized former Reason and technique effect are similar with the implementing principle and technical effect of speedy carding process interface circuit, and details are not described herein again for the present embodiment.

Fourth aspect, the present invention provide a kind of transmission side data carried out data transmission using high speed input interface circuit Method, the high speed input interface circuit are arranged in high speed input/output interface, and the high speed input interface circuit is applied to fast The protocol stack of fast input and output transmission, the protocol stack includes link layer, logical layer, transport layer and physical layer；The high speed Input interface circuit includes：High speed input interface, decapsulation module and link layer circuit, the method includes：

The message that transmitting terminal is sent is received by the high speed input interface, and the message is sent to the decapsulation Module；

The message that the high speed input interface is sent is received by the decapsulation module, object is carried out successively to the message The decapsulation for managing layer, transport layer and logical layer, obtain include link layer information message, and will be described including link layer information Message be sent to the link layer circuit, the link layer information includes message total, the message in sequence of message The mark of sequence number, the corresponding data packet of the message；

The message for including link layer information described in the decapsulation module transmission is received by the link layer circuit, it is right The message including link layer information is decapsulated into downlink layer, obtains the number in the link layer information and the message According to according to the identifying of the data packet, the sequence number of the message total and the message in sequence of message, to the report Data in text and the data in other messages are recombinated to obtain the corresponding data packet of the message.

Further, it is described by link layer circuit according to the identifying of the data packet, the message total and described Sequence number of the message in sequence of message is recombinated to obtain described to the data in the message and the data in other messages The corresponding data packet of message, including：

The matched list item of mark existed with the data packet is determined in recombinating table by the link layer circuit, it is described List item includes mark, cache information and the message total of the data packet, and the cache information includes link layer buffer area Initial position and size and data buffer area initial position and size；

It, will by the link layer circuit according to sequence number of the message in sequence of message and the cache information Data in the message are stored into the data buffer storage, and the link layer information of the corresponding first message of the data packet is deposited During storage is cached to the link layer.

Mark, message total by the link layer circuit according to the data packet, determination are corresponding with the message Whether data packet recombinates success.

Further, the high speed input interface circuit further includes：Software interface and cached configuration module；The side Method further includes：

The caching letter of the configuration of the processor except the high speed input interface circuit is obtained by the software interface Breath, the cached configuration module is sent to by the cache information；

The cache information that the software interface is sent is received by the cached configuration module, to the cache information It is stored, and the cache information is sent to the link layer circuit.

Data transmission method provided in this embodiment is carried out data transmission using high speed input interface circuit, is realized former Reason and technique effect are similar with the implementing principle and technical effect of high speed input interface circuit, and details are not described herein again for the present embodiment.

Description of the drawings

In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is this hair Some bright embodiments for those of ordinary skill in the art without having to pay creative labor, can be with Obtain other attached drawings according to these attached drawings.

Fig. 1 shows the application schematic diagram of RapidIO interconnection in embedded systems；

Fig. 2 is the structural schematic diagram for the protocol stack that the present invention rapidly inputs output transmission；

Fig. 3 is the structural schematic diagram of speedy carding process of the present invention, input interface circuit；

Fig. 4 is the form schematic diagram of link layer；

Fig. 5 is the form schematic diagram of descriptor；

Fig. 6 is recombination tableau format schematic diagram；

Fig. 7 is the storage schematic diagram of link layer information and data packet；

Fig. 8 is the flow diagram of data transmission method embodiment one of the present invention；

Fig. 9 is the flow diagram of data transmission method embodiment two of the present invention.

Specific implementation mode

In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art The every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.

The present embodiment provides a kind of speedy carding process, input interface circuit and data transmission methods.The speedy carding process, input connect Mouth circuit and data transmission method can be based on RapidIO protocol realizations.Speedy carding process provided in this embodiment, input interface electricity Road and data transmission method are mainly used in embedded system intraconnection, support chip to chip, board to leading between board Letter.Transmitting terminal in this example can be chip or board etc. in embedded system inside, and receiving terminal may be embedded Chip or board in internal system etc..Speedy carding process interface circuit is located at transmitting terminal, and high speed input interface circuit, which is located at, to be received End.Fig. 1 shows the application schematic diagram of RapidIO interconnection in embedded systems.As shown in Figure 1, transmitting terminal is as a kind of logical Believe equipment, including processor 101, SRIO interfaces 102, memory 103, as being cached in piece, including drive software, storage Device 104, as random access memory outside piece, wherein each device inside transmitting terminal is communicated by bus.Receiving terminal is as one Kind of communication equipment, including processor 107, SRIO interfaces 105, memory 106, including drive software, as being cached in piece, Memory 108 is as the outer random access memory of piece, wherein each device inside receiving terminal is communicated by bus.Transmitting terminal with Pass through serial high speed input and output (Serial Rapid Input Output, abbreviation SRIO) interface communication between receiving terminal.Hair For sending end by SRIO interfaces 102 to receiving terminal transmission data, receiving terminal receives the number that transmitting terminal is sent by SRIO interfaces 105 According to.

During specific implementation, the data transmission between receiving terminal and transmitting terminal is realized based on Rapid I/O protocols.Its In, the data packet maximum under RapidIO agreements supports the transmission of 4KB.Rapid I/O protocols use three layers of staging hierarchy：Logic Layer, transport layer and physical layer.

It is big in order to solve transmitting terminal and receiving terminal software overhead, the low problem of efficiency of transmission.The present embodiment is in Rapid On the basis of I/O protocol, one layer of link layer is further added by logical layer.The number of transmitting terminal and receiving terminal defined in the link layer Fractionation according to packet and shuffling information, for example, sequence number in sequence of message of message total, message, data packet mark so that The transmission of data packet can be completed by hardware, rather than be completed by software.Fig. 2 is that the present invention rapidly inputs output transmission The structural schematic diagram of protocol stack.As shown in Fig. 2, link layer be located at it is top, logical layer is located under link layer, logical layer define All agreements and packet format support the I/O system of memory mapping, message transmission, flow control and data flow.To transmitting terminal and Receiving terminal is initiated and is completed data packet transmission and submits necessary information.Transport layer defines the address of Rapid IO in middle layer Space and the routing iinformation needed for transmitting terminal and receiving terminal common transmission data packet.Physical layer is at the bottom of entire hierarchical structure Portion includes the details of device level interface, such as packet transmission mechanism, flow control, electrical characteristic and mistake manages.

Speedy carding process interface circuit provided in this embodiment is arranged in the SRIO interfaces 102 of transmitting terminal as shown in Figure 1, High speed input interface circuit is arranged in the SRIO interfaces 105 of receiving terminal as shown in Figure 2.Those skilled in the art can manage Solution, during specific implementation, arbitrary SRIO interfaces can include speedy carding process interface circuit provided in this embodiment with And high speed input interface circuit.For convenience of description, the present embodiment in figure 3 simultaneously depict speedy carding process interface circuit and High speed input interface circuit.As shown in figure 3, Fig. 3 is the structural schematic diagram of speedy carding process of the present invention, input interface circuit.

For convenience of description, use specific embodiment below, respectively to the speedy carding process interface circuit of transmitting terminal and The high speed input interface circuit of receiving terminal is described in detail.

With reference to Fig. 1 to Fig. 3, to speedy carding process interface circuit, how transmission data packet is described in detail.Such as Fig. 3 institutes Show, the speedy carding process interface circuit of transmitting terminal includes：Link layer circuit 303, package module 304 and speedy carding process interface 305, Wherein, package module 304 is connect with link layer circuit 303, speedy carding process interface 305 respectively.Optionally, the speedy carding process interface Circuit further includes software interface 301 and chained list module 302, and wherein software interface 301 is connect with chained list module 302, chained list mould Block 302 is connect with link layer circuit 303.

Wherein, link layer circuit 303, for obtaining the pending of the processor configuration except speedy carding process interface circuit Data packet is sent, link layer packaging is carried out to sent the partial data in data packet, obtains including data and link layer letter The message of breath, and message is sent to package module 304, link layer information include that the corresponding message total of data packet, message exist The mark of the corresponding data packet of sequence number, message in sequence of message；

Package module 304 carries out message logical layer, transmission successively for the message that receives link layer circuit 303 is sent Layer and physical layer encapsulation obtain the message for completing encapsulation, and the message for completing encapsulation are sent to speedy carding process interface 305；

Speedy carding process interface 305, the message of the completion encapsulation for receiving the transmission of package module 304, will complete encapsulation Message is sent to receiving terminal.

During specific implementation, in transmitting terminal, processor 101 for reading drive software from memory 104, and Under the driving of drive software data packet to be sent is provided to speedy carding process interface circuit.Link layer in speedy carding process interface circuit Circuit 303 is determining that this is to be sent from acquisition in memory (such as memory 104 shown in FIG. 1) there is currently when available bandwidth Data packet, in the data packet to be sent partial data carry out link layer packaging (link layer in corresponding diagram 2), obtain Message including data and link layer information.Wherein, the data packet stored before being processor of the data packet in memory. The form schematic diagram of link layer can be as shown in Figure 4.Optionally, link layer circuit 303 can encapsulate link layer information to the message Head.

Fig. 4 is the form schematic diagram of link layer.As shown in figure 4, the bit wide of MsgNo is 16, it is used to indicate the mark of data packet Know, for the message of same data packet, package identification is identical.It will be understood by those skilled in the art that the mark of the data packet It can be number, often handle the corresponding data packet of a task, which adds one；The bit wide of FragNum is 8, for referring to Show message total；The bit wide of FragNo is 8, is used to indicate sequence number of the message in sequence of message.With a specific example For, the data packet of a 12KB will produce 3 messages, the FragNum=3 of the first message, FragNo=0；Second message FragNum=3, FragNo=1；Third message FragNum=3, FragNo=2, the package identification phase of above-mentioned 3 messages Together, for example, MsgNo=2.

Link layer circuit 303 obtain include data and link layer information message after, which is sent to encapsulation Module 304.Package module 304 carries out the message logical layer, transport layer and physical layer encapsulation successively, obtains completing encapsulation Message, and the message that the completion encapsulates is sent to speedy carding process interface 305, encapsulation will be completed by speedy carding process interface 305 Message is sent to receiving terminal.

Speedy carding process interface circuit provided by the invention, the speedy carding process interface circuit are arranged in high speed input/output interface In, speedy carding process interface circuit is applied to rapidly input output transport protocol stack, which includes link layer, logical layer, biography Defeated layer and physical layer；The speedy carding process interface circuit includes：Link layer circuit, package module and speedy carding process interface.Its In, processor only needs to configure data packet to be sent, and link layer circuit can split the data packet, and split During, link layer information is encapsulated into data, so that receiving terminal can recombinate data packet according to link layer information, Then it is further encapsulated by package module, the data for completing encapsulation are directly sent to receiving terminal by speedy carding process interface, are not needed Data packet is split by processor runs software, reduces the expense of software, does not interfere with the processing of general processor Efficiency.

Optionally, on the basis of the above embodiments, in order to ensure that multiple data packets can orderly be sent, the present embodiment is also Software interface 301 and chained list module 302 can be coordinated, the transmission of each data packet is managed by task list.

Specifically, processor (such as processor 101 in Fig. 1) generates descriptor according to data packet to be sent, and will The descriptor is handed down to software interface 301.After software interface 301 obtains the descriptor, which is sent to chained list mould Block 302.Wherein, descriptor may include the mark etc. of the size of data packet, the memory address of data packet and receiving terminal.One In the feasible realization method of kind, the way of realization of descriptor is as shown in Figure 5.Fig. 5 is the form schematic diagram of descriptor.Wherein, The bit wide of size is 20, is used to indicate the size of data packet, unit is byte, and data packet maximum can be 1M (million) byte；addr Bit wide be 32, be used to indicate the address of data packet in memory；The bit wide of dest_id is 16, is used to indicate the mark of receiving terminal Know.The descriptor is added in task list by chained list module 302, is determining that there is currently available bandwidths, i.e. speedy carding process interface When 305 free time, descriptor can be obtained from task list, and the descriptor is sent to link layer circuit 303.

Link layer circuit 303 receives the descriptor that chained list module 302 is sent, and link layer circuit 303 is according in data packet Address is deposited, obtains data, and the reading order according to the data in the packet in the packet, determines the message in message sequence Sequence number in row.In the process, link layer circuit 303 is according to the size of the descriptor acquiring data packet, according to data packet Size and size of data, determine message total, according to the mark of other data packets, generate with the mark of other data packets not Same package identification.Wherein, size of data can be 4KB.At this point, link layer circuit 303 is being reported according to message total, message The mark of sequence number and data packet in literary sequence generates link layer information, and link layer information is encapsulated into the data, Obtain message corresponding with the data.The mark of the message and receiving terminal is sent to package module 304, by package module 304 it is further encapsulated, and the message for completing encapsulation and the mark of receiving terminal are sent to speedy carding process interface 305, by Speedy carding process interface 305 sends the message of completion encapsulation according to the mark of receiving terminal.

Further, after link layer circuit 303 carries out link layer packaging to the message, link layer circuit 303 judges should Whether message is the last one message of the data packet, if so, descriptor deletion instruction is sent to chained list module 302, with instruction Chained list module 302 deletes the descriptor from task list.If it is not, then continuing to read another part data in the data packet. Specific reading and transmission process, similar to the above embodiments, details are not described herein again for the present embodiment.Those skilled in the art can be with Understand, specific reading times are determined that the size of the data read every time is identical by the size of data packet.

Speedy carding process interface circuit provided in this embodiment obtains what processor was configured according to data packet by software interface Descriptor, chained list module send the number for not being sent to receiving terminal to link layer module according to the idle state of speedy carding process interface According to the corresponding descriptor of packet, link layer packaging of the link layer module to data so that the transmission of data packet is by speedy carding process interface State determine so that the transmission of message is not limited by identification field, and available bandwidth is utilized to greatest extent.Package module pair The message that encapsulation is completed is sent to receiving terminal by the further encapsulation of data and speedy carding process interface, need not pass through processor Runs software is split in advance to sent data packet, as long as reading data in the packet, to the data into line link After layer encapsulation, you can send the data, reduce the expense of software, do not interfere with the treatment effeciency of processor.

With reference to Fig. 1 to Fig. 3, how high speed input interface circuit is received and reorganizing packets are described in detail. As shown in figure 3, the high speed input interface circuit of receiving terminal includes：High speed input interface 401, decapsulation module 402 and link Layer circuit 403, wherein decapsulation module 402 is connect with high speed input interface 401 and link layer circuit 403 respectively.It is optional Ground, the high speed input interface circuit further include：Software interface 405 and cached configuration module 404；Cached configuration module 404 is divided It is not connect with software interface 405 and link layer circuit 403.

Wherein, high speed input interface 401, for receive transmitting terminal transmission message, and by message be sent to deblocking it is die-filling Block 402；

Decapsulation module 402, the message for receiving the transmission of high speed input interface carry out message physical layer, pass successively The decapsulation of defeated layer and logical layer, obtain include link layer information message, and by including link layer information message send To link layer circuit 403, link layer information includes the corresponding number of sequence number, message of message total, message in sequence of message According to the mark of packet；

Link layer circuit 403, the message for including link layer information for receiving the transmission of decapsulation module 402, to including The message of link layer information is decapsulated into downlink layer, the data in link layer information and message is obtained, according to data packet Mark, the sequence number of message total and message in sequence of message, to the data in data and other messages in message into Row recombination obtains the corresponding data packet of message.

During specific implementation, receiving terminal receives the message that transmitting terminal is sent by high speed input interface 401, and should Message is sent to decapsulation module 402.Decapsulation module 402 carries out physical layer, transport layer and logical layer successively to message Decapsulation, obtain include link layer information message, which is sent to link layer circuit 403.

Link layer circuit 403 decapsulates the message into downlink layer, obtains link layer information.Optionally, work as link layer Information encapsulation can obtain link layer information at the head of the message from the head of the message.Link layer information includes that message is total The mark of number, sequence number, message corresponding data packet of the message in sequence of message.

Specifically, link layer circuit 403 is after receiving the message, according to sequence of the message in sequence of message Number, which is stored and recombinated, then paid-in message data corresponding to package identification carries out dull add at 1 Reason, for the package identification, judges whether paid-in message number is consistent with message total, if so, showing will be each Packet reassembling is data packet, if it is not, then showing that the data packet has not yet reassembled success.

After data packet recombinates successfully, processor 107 is used to read drive software from memory 104 and in drive software Driving under, from speedy carding process interface circuit receive recombination after data packet.

High speed input interface circuit provided in this embodiment, high speed input interface circuit setting connect in high speed input and output Mouthful in, high speed input interface circuit be applied to rapidly input output transport protocol stack, the protocol stack include link layer, logical layer, Transport layer and physical layer；The high speed input interface circuit includes：High speed input interface, decapsulation module and link layer electricity Road.Wherein, high speed input interface circuit receives the message that transmitting terminal is sent, and decapsulation module carries out physics successively to the message The decapsulation of layer, transport layer and logical layer, link layer circuit carry out the recombination of message according to link layer information, obtain complete Data packet need not recombinate message by processor runs software, reduce the expense of software, not interfere with general place Manage the treatment effeciency of device.

Optionally, on the basis of the above embodiments, in order to ensure that the message received can have Quick Casting and orderly deposit Storage, the present embodiment can also coordinate cached configuration module 404 and software interface 405, the data of reception managed by recombination table Packet.

Specifically, software interface 405 obtains processor (such as the processor in Fig. 1 except high speed input interface circuit 107) cache information is sent to cached configuration module 404 by the cache information configured, and cached configuration module 404 believes the caching Breath is stored.

When the first message in the data packet that link layer circuit 403 gets transmitting terminal transmission, according to link layer information Empty list item is initialized in recombination table.Specifically, link layer circuit 403 determines number according to message total and size of data According to memory space shared by packet, cache information is obtained to cached configuration module 404 according to the memory space, which includes chain The initial position of road floor buffer area and the initial position and size of size and data buffer area, link layer circuit 403 is according to report Sequence number and cache information of the text in sequence of message, the data in message are stored into data buffer storage, by data packet pair The link layer information for the first message answered is stored into link layer caching.Meanwhile according to the package identification in link layer information And message total, package identification and message total in list item are set, and package identification is corresponding paid-in Message number is set to 1.

Optionally, in the present embodiment, in order to be managed to the list item in recombination table, list item resource is not wasted, then is existed After data packet recombinates successfully, the list item is deleted so that the list item is sky, accordingly, use is increased in the list item of recombination table In indicating whether the list item is empty indicating bit.As long as link layer circuit 403 is according to the indicating bit in the recombination table, so that it may with Empty list item is judged whether in recombination table.

Recombination tableau format can be as shown in Figure 6 as a result,.Fig. 6 is recombination tableau format schematic diagram.As shown in fig. 6, msgno It is used to indicate package identification；Fragnum is used to indicate message total；Fragcnt is used to indicate paid-in message number； Head_ptr is used to indicate the address of link layer buffer area；Payload_ptr is used to indicate the address of data buffer area；Vld is used In instruction list item, whether the bit wide for being empty indicating bit vld, vld is 1, and indicating bit is specially effective indicating bit or invalid instruction Position, wherein invalid indicating bit is used to indicate empty list item, and effective indicating bit is used to indicate the list item of non-empty.

When link layer circuit 403 gets other messages of the data packet of transmitting terminal transmission, message correspondence is obtained Package identification, in recombinating table determine exist and the matched list item of the package identification, i.e., there are the data packets in list item Mark, then only paid-in message number corresponding to the package identification in the list item carries out dull plus 1 processing, according to message Sequence number in sequence of message determines the storage offset of the data in the message, according to the offset and data buffer storage The initial position in area stores data to data buffer area.When not being the first message of the data packet for the message, do not need Store the link layer information in the message.

In the present embodiment, by link layer buffer area and data buffer area, link layer information and data separating are realized Storage.Further, the present embodiment can also establish the address of link layer buffer area and the mapping of the address of data buffer area is closed System.For example, last 4 byte on the head of first message to be changed to the initial address of data buffer area.In this way, can be by data It measures less link layer buffer area to be all mapped in the spatial cache of processor (such as processor 101 in Fig. 1) so that place Manage device can in the spatial cache of processor quick obtaining link layer information, and according to the mapping relations, obtain data packet, carry The high treatment effeciency of processor.

Optionally, in order to save spatial cache, the link layer information of each data packet can closely be arranged in link layer buffer area It puts, each data packet is closely discharged in data buffer area.Fig. 7 is the storage schematic diagram of link layer information and data packet.Such as Fig. 7 institutes Show, store 3 data packets altogether, wherein the areas H represent link breath buffer area, and the areas P represent data buffer area.3 data The corresponding link layer information of packet (P0, P1, P2) is closely discharged in link layer buffer area, and 3 data packets (P0, P1, P2) are corresponding Data are closely discharged in data buffer area.

High speed input interface circuit provided in this embodiment is obtained by software interface except high speed input interface circuit Cache information is sent to cached configuration module by the cache information of processor configuration, cached configuration module to the cache information into Row storage, and the cache information is sent to link layer circuit.Link layer circuit decapsulates message into downlink layer, obtains chain Road floor information, according to the mark of the corresponding data packet of message, determination presence and the matched list item of package identification in recombinating table, According to the sequence number of cache information and message in sequence of message in list item, the data in message are stored to data buffer storage In, the link layer information of first message is stored to link layer in caching, is directly recombinated while storing data, no It needs to recombinate message by processor runs software, reduces the expense of software, do not interfere with the processing effect of processor Rate.

Fig. 8 is the flow diagram of data transmission method embodiment one of the present invention.This method utilizes speedy carding process interface electricity Road carries out data transmission, which is arranged in high speed input/output interface, and speedy carding process interface circuit is answered Protocol stack for rapidly inputting output transmission, protocol stack includes link layer, logical layer, transport layer and physical layer；High speed is defeated Outgoing interface circuit includes：Link layer circuit, package module and speedy carding process interface.This method includes：

Step 801 obtains the processor being located at except speedy carding process interface circuit configuration by the link layer circuit Data packet to be sent carries out link layer packaging to the partial data in the data packet to be sent, obtains including the data And the message of link layer information, and the message is sent to package module, the link layer information includes the data packet The mark of sequence number in sequence of message of corresponding message total, the message, the corresponding data packet of the message；

Step 802 receives the message that the link layer circuit is sent by the package module, to the message according to Secondary progress logical layer, transport layer and physical layer encapsulation obtain the message for completing encapsulation, and the message for completing encapsulation are sent out It send to high speed output interface；

Step 803, the message encapsulated by the completion that package module described in the speedy carding process interface is sent, The message for completing encapsulation is sent to receiving terminal.

Optionally, the speedy carding process interface circuit further includes：Software interface and chained list module,

Optionally, further include the size of the data packet in the descriptor, the method further includes：

Fig. 9 is the flow diagram of data transmission method embodiment two of the present invention.This method utilizes high speed input interface electricity The data transmission method that road carries out data transmission, the high speed input interface circuit are arranged in high speed input/output interface, high speed Input interface circuit be applied to rapidly input output transmission protocol stack, protocol stack include link layer, logical layer, transport layer and Physical layer；High speed input interface circuit includes：High speed input interface, decapsulation module and link layer circuit, this method include：

Step 901 receives the message that transmitting terminal is sent by the high speed input interface, and the message is sent to institute State decapsulation module；

Step 902 receives the message that the high speed input interface is sent by the decapsulation module, to the message according to The secondary decapsulation for carrying out physical layer, transport layer and logical layer, obtain include link layer information message, and will be described including chain The message of road floor information is sent to the link layer circuit, and the link layer information includes message total, the message in message The mark of sequence number, the corresponding data packet of the message in sequence；

Step 903 is received described in the decapsulation module transmission by the link layer circuit including link layer information Message, the message including link layer information is decapsulated into downlink layer, obtains the link layer information and described Data in message, according to the identifying of the data packet, the sequence of the message total and the message in sequence of message Number, recombinated to obtain the corresponding data packet of the message to data and the data in other messages in the message.

Optionally, it is described by link layer circuit according to the identifying of the data packet, the message total and the report Sequence number of the text in sequence of message is recombinated to obtain the report to the data in the message with the data in other messages The corresponding data packet of text, including：

Optionally, the high speed input interface circuit further includes：Software interface and cached configuration module；The method is also Including：

One of ordinary skill in the art will appreciate that：Realize that all or part of step of above-mentioned each method embodiment can lead to The relevant hardware of program instruction is crossed to complete.Program above-mentioned can be stored in a computer read/write memory medium.The journey When being executed, execution includes the steps that above-mentioned each method embodiment to sequence；And storage medium above-mentioned includes：ROM, RAM, magnetic disc or The various media that can store program code such as person's CD.

Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims

1. a kind of speedy carding process interface circuit, which is characterized in that the speedy carding process interface circuit is arranged in high speed input and output In interface, the speedy carding process interface circuit is applied to rapidly input the protocol stack of output transmission, and the protocol stack includes link Layer, logical layer, transport layer and physical layer；The speedy carding process interface circuit includes：Link layer circuit, package module and height Fast output interface, wherein the package module is connect with the link layer circuit, the speedy carding process interface respectively；

The link layer circuit, the data to be sent for obtaining the processor configuration except speedy carding process interface circuit Packet carries out link layer packaging to the partial data in the data packet to be sent, obtains including the data and link layer The message of information, and the message is sent to package module, the link layer information includes the corresponding message of the data packet The mark of sequence number of total, the described message in sequence of message, the corresponding data packet of the message；

The package module, the message sent for receiving the link layer circuit, logic is carried out to the message successively Layer, transport layer and physical layer encapsulation, obtain the message for completing encapsulation, and to be sent to high speed defeated by the message for completing encapsulation Outgoing interface；

The speedy carding process interface, the message for receiving the completion encapsulation that the package module is sent will be completed to encapsulate The message be sent to receiving terminal.

2. speedy carding process interface circuit according to claim 1, which is characterized in that the speedy carding process interface circuit also wraps It includes：Software interface and chained list module, the software interface are connect with the chained list module, the chained list module and the link Layer circuit connection；

The software interface, the descriptor for obtaining the processor configuration, and the descriptor is sent to the chained list Module, the descriptor include the memory address of the data packet and the mark of the receiving terminal；

The chained list module, the descriptor sent for receiving the software interface, and the descriptor is added to task list In, in the speedy carding process interface free time, the descriptor in the task list is sent to the link layer circuit；

The link layer circuit is specifically used for, and the descriptor that the chained list module is sent is received, according to the data packet Memory address obtains the data packet to be sent of the processor configuration, to the number in the data packet to be sent from memory According to link layer packaging is carried out, obtain include the data and link layer information message, and by the message and described connect The mark of receiving end is sent to package module；

The package module is additionally operable to, and receives the mark for the receiving terminal that the link layer circuit is sent, and by the reception The mark at end is sent to the speedy carding process interface；

The speedy carding process interface is specifically used for, and receives the message of the completion encapsulation that the package module is sent and described The message for completing encapsulation is sent to receiving terminal by the mark of receiving terminal according to the mark of the receiving terminal.

3. speedy carding process interface circuit according to claim 2, which is characterized in that further include the number in the descriptor According to the size of packet, the link layer circuit is additionally operable to,

According to the mark of other data packets, the mark of the data packet different from the mark of other data packets is generated；

According to the size of the data packet and the size of the data, the message total is obtained,

According to reading order of the data in the data packet, sequence number of the message in sequence of message is determined；

According to the mark of the sequence number and the data packet of the message total, the message in sequence of message, institute is generated State link layer information.

4. speedy carding process interface circuit according to claim 2 or 3, which is characterized in that the link layer circuit is additionally operable to,

Judge the message whether be the data packet the last one message；

If so, sending descriptor to the chained list module deletes instruction, the descriptor deletes instruction and is used to indicate the chained list Module deletes the descriptor from the task list；

If it is not, continuing to read another part data in the data packet.

5. a kind of communication equipment, which is characterized in that including speedy carding process interface according to any one of claims 1 to 4 electricity Road and processor, memory；

The memory includes drive software；

The processor, for reading the drive software and under the driving of the drive software to described from the memory Speedy carding process interface circuit provides data packet to be sent.

6. a kind of high speed input interface circuit, which is characterized in that the high speed input interface circuit is arranged in high speed input and output In interface, the high speed input interface circuit is applied to rapidly input the protocol stack of output transmission, and the protocol stack includes link Layer, logical layer, transport layer and physical layer；The high speed input interface circuit includes：High speed input interface, decapsulation module with And link layer circuit, wherein the decapsulation module is connect with the high speed input interface and the link layer circuit respectively；

The high speed input interface, for receive transmitting terminal transmission message, and by the message be sent to it is described deblocking it is die-filling Block；

The decapsulation module, the message sent for receiving the high speed input interface, physics is carried out to the message successively The decapsulation of layer, transport layer and logical layer, obtain include link layer information message, and by it is described include link layer information Message is sent to the link layer circuit, and the link layer information includes the sequence of message total, the message in sequence of message The mark of row number, the corresponding data packet of the message；

The link layer circuit, the message for including link layer information sent for receiving the decapsulation module, to institute It states the message including link layer information to decapsulate into downlink layer, obtains the number in the link layer information and the message According to according to the identifying of the data packet, the sequence number of the message total and the message in sequence of message, to the report Data in text and the data in other messages are recombinated to obtain the corresponding data packet of the message.

7. high speed input interface circuit according to claim 6, which is characterized in that the link layer circuit is specifically used for,

The message for including link layer information that the decapsulation module is sent is received, to the report for including link layer information Text is decapsulated into downlink layer, obtains the link layer information and the data；

The matched list item of mark existed with the data packet is determined in recombinating table, the list item includes the data packet Mark, cache information and message total, the cache information include initial position and the size of link layer buffer area, and number Initial position according to buffer area and size；

According to sequence number of the message in sequence of message and the cache information, by the data in the message store to In the data buffer storage, the link layer information of the corresponding first message of the data packet is stored to the link layer in caching；

8. high speed input interface circuit according to claim 7, which is characterized in that the high speed input interface circuit also wraps It includes：Software interface and cached configuration module；The cached configuration module respectively with the software interface and the link layer Circuit connects；

The software interface, the cache information for obtaining the processor configuration except the high speed input interface circuit, The cache information is sent to the cached configuration module；

The cached configuration module, the cache information sent for receiving the software interface, to the cache information into Row storage, and send the cache information to the link layer circuit.

9. a kind of communication equipment, which is characterized in that include the high speed input interface electricity as described in any one of claim 6 to 8 Road and processor, memory；

The memory includes drive software；

The processor, for reading the drive software and under the driving of the drive software from described from the memory High speed input interface circuit receives the data packet after recombination.

10. a kind of data transmission method carried out data transmission using speedy carding process interface circuit, which is characterized in that the high speed Output interface circuit is arranged in high speed input/output interface, and the speedy carding process interface circuit is applied to rapidly input output biography Defeated protocol stack, the protocol stack include link layer, logical layer, transport layer and physical layer；The speedy carding process interface circuit Including：Link layer circuit, package module and speedy carding process interface, the method includes：

The data packet to be sent of the processor being located at except speedy carding process interface circuit configuration is obtained by the link layer circuit, Link layer packaging is carried out to the partial data in the data packet to be sent, obtains including the data and link layer information Message, and the message is sent to package module, the link layer information include the corresponding message total of the data packet, The mark of sequence number of the message in sequence of message, the corresponding data packet of the message；

The message that the link layer circuit is sent is received by the package module, logic is carried out successively to the message Layer, transport layer and physical layer encapsulation, obtain the message for completing encapsulation, and to be sent to high speed defeated by the message for completing encapsulation Outgoing interface；

By the message for the completion encapsulation that package module described in the speedy carding process interface is sent, encapsulation will be completed The message is sent to receiving terminal.

11. according to the method described in claim 10, it is characterized in that, the speedy carding process interface circuit further includes：Software connects Mouth and chained list module,

The descriptor of the processor configuration is obtained by the software interface, and the descriptor is sent to the chained list mould Block, the descriptor include the memory address of the data packet and the mark of the receiving terminal；

The descriptor that the software interface is sent is received by the chained list module, and the descriptor is added to task list In, in the speedy carding process interface free time, the descriptor in the task list is sent to the link layer circuit；

The number to be sent that the processor being located at except speedy carding process interface circuit configuration is obtained by the link layer circuit According to packet, including：

By the link layer circuit, according to the memory address of the data packet, the processor configuration is obtained from memory Data packet to be sent；

It is described the message is sent to the package module to include：The mark of the message and the receiving terminal is sent to The package module；

The method further includes：The mark for the receiving terminal that the link layer circuit is sent is received by the package module, And the mark of the receiving terminal is sent to the speedy carding process interface；

The message of the completion encapsulation sent by package module described in the speedy carding process interface, will complete to seal The message of dress is sent to receiving terminal, including：

The message encapsulated by the completion that package module described in the speedy carding process interface is sent and the reception The message for completing encapsulation is sent to receiving terminal by the mark at end according to the mark of the receiving terminal.

12. according to the method for claim 11, which is characterized in that further include the big of the data packet in the descriptor Small, the method further includes：

By the link layer circuit according to the mark of other data packets, the number different from the mark of other data packets is generated According to the mark of packet；

By the link layer circuit according to the size of the data packet and the size of the data, it is total to obtain the message Number；

Reading order by the link layer circuit according to the data in the data packet determines the message in message Sequence number in sequence；

By the link layer circuit according to sequence number in sequence of message of the message total, the message and the number According to the mark of packet, the link layer information is generated.

13. a kind of data transmission method carried out data transmission using high speed input interface circuit, which is characterized in that the high speed Input interface circuit is arranged in high speed input/output interface, and the high speed input interface circuit is applied to rapidly input output biography Defeated protocol stack, the protocol stack include link layer, logical layer, transport layer and physical layer；The high speed input interface circuit Including：High speed input interface, decapsulation module and link layer circuit, the method includes：

By the high speed input interface receive transmitting terminal send message, and by the message be sent to it is described deblocking it is die-filling Block；

The message that the high speed input interface is sent is received by the decapsulation module, physics is carried out successively to the message The decapsulation of layer, transport layer and logical layer, obtain include link layer information message, and by it is described include link layer information Message is sent to the link layer circuit, and the link layer information includes the sequence of message total, the message in sequence of message The mark of row number, the corresponding data packet of the message；

The message for including link layer information described in the decapsulation module transmission is received by the link layer circuit, to described Message including link layer information is decapsulated into downlink layer, obtains the data in the link layer information and the message, According to the identifying of the data packet, the sequence number of the message total and the message in sequence of message, to the message In data and the data in other messages recombinated to obtain the corresponding data packet of the message.

14. according to the method for claim 13, which is characterized in that it is described by link layer circuit according to the data packet Mark, the sequence number of the message total and the message in sequence of message, to the data and other reports in the message Data in text are recombinated to obtain the corresponding data packet of the message, including：

The matched list item of mark existed with the data packet, the list item are determined in recombinating table by the link layer circuit Include mark, cache information and the message total of the data packet, the cache information includes rising for link layer buffer area The initial position and size of beginning position and size and data buffer area；

It, will be described by the link layer circuit according to sequence number of the message in sequence of message and the cache information Data in message are stored into the data buffer storage, by the link layer information of the corresponding first message of the data packet store to In the link layer caching；

Mark, message total by the link layer circuit according to the data packet determine data corresponding with the message Whether packet recombinates success.

15. according to the method for claim 14, which is characterized in that the high speed input interface circuit further includes：Software connects Mouth and cached configuration module；The method further includes：

The cache information of the configuration of the processor except the high speed input interface circuit is obtained by the software interface, it will The cache information is sent to the cached configuration module；

The cache information that the software interface is sent is received by the cached configuration module, the cache information is carried out Storage, and send the cache information to the link layer circuit.