CN105510883A - Secondary radar digital inquiry coding implementation method - Google Patents

Secondary radar digital inquiry coding implementation method Download PDF

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CN105510883A
CN105510883A CN201510884064.7A CN201510884064A CN105510883A CN 105510883 A CN105510883 A CN 105510883A CN 201510884064 A CN201510884064 A CN 201510884064A CN 105510883 A CN105510883 A CN 105510883A
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data
interrogation
digitizing
digital
mode
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CN105510883B (en
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张中南
李海军
张竞文
唐斯亮
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Sichuan Jiuzhou ATC Technology Co Ltd
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Sichuan Jiuzhou ATC Technology Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/74Systems using reradiation of radio waves, e.g. secondary radar systems; Analogous systems

Abstract

The invention discloses a secondary radar digital inquiry coding implementation method. The method specifically comprises the following steps of constructing a communication mechanism, carding the digital content, planning a data communication format, formulating a digital starting time reference criterion and a digital data generation criterion, compiling a modal digital coded data script, receiving a mode changing control command in real time, automatically adjusting interrogation coding script data, and dynamically outputting digital coded pulses. According to the technical scheme of the invention, interrogation modes can be switched conveniently and accurately in real time. Meanwhile, interrogation coding pulses can be efficiently outputted based on the timing relationship thereof. When the method is applied to a ground-based radar and an airborne radar provided with a secondary radar device, the switching efficiency of interrogation modes is improved. Meanwhile, the real-time performance, the reliability and the stability of the secondary radar device are improved. Therefore, the tactical and technical index of a radar system is further improved. The method provides a stable and reliable basis for the synthetic combat commanding and the intelligent decision commanding of an electronic task system.

Description

Secondary radar digitizing interrogation coding implementation method
Technical field
The present invention relates to radar (comprising inquisitor and the answering machine of secondary radar) communication technical field, particularly relate to a kind of novel secondary radar digital coding implementation method based on FPGA+PowerPC framework.
Background technology
Along with the development of aviation industry, the increase of air traffic makes the effect of air traffic control system (ATCS) seem extremely important.Blank pipe personnel utilize radar to provide regulatory service for the aircraft be identified, and can see the information parameter of aircraft from radar screen.In aviation management system, normal mode and S mode technology are used for function for monitoring, are based upon independent addressing, and on the basis of selection inquiry, message exchange is by up inquiry content and descending response content are carried out pulse code realization.Scrambler is the center of whole radar, for generation of complete machine synchronizing signal and interrogating signal.Therefore, there is high premium properties inquisitor encoder pulse coded signal treatment technology most important.Strict requirement is proposed to the real-time of Radar Signal Processing simultaneously, within the time of Microsecond grade, complete the process to answer signal, complete target identification, provide the information parameter of target aircraft; Strict demand simultaneously in equipment volume, power consumption makes signal handling equipment to miniaturization, intellectuality, programmable trend development, must require that again signal processing system has the needs of high reliability and system upgrade.For above-mentioned growth requirement, the expert in domestic and international secondary radar field has carried out the theoretical research of system, for the current difficult problem faced of gordian technique of coding proposes multiple solution, mainly concentrate on the aspect such as the real-time of coding and the extensibility of coding, these researchs have promoted the correlation technique development of secondary radar scrambler greatly, but the achievement that the theory that these documents relate to is applied to engineering practice is few.
For the radar coding techniques of widespread use in prior art, be necessary to provide a kind of novel secondary radar digital coding implementation method based on FPGA+PowerPC framework, and be applied to engineering practice.
Summary of the invention
In order to overcome the shortcoming of prior art, the invention provides a kind of secondary radar digitizing interrogation coding implementation method, solve that traditional secondary radar encoder device volume is large, power consumption is not high, poor real and the not high problem of programmability, make signal handling equipment to miniaturization, intellectuality, programmable trend development.
The technical solution adopted in the present invention is: a kind of secondary radar digitizing interrogation coding implementation method, comprises the steps:
Communication mechanism between step one, structure FPGA and PowerPC;
Step 2, combing needed number content, layout data communication format;
Step 3, according to each pattern sequential relationship, formulate digitizing initial time with reference to criterion and mode digital data genaration criterion;
Step 4, work out the digital coding script file of all patterns;
Step 5, power on and read digital coding script file, and the script data that criterion of shaking hands according to powering on performs between PowerPC and FPGA is mutual, completes the verification of coded data according to service data verification scheme simultaneously;
Step 6, real-time reception preserve the interrogation mode Variation control order that host computer initiatively sends, and judge whether it meets mode control commands time-to-live criterion: if do not met, then be considered as invalid command to be removed, then terminate the process of epicycle digital coding; As met, then enter step 7;
Step 7, according to change interrogation mode produce mode control data in real time, and write fix IO address;
Step 8, FPGA select the script data of corresponding modes according to the mode control data of current write, and press output frequency by the output of data script, then terminate the process of epicycle digital coding.
Further, the communication mechanism content described in step one between FPGA and PowerPC is: in FPGA, set up the dual port RAM memory that two bit wides are 8, the degree of depth is 2048, for the mode data after interactive digitizing.Wherein, PowerPC is responsible for its data write appropriate address, and FPGA is responsible for exporting after digital independent with the sample frequency of 20MHZ multiplying power.
Further, digitized content described in step 2 amounts to 14 signals, is respectively: M1, M2, M3/A, MC, MB and MD six kinds of patterns; M1_AM, M2_AM, M3/A_AM, MC_AM, MB_AM and MD_AM six kinds of Mode Launch doors; And RECGTC and GTC two kinds of gain time control signals.
Further, data communication form described in step 2 refers to the communication format of the one-signal set up in conjunction with communication mechanism and digitized content, the value energy after often kind of signal digital and only can take dual port RAM bit wide.
Further, digitizing initial time described in step 3 refers to reference to criterion: often kind of mode digital initial time is all to push away 154us moment point for initial time reference point before P3 pulse front edge.
Further, described in step 3, mode digital data genaration criterion refers to: according to the timing requirements of often kind of interrogation mode in " international civil aviation annex 10 ", take 50ns as digitizing least unit, the linear coded data producing often kind of pattern.
Further, the criterion of shaking hands of powering on described in step 5 refers to: after PowerPC, FPGA electrifying startup, both first read the data of its appropriate address separately respectively, if the data of the data of this address and agreement do not possess consistance, then immediately to the address space write fixed number itself writing data, if when the data that both either party read are identical with appointment data, then terminate epicycle immediately and to power on handshake operation process.
Further, described in step 5, service data verification scheme content is: PowerPC software utilizes random function to produce 65 12 random seeds, then using these random seeds as sampling of data address, read its corresponding data in FPGA dual port RAM to compare with former data, the whole comparison success of all data from the sample survey that and if only if, Fang Ze is verified by service data; Otherwise then do not pass through.
Further, described in step 6, mode control commands time-to-live criterion content is: the mistiming that current time and control command generate is less than or equal to the inquiry command time-to-live.
Further, output frequency described in step 8 refers to that FPGA is by the output speed of the mode data of generation by discrete signal.
Compared with prior art, good effect of the present invention is:
The invention provides a kind of novel secondary radar digital coding implementation method based on FPGA+PowerPC framework, and be applied to engineering practice.The present invention is by making mode digital coding data script, real-time reception mode altering control command, automatic adjustment interrogation coding script data, the pulse of dynamical output digital coding, thus reach under the prerequisite effectively improving secondary radar encoder hardware cost requirement, improve the object arriving real-time and reliability.
The invention provides a kind of brand-new secondary radar digitizing interrogation coding actualizing technology, have widespread demand in fields such as military affairs investigation, Routing monitoring.Method of the present invention is under the prerequisite not increasing hardware cost, greatly can improve the expandability of secondary radar scrambler, in the aircraft industry of high speed development, the method only needs by amendment coding script data, just can in real time, just clean, the required interrogation mode of expansion exactly.
Accompanying drawing explanation
Examples of the present invention will be described by way of reference to the accompanying drawings, wherein:
Fig. 1 is a kind of novel secondary radar digital coding implementation method coding sequential ruleization figure based on the novel framework of FPGA+PowerPC;
Fig. 2 is a kind of novel secondary radar digital coding implementation method coded excitation door sequential ruleization figure based on the novel framework of FPGA+PowerPC.
Embodiment
It is by FPGA and PowerPC framework that the inventive method mainly realizes thought, formulate digitizing initial time with reference to criterion and digitalized data generating criteria, making mode digital coding data script, real-time reception mode altering control command, automatic adjustment interrogation coding script data, the pulse of dynamical output digital coding.
The inventive method specifically comprises the steps:
Communication mechanism between step one, structure FPGA and PowerPC:
According to the requirement such as size of FPGA and PowerPC read or write speed, transmission data, it is transmission medium that the present invention have selected with bus, with dual port RAM core in FPGA for data interaction hinge, constructs the communication mechanism that reliability is high, real-time, data rate is fast.Under this kind of framework, FPGA is as in PowerPC bus common plug-in peripheral hardware and its communication, and address scope is: 0x200f1000 ~ 0x200f1fff.
The dual port RAM memory that two bit wides are 8, the degree of depth is 2048 is set up, for the mode data after interactive digitizing in FPGA.Wherein, PowerPC is responsible for its data write appropriate address, and FPGA is responsible for exporting after digital independent with the sample frequency of 20MHZ multiplying power.
The maximum feature of design of above-mentioned communication mechanism is the Kernel Technology adopting FPAG dual port RAM, so-called kernel refers to that ISE platform development manufacturer is integrated in this platform interior after being encapsulated by the source code successfully realizing certain functional module (at this acute pyogenic infection of finger tip dual port RAM), and arranges and calling interface it for user provides.The employing of this technology reduces the cost of development of deviser greatly, for the integrated of system has established solid foundation.
Step 2, combing needed number content, layout data communication format:
According to " International Civil Aviation Covenant annex 10 " content, combing goes out secondary radar interrogation mode under regular situation and signal associated with it, amount to 14 kinds, and according to the sequential relationship of each signal, the concrete communication of often kind, ruleization signal sequentially and Content of communciation.Each signal sequence relation as depicted in figs. 1 and 2.Digitized content comprises: six kinds of patterns (M1, M2, M3/A, MC, MB and MD), six kinds of Mode Launch doors (M1_AM, M2_AM, M3/A_AM, MC_AM, MB_AM and MD_AM) and two kinds of gain time control signals (RECGTC, GTC), amounts to 14 signals.Realize functionally from 14 kinds of signals above, signal can be roughly divided into following three classes, they respectively: interrogation mode signal, emissioning controling signal and synchronizing signal; Interrogation mode signal comprises M1, M2, M3/A, MC, MB and MD6 kind signal, mainly realizes the uplink communication of inquisitor and answering machine; Emissioning controling signal comprises M1_AM, M2_AM, M3/A_AM, MC_AM, MB_AM and MD_AM, amounts to 6 kinds of signals, the sequential control to transmitter module when being mainly used in launching interrogating signal; Synchronizing signal, as the term suggests, mainly complete the time synchronized of secondary radar inquiry, answer signal, comprise 2 kinds of signals, i.e. RECGTC, GTC altogether.
Data communication form, wherein format content is: the digitized content of communication mechanism and this step in integrating step one, set up the communication format of one-signal, value (representing with 1 or 0) namely after often kind of signal digital can and only can take dual port RAM bit wide.In this kind of implementation method, the data communication form after the content of secondary radar inquiry system needed number and digitizing refers to shown in following table 1.
Table 1 secondary radar inquiry system digital information inventory
Step 3, according to each pattern sequential relationship, and composition graphs 1 and Fig. 2 formulate digitizing initial time with reference to criterion and mode digital data genaration criterion:
So-called digitizing initial time is exactly in all interrogation modes of secondary radar and signal associated with it, find a certain moment point as digitizing initial time reference point with reference to the thought that criterion is most crucial, and namely the selection of digitizing initial time reference point selects certain pulse in a certain signal or a certain signal as the reference moment point under whole secondary radar interrogation mode in above-mentioned 14 kinds of signals, then using this point for benchmark finds forward maximum idle time point in all signals (namely with reference to moment point front end again without useful pulse) as digitizing initial time reference point.The present invention's P3 pulse front edge that under selecting secondary radar interrogation mode, each pattern all has is as reference moment point, and digitizing initial time reference point is then the moment point pushing away 154us before P3 pulse front edge.
Initial time reference point can be described as again 0 moment reference point, according to the reference point of this setting, combing of the present invention action time of often kind of signal first pulse, then according to its sequential relationship of regulation in " international civil aviation annex 10 ", complete the location of each pulse operating time.Often kind of signal first pulse combing situation particular content sees the following form shown in 2.
Table 2 signal first pulse combing situation inventory
Mode digital data genaration criterion is the most crucial part of the present invention, and its design constraint comprises following content: 1) a kind of signal fixes corresponding one-bit digital data (permanent order performs by step 2 requirement); 2) high level digital value is 1, and low level digital value is 0; 3) the corresponding digitization time of a data is 50ns; 4) each signal digital final lengths is 65296.The particular content of mode digital data genaration criterion is: in strict accordance with the timing requirements of often kind of interrogation mode in " international civil aviation annex 10 ", take 50ns as digitizing least unit, the linear coded data producing often kind of pattern.In conjunction with design content and the design constraint of this criterion, the present invention transforms, and the final product after conversion is a digitized signal control table, and concrete detailed content sees the following form shown in 3.
The control table of table 3 secondary radar interrogation mode digitized signal
Step 4, the criterion generated according to upper step work out the digital coding script file of all patterns:
Digital coding script file totally 2, each file size is 2KB.In two coding script files, the content of a storage is 6 kinds of interrogation mode digitalized datas (i.e. D0-D7 least-significant byte data in table 2), and another content of storing is 8 kinds of pulse signal digital data (i.e. in table 1 D8-D15 most-significant byte data) relevant to interrogation mode.
Step 5, power on read mode digital coding script file, and the script data that criterion of shaking hands according to powering on performs between PowerPC and FPGA is mutual, completes the verification of coded data according to service data verification scheme simultaneously:
This step mainly completes the work of following three aspects, first aspect, the reading of the file that powers on; In file reading process, if read unsuccessful, then by software correlated variables the mode of the data of assignment digital coding script in mode stored in file (for place mat is made in the reading of pattern script data after powering on next time).Second aspect, powers on and shakes hands; Because there is certain otherness, randomness in PowerPC and FPGA power up on start-up time and startup sequencing, so that when performing script data and being mutual, the correctness that data perform cannot be ensured, for these reasons, formulate complete set, efficiently security policies (namely power on handshake mechanism) guarantee that the mutual success of script data is imperative.3rd aspect, the mutual and verification of script data.Data interaction essence refers to the description of PowerPC to FPGA dual port RAM kernel reading and writing process, and its implementation is mainly divided into two stages, and the first stage is PowerPC write operation mainly, and namely PowerPC transmits script data to FPGA.PowerPC is before by data write bus, its bottom layer driving first must judge whether BUSY signal is in busy state (whether being namely high level), if busy, wait for, otherwise the W signal of dual port RAM is set low (this signal Low level effective), the script data that then need write in order puts into I/O address section (address space range: 0x200f1000-0x200f1fff) corresponding to core, after pending data latches certain hour in bus, bottom layer driving will set high W signal automatically, thus terminates epicycle to the data writing operation of dual port RAM; PowerPC reads the operation of dual port RAM core and is mainly reflected in the data check stage, i.e. subordinate phase.With write operation in like manner, first the running status of BUSY is judged before PowerPC read data, after operation allows, R signal sets high by bottom layer driving, then the inner corresponding data of dual port RAM is read according to the random address produced, after digital independent completes, and R signal is resetted, terminate epicycle PowerPC read operation.Checking procedure, completes following operation according to the verification scheme that the present invention proposes: a) read the random address interior volume data that random function produces; B) corresponding data in the former pin file of comparison, and form matching result; C) terminal check conclusion is judged.
The shake hands particular content of criterion of powering on is: after PowerPC, FPGA electrifying startup, both first read the data of its appropriate address separately respectively, if the data of the data of this address and agreement do not possess consistance, then immediately to the address space write fixed number itself writing data, if when the data that both either party read are identical with appointment data, then terminate epicycle immediately and to power on handshake operation process.The design of this criterion of shaking hands, has fully taken into account real-time when this program performs, security and reliability, for follow-up date interworkmg has established solid foundation.The communications protocol detailed content in handshake procedure that powers on PowerPC and FPGA sees the following form shown in 4.
Table 4 powers on carrying out shake communication agreement
The particular content of service data verification scheme is: PowerPC software utilizes random function to produce 65 12 random seeds, then using these random seeds as sampling of data address, read its corresponding data in FPGA dual port RAM to compare with former data, all data from the sample survey that and if only if (65) comparison is success all, and Fang Ze is verified by service data; Otherwise do not pass through.In this verification scheme, 65 and 12 two values are selected to determine because of design in early stage and engineering experience as key factor, selection as 12 random seeds is the size depending on FPGA dual port RAM storage space, in other words, the setting of dual port RAM storage size has determined PowerPC only needs 12 address wires just can realize the complete traversal of 4096 address spaces.And the setting of 65 sampling addresses obtains according to sampling proportion empirical value in many project practice, in engineering in the past, can set by the factor of 1:1000 for the large sample of data volume (data that sample size is not less than 50000 are big-sample data) its sampling proportion.Based on this kind of design philosophy, after the verification of service data of the present invention calculates by the 1:1000 sampling proportion factor, can obtain its value is 65.
Step 6, real-time reception preserve the interrogation mode Variation control order that host computer initiatively sends, and in strict accordance with mode control commands time-to-live criterion, maintenance test is carried out to it, then be considered as invalid command to the control command not meeting this criterion to remove, thus terminate the process of epicycle digital coding, then allow it continue the preparation of the digitizing script data participating in step 7 to the control command meeting this criterion:
The fundamental purpose of setting up of mode control commands time-to-live criterion is the strict ageing and security controlled order and issue, thus improves the reliability and stability of secondary radar inquiry system further.Mode control commands adopts 100/1000Mbps network to issue in the present invention, and its time-to-live threshold value is 5.5s.The setting size of threshold value should decide according to the speed of command transfer medium.The particular content of mode control commands time-to-live criterion is: the mistiming that current time and control command generate is not more than the inquiry command time-to-live.The inquiry command time-to-live can be described as again inquiry command effective time, and its threshold value is 5.5 seconds in the present invention.The precondition that this criterion performs is the synchronous of time, namely requires that the time attribute information of each equipment of secondary radar system all comes from same time service source.
Step 7, according to change interrogation mode produce mode control data in real time, and write fix IO address:
Mode control data size is 1 byte, and it specifically defines and is shown in Table 5.
Table 5 secondary radar mode control data table
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EN 0 MD_En MB_En MC_En M3/A_En M2_En M1_En
Wherein EN is this byte enable position, represents that this control data is effective when being 1, otherwise 0 represents that this control bit is invalid; Bit5-Bit0 six bit data every all represents the enable bit of corresponding interrogation mode, and 1 represents that corresponding interrogation mode is effective, otherwise invalid.The fixing IO address of secondary radar mode control data write is 0x200f0004.
Step 8, FPGA select the script data of corresponding modes according to the mode control data of current write, and press output frequency by the output of data script, terminate the process of epicycle digital coding:
FPGA according to enable interrogation mode by data corresponding in dual port RAM with a fixing rate-adaptive pacemaker on final output signal line.Its output signal of the change of each pattern also should comprise transmitting door, GTC and the RECVGTC signal of change pattern.
The particular content of described output frequency is: output frequency and FPGA are by the output speed of the mode data of generation by discrete signal.The present invention is preferably 20MHZ.
By above-mentioned implementation method, can in real time, just clean, map function interrogation mode exactly, and export interrogation coding pulse efficiently according to its sequential relationship.In ground radar and airborne radar (being equipped with secondary radar equipment) during application, the switching efficiency of interrogation mode can be improved, strengthen the real-time of secondary radar equipment, reliability and stability, thus can further improve the war skill index of radar system, for the operational commanding of electronic tasks system synthesis and intelligent decision making commander establish reliable and stable basis.

Claims (10)

1. a secondary radar digitizing interrogation coding implementation method, is characterized in that: comprise the steps:
Communication mechanism between step one, structure FPGA and PowerPC;
Step 2, combing needed number content, layout data communication format;
Step 3, according to each pattern sequential relationship, formulate digitizing initial time with reference to criterion and mode digital data genaration criterion;
Step 4, work out the digital coding script file of all patterns;
Step 5, power on and read digital coding script file, and the script data that criterion of shaking hands according to powering on performs between PowerPC and FPGA is mutual, completes the verification of coded data according to service data verification scheme simultaneously;
Step 6, real-time reception preserve the interrogation mode Variation control order that host computer initiatively sends, and judge whether it meets mode control commands time-to-live criterion: if do not met, then be considered as invalid command to be removed, then terminate the process of epicycle digital coding; As met, then enter step 7;
Step 7, according to change interrogation mode produce mode control data in real time, and write fix IO address;
Step 8, FPGA select the script data of corresponding modes according to the mode control data of current write, and press output frequency by the output of data script, then terminate the process of epicycle digital coding.
2. secondary radar digitizing interrogation coding implementation method according to claim 1, it is characterized in that: the communication mechanism content described in step one between FPGA and PowerPC is: in FPGA, set up the dual port RAM memory that two bit wides are 8, the degree of depth is 2048, for the mode data after interactive digitizing.Wherein, PowerPC is responsible for its data write appropriate address, and FPGA is responsible for exporting after digital independent with the sample frequency of 20MHZ multiplying power.
3. secondary radar digitizing interrogation coding implementation method according to claim 1, is characterized in that: digitized content described in step 2 amounts to 14 signals, is respectively: M1, M2, M3/A, MC, MB and MD six kinds of patterns; M1_AM, M2_AM, M3/A_AM, MC_AM, MB_AM and MD_AM six kinds of Mode Launch doors; And RECGTC and GTC two kinds of gain time control signals.
4. secondary radar digitizing interrogation coding implementation method according to claim 1, it is characterized in that: data communication form described in step 2 refers to the communication format of the one-signal set up in conjunction with communication mechanism and digitized content, the value energy after often kind of signal digital and only can take dual port RAM bit wide.
5. secondary radar digitizing interrogation coding implementation method according to claim 1, is characterized in that: digitizing initial time described in step 3 refers to reference to criterion: often kind of mode digital initial time is all to push away 154us moment point for initial time reference point before P3 pulse front edge.
6. secondary radar digitizing interrogation coding implementation method according to claim 1, it is characterized in that: described in step 3, mode digital data genaration criterion refers to: according to the timing requirements of often kind of interrogation mode in " international civil aviation annex 10 ", take 50ns as digitizing least unit, the linear coded data producing often kind of pattern.
7. secondary radar digitizing interrogation coding implementation method according to claim 1, it is characterized in that: the criterion of shaking hands of powering on described in step 5 refers to: after PowerPC, FPGA electrifying startup, both first read the data of its appropriate address separately respectively, if the data of the data of this address and agreement do not possess consistance, then immediately to the address space write fixed number itself writing data, if when the data that both either party read are identical with appointment data, then terminate epicycle immediately and to power on handshake operation process.
8. secondary radar digitizing interrogation coding implementation method according to claim 1, it is characterized in that: described in step 5, service data verification scheme content is: PowerPC software utilizes random function to produce 65 12 random seeds, then using these random seeds as sampling of data address, read its corresponding data in FPGA dual port RAM to compare with former data, the whole comparison success of all data from the sample survey that and if only if, Fang Ze is verified by service data; Otherwise then do not pass through.
9. secondary radar digitizing interrogation coding implementation method according to claim 1, is characterized in that: the mode control commands time-to-live described in step 6, criterion content was: the mistiming that current time and control command generate is less than or equal to the inquiry command time-to-live.
10. secondary radar digitizing interrogation coding implementation method according to claim 1, is characterized in that: output frequency described in step 8 refers to that FPGA is by the output speed of the mode data of generation by discrete signal.
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CN108761409A (en) * 2018-07-19 2018-11-06 电子科技大学 A kind of generation of secondary radar signals and test method
CN108761409B (en) * 2018-07-19 2022-03-25 电子科技大学 Secondary radar signal generation and test method
RU2742943C1 (en) * 2020-05-12 2021-02-12 Российская Федерация, от имени которой выступает Министерство обороны Российской Федерации Radar interrogator with system of active phased arrays
CN112241281A (en) * 2020-10-14 2021-01-19 四川九洲空管科技有限责任公司 Digital radar TR component FPGA program batch upgrading method and system
CN112241281B (en) * 2020-10-14 2024-02-06 四川九洲空管科技有限责任公司 Batch upgrading method and system for digital radar TR (transmitter/receiver) module FPGA (field programmable Gate array) program

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