CN105489182A - 显示基板和显示装置 - Google Patents
显示基板和显示装置 Download PDFInfo
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
本发明涉及一种显示基板,包括公共电极线和多个像素单元,每个像素单元包括:像素电极,其中,所述像素电极连接至公共电极线;所述显示基板还包括:第一开关单元,设置在所述公共电极线和所述像素电极之间,在所述显示基板关机后的预设时间内导通,以导通所述公共电极线和像素电极,在所述显示基板开机时断开,以断开所述公共电极线和像素电极。通过第一开关单元可以在显示基板关机后的预设时间内将公共电极线和像素电极导通,使得关机后像素电极中存储的电荷都在公共电极线中进行中和,从而使得像素电极和公共电极可以通过相同的放电回路放电,保证了放电后的像素电极中无直流残留。
Description
技术领域
本发明涉及显示技术领域,具体而言,涉及一种显示基板和一种显示装置。
背景技术
传统复位电路在关机后将栅极驱动输出电压全拉到高电压(VGH),以便每行像素的TFT(薄膜晶体管)开启进行放电,但是由于所有行的TFT实际上无法同时开启,后开启的行像素接收到的VGH已经衰减,导致无法有效地进行放电。并且像素电极的电压在中和至公共电压后,最终的放电回路与公共电极的放电回路不同,通过不同回路放电会导致像素电极的放电速度慢于公共电极而造成直流残留,对于某些ADS(AdvancedSuperDimensionSwitch高级超维场)产品由于液晶电容较大,像素电极放电慢,极易造成开机闪烁漂移。
发明内容
本发明所要解决的技术问题是如何使得像素电极和公共电极通过相同的放电回路放电。
为此目的,本发明提出了一种显示基板,包括公共电极线和多个像素单元,每个像素单元包括:
像素电极,
其中,所述像素电极连接至公共电极线;
所述显示基板还包括:
第一开关单元,设置在所述公共电极线和所述像素电极之间,在所述显示基板关机后的预设时间内导通,以导通所述公共电极线和像素电极,在所述显示基板开机时断开,以断开所述公共电极线和像素电极。
优选地,每个像素单元还包括:
驱动晶体管,其中,所述驱动晶体管的驱动源极连接至数据线,所述驱动晶体管的驱动漏极连接至所述像素电极,所述驱动源极和驱动漏极在所述显示基板关机后的预设时间内导通,
其中,所述第一开关单元设置在所述数据线与所述公共电极线之间。
优选地,每个像素单元还包括:
第二开关单元,在所述显示基板关机后的预设时间内导通,以导通所述驱动晶体管的驱动栅极和所述像素电极,在所述显示基板开机时断开,以断开所述驱动栅极和所述像素电极。
优选地,上述显示基板还包括:
栅极驱动集成电路,所述栅极驱动集成电路在所述显示基板开机时,用于向所述驱动栅极传输扫描信号;
第三开关单元,设置在所述栅极驱动集成电路和所述驱动晶体管之间,所述第三开关单元在所述显示基板关机后的预设时间内断开,以断开所述栅极驱动集成电路和所述驱动晶体管,在所述显示基板开机时导通,以导通所述栅极驱动集成电路和所述驱动晶体管。
优选地,上述显示基板还包括:
控制单元,在所述显示基板关机后的预设时间内控制所述第一开关单元和第二开关单元导通,控制所述第三开关单元断开,
在所述显示基板开机时控制所述第一开关单元和第二开关单元断开,控制所述第三开关单元导通。
优选地,所述第一开关单元包括多个第一晶体管,每个第一晶体管的第一源极连接至公共电极线,每个第一晶体管的第一漏极分别连接一条数据线,每个第一晶体管的第一栅极分别连接至所述控制单元,
所述控制单元在所述显示基板关机后的预设时间内输出高电压,在所述显示基板开机时输出低电压。
优选地,所述第二开关单元包括第二晶体管,第二晶体管的第二源极连接至所述驱动栅极,第二晶体管的第二漏极连接至所述驱动漏极,第二晶体管的第二栅极连接至所述控制单元。
优选地,所述第三开关单元包括一个非门和多个第三晶体管,所述非门的输入端连接至所述控制单元,所述非门的输出端分别连接至每个第三晶体管的第三栅极,每个第三晶体管的第三源极分别连接至所述栅极驱动集成电路,每个第三晶体管的第三漏极分别连接至一条栅线。
优选地,所述第一开关单元和第三开关单元设置在外围电路中。
本发明还提出了一种显示装置,包括上述显示基板。
根据上述技术方案,通过第一开关单元可以在显示基板关机后的预设时间内将公共电极线和像素电极导通,使得关机后像素电极中存储的电荷都在公共电极线中进行中和,从而使得像素电极和公共电极可以通过相同的放电回路放电,保证了放电后的像素电极中无直流残留。
附图说明
通过参考附图会更加清楚的理解本发明的特征和优点,附图是示意性的而不应理解为对本发明进行任何限制,在附图中:
图1示出了根据本发明一个实施例的显示基板中的电路示意图;
图2为图1的局部放大示意图;
1-公共电极线;2-像素单元;20-像素电极;21-第一开关单元;22-第二开关单元;23-第三开关单元;24-驱动晶体管;3-数据线;4-栅极驱动集成电路;5-控制单元;6-数据信号集成电路。
具体实施方式
为了能够更清楚地理解本发明的上述目的、特征和优点,下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是,在不冲突的情况下,本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本发明,但是,本发明还可以采用其他不同于在此描述的其他方式来实施,因此,本发明的保护范围并不受下面公开的具体实施例的限制。
如图1所示,根据本发明一个实施例的显示基板包括公共电极线1和多个像素单元2,每个像素单元2包括:
像素电极20,
其中,像素电极20连接至公共电极线1;
显示基板还包括:
第一开关单元21,设置在公共电极线1和像素电极20之间,在显示基板关机后的预设时间内导通,以导通公共电极线和像素电极,在显示基板开机时断开,以断开公共电极线和像素电极。
需要说明的是,上述预设时间可以在显示基板的制作过程中设定好的时间值,也可以是在使用包含该显示基板的产品的过程中进行人为的修改和设定的时间值,例如该预设时间为0.1ms至10ms之间的一个时间值,具体时间值的大小由显示基板的放电速度决定。
本实施通过第一开关单元可以在显示基板关机后的预设时间内将公共电极线和像素电极导通,使得关机后每个像素单元中像素电极中存储的电荷都在公共电极线中进行中和,从而使得像素电极和公共电极可以通过相同的放电回路放电,保证了放电后的像素电极中无直流残留。
优选地,每个像素单元2还包括:
驱动晶体管24,其中,驱动晶体管的驱动源极连接至数据线3,驱动晶体管的驱动漏极连接至像素电极20,驱动源极和驱动漏极在显示基板关机后的预设时间内导通,
其中,第一开关单元21设置在数据线3与公共电极线1之间。
本实施例通过控制驱动晶体管在显示基板关机后的预设时间内导通,将像素电极中的电荷导入公共电极线,可以充分利用像素单元的原有结构作为像素电极和公共电极线之间的连接结构,减少对像素单元的调整。
优选地,每个像素单元2还包括:
第二开关单元22,在显示基板关机后的预设时间内导通,以导通驱动栅极和像素电极20,在显示基板开机时断开,以断开驱动栅极和像素电极20。
本实施例中的第二开关单元在导通时可以将像素电极的存储电荷传输至驱动晶体管的栅极,充分利用了关机后像素电极中的残留电荷来导通驱动晶体管。
需要说明的是,不同像素电极中残留电荷量可以不同,例如对于列反转的像素阵列,其中相邻列像素电极的残留电荷量不同,相邻列像素电极的电压分别为高电平和低电平,但是并不会存在负电压,因此在将像素电极与驱动晶体管的栅极导通时,像素电极即可在一段时间内向驱动晶体管的栅极提供开启电压,从而使得驱动晶体管的源极和漏极导通。
优选地,上述显示基板还包括:
栅极驱动集成电路4,栅极驱动集成电路4在显示基板开机时,用于向驱动栅极传输扫描信号;
第三开关单元23,设置在栅极驱动集成电路4和驱动晶体管24之间,第三开关单元23在显示基板关机后的预设时间内断开,以断开栅极驱动集成电路4和驱动晶体管24,在显示基板开机时导通,以导通栅极驱动集成电路4和驱动晶体管24。
由于第二开关单元在上述预设时间内导通了驱动晶体管的栅极和漏极,也即导通了栅线和像素电极,通过第三开关单元在显示基板关机后的预设时间内断开,可以避免栅极驱动集成电路中的电荷在上述预设时间内流入像素电极而对像素电极造成的损伤。
优选地,上述显示基板还包括:
控制单元5,在显示基板关机后的预设时间内控制第一开关单元21和第二开关单元22导通,控制第三开关单元23断开,
在显示基板开机时控制第一开关单元21和第二开关单元22断开,控制第三开关单元23导通。
本实施例通过一个控制单元可以统一控制第一开关单元、第二开关单元和第三开关单元的开关状态,便于简化电路布线。
优选地,第一开关单元21包括多个第一晶体管,每个第一晶体管的第一源极连接至公共电极线1,每个第一晶体管的第一漏极分别连接一条数据线3,每个第一晶体管的第一栅极分别连接至控制单元5,
控制单元5在显示基板关机后的预设时间内输出高电压,在显示基板开机时输出低电压。
本实施例中的控制单元在上述预设时间内向第一晶体管的栅极输出高电压,可以使得第一晶体管导通,从而将源极端的公共电极线与漏极端的数据线导通,进而将公共电极线和像素电极导通。
需要说明的是,本实施例中的数据线,可以是位于两列像素单元之间的用于向其中一列像素单元传输数据信号的数据线,也可以位于两列像素单元之间的向两列像素单元中间隔的像素单元传输数据信号的数据线(例如在双栅结构中,数据线向一列像素单元中的奇数像素单元传输数据信号,向另一列像素单元中的偶数像素单元传输数据信号)。
优选地,第二开关单元22包括第二晶体管,第二晶体管的第二源极连接至驱动栅极,第二晶体管的第二漏极连接至驱动晶体管24的漏极,第二晶体管的第二栅极连接至控制单元5。
控制单元在上述预设时间内向第二晶体管的栅极输出高电压,可以使得第二晶体管导通,从而将像素电极的电荷从驱动晶体管的漏极传输至源极,进而传输至驱动晶体管的栅极,以导通驱动晶体管。驱动晶体管漏极端像素电极的电荷通过源极导入数据线,再通过第一晶体管导入公共电极线。
由于一列像素电极连接于同一条数据线,而每条数据线在第一开关单元导通时均与公共电极线导通,从而使得每列像素电极中的电荷都导入公共电极线进行中和,并与公共电极线中的电荷通过同一回路导出,保证了放电后的每列像素电极中均无直流残留。
优选地,第三开关单元23包括一个非门和多个第三晶体管,非门的输入端连接至控制单元5,非门的输出端分别连接至每个第三晶体管的第三栅极,每个第三晶体管的第三源极分别连接至栅极驱动集成电路4,每个第三晶体管的第三漏极分别连接一条栅线。
需要说明的是,本实施例中的栅线,可以是位于两行像素单元之间的用于向其中一行像素单元传输扫描信号的栅线,也可以位于两行像素单元之间的向两行像素单元中间隔的像素单元传输扫描信号的栅线(例如栅线向一行像素单元中的奇数像素单元传输扫描信号,向另一行像素单元中的偶数像素单元传输扫描信号)。
在上述预设时间内,控制单元输出的高电压经过非门后变为低电压,从而保证第三晶体管断开,以避免栅极驱动集成电路中的电荷在上述预设时间内流入像素电极。同理,在显示基板开机(上电)后,控制单元输出的低电压经过非门后变为高电压,从而保证第三晶体管导通,以为像素单元正常提供扫描信号。
需要说明的是,上述第三开关单元除了可以由非门与多个NPN型的第三晶体管组成,也可以直接由多个PNP型的第三晶体管组成。
优选地,第一开关单元21和第三开关单元23设置在外围电路中。
外围电路可以是设置在边框与显示基板之间的电路,用于设置电源走线、栅极驱动集成电路4、数据信号集成电路6等。根据本实施例可以减少对像素区域的占用,提高有效发光面积。进一步地,可以将包含有第一开关单元21和第三开关单元23的外围电路设置为柔性电路,以便在将显示基板组装为显示装置时,将柔性电路弯折在显示基板的背面,从而减少对平面空间的占用。当然,控制单元5也可以设置在外围电路中以减少对像素区域的占用。
本发明还提出了一种显示装置,包括上述显示基板。
需要说明的是,本实施例中的显示装置可以为:电子纸、手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上结合附图详细说明了本发明的技术方案,考虑到现有技术中,像素电极与公共电极的放电回路不同,容易在像素电极中形成直流残留。根据本发明的技术方案,通过第一开关单元可以在显示基板关机后的预设时间内将公共电极线和像素电极导通,使得关机后像素电极中存储的电荷都在公共电极线中进行中和,从而使得像素电极和公共电极可以通过相同的放电回路放电,保证了放电后的像素电极中无直流残留。
在本发明中,术语“第一”、“第二”和“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性。术语“多”指大于或等于二,除非另有明确的限定。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种显示基板,包括公共电极线和多个像素单元,其特征在于,每个像素单元包括:
像素电极,
其中,所述像素电极连接至公共电极线;
所述显示基板还包括:
第一开关单元,设置在所述公共电极线和所述像素电极之间,在所述显示基板关机后的预设时间内导通,以导通所述公共电极线和像素电极,在所述显示基板开机时断开,以断开所述公共电极线和像素电极。
2.根据权利要求1所述的显示基板,其特征在于,每个像素单元还包括:
驱动晶体管,其中,所述驱动晶体管的驱动源极连接至数据线,所述驱动晶体管的驱动漏极连接至所述像素电极,所述驱动源极和驱动漏极在所述显示基板关机后的预设时间内导通,所述第一开关单元设置在所述数据线与所述公共电极线之间。
3.根据权利要求2所述的显示基板,其特征在于,每个像素单元还包括:
第二开关单元,在所述显示基板关机后的预设时间内导通,以导通所述驱动晶体管的驱动栅极和所述像素电极,在所述显示基板开机时断开,以断开所述驱动栅极和所述像素电极。
4.根据权利要求3所述的显示基板,其特征在于,还包括:
栅极驱动集成电路,所述栅极驱动集成电路在所述显示基板开机时,用于向所述驱动栅极传输扫描信号;
第三开关单元,设置在所述栅极驱动集成电路和所述驱动晶体管之间,所述第三开关单元在所述显示基板关机后的预设时间内断开,以断开所述栅极驱动集成电路和所述驱动晶体管,在所述显示基板开机时导通,以导通所述栅极驱动集成电路和所述驱动晶体管。
5.根据权利要求4所述的显示基板,其特征在于,还包括:
控制单元,在所述显示基板关机后的预设时间内控制所述第一开关单元和第二开关单元导通,控制所述第三开关单元断开,
在所述显示基板开机时控制所述第一开关单元和第二开关单元断开,控制所述第三开关单元导通。
6.根据权利要求5所述的显示基板,其特征在于,所述第一开关单元包括多个第一晶体管,每个第一晶体管的第一源极连接至公共电极线,每个第一晶体管的第一漏极分别连接一条数据线,每个第一晶体管的第一栅极分别连接至所述控制单元,
所述控制单元在所述显示基板关机后的预设时间内输出高电压,在所述显示基板开机时输出低电压。
7.根据权利要求5所述的显示基板,其特征在于,所述第二开关单元包括第二晶体管,第二晶体管的第二源极连接至所述驱动栅极,第二晶体管的第二漏极连接至所述驱动漏极,第二晶体管的第二栅极连接至所述控制单元。
8.根据权利要求5所述的显示基板,其特征在于,所述第三开关单元包括一个非门和多个第三晶体管,所述非门的输入端连接至所述控制单元,所述非门的输出端分别连接至每个第三晶体管的第三栅极,每个第三晶体管的第三源极分别连接至所述栅极驱动集成电路,每个第三晶体管的第三漏极分别连接一条栅线。
9.根据权利要求4至8中任一项所述的显示基板,其特征在于,所述第一开关单元和第三开关单元设置在外围电路中。
10.一种显示装置,其特征在于,包括权利要求1至9中任一项所述的显示基板。
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CN114667561B (zh) * | 2019-11-18 | 2024-01-05 | 伊英克公司 | 用于驱动电光显示器的方法 |
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US10204578B2 (en) | 2019-02-12 |
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