CN105487597A - Clock management method and device of central processing unit - Google Patents
Clock management method and device of central processing unit Download PDFInfo
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- CN105487597A CN105487597A CN201410528220.1A CN201410528220A CN105487597A CN 105487597 A CN105487597 A CN 105487597A CN 201410528220 A CN201410528220 A CN 201410528220A CN 105487597 A CN105487597 A CN 105487597A
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- clock
- cpu
- idleness
- clock frequency
- operating strategy
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
Abstract
The invention discloses a clock management method of a central processing unit. The clock management method comprises the following steps: obtaining a signal used for indicating the state of the CPU (Central Processing Unit), determining the vacancy rate of the CPU in a fixed period according to the signal used for indicating the state of the CPU, and managing a clock according to the vacancy rate and a pre-stored CPU clock management strategy. The invention also simultaneously discloses a clock management device of the central processing unit.
Description
Technical field
The present invention relates to computer technology, particularly relate to a kind of central microprocessor (CentralProcessingUnit, CPU) clock management method and device.
Background technology
In terminal device, the clock adjustable strategies of CPU is divided into static adjust strategy and dynamic conditioning strategy two kinds; Wherein, during by static adjust tactical management clock, the duty of CPU is divided into full speed operation state and turns off the low-power consumption duty two kinds of clock completely, according to actual needs for CPU provides suitable clock, can not can cause the waste of CPU power consumption.During by dynamic conditioning tactical management clock, need the frequency by software control CPU; On the one hand, when dynamic conditioning clock, CPU performs power managed software and can bring extra load to CPU self, reduces the energy-saving effect of dynamic conditioning frequency; On the other hand, based on the dynamic conditioning tactical management clock of software also exist requirement of real-time, the time delay that cannot meet cpu clock frequency adjustment long, under the application scenarios of complexity, realize the problems such as cost is very high.
Summary of the invention
In view of this, the embodiment of the present invention is expected to provide a kind of central microprocessor clock management method and device, according to the frequency of the load state dynamic conditioning cpu clock of CPU, can reduce the power consumption of CPU.
The technical scheme of the embodiment of the present invention is achieved in that
The embodiment of the present invention provides a kind of central microprocessor clock management method, described method comprises: the signal obtaining instruction central microprocessor CPU state, the idleness of CPU in the fixed cycle is determined, according to described idleness and the cpu clock operating strategy management clock prestored according to the signal of described instruction CPU state.
In above-mentioned implementation, described according to described idleness and the cpu clock operating strategy management clock prestored, comprise: the idleness scope that described idleness is corresponding with current clock frequency in described cpu clock operating strategy compares, time within the scope of the described idleness idleness that current clock frequency is corresponding in described cpu clock operating strategy, keep current clock frequency; Described idleness is greater than the upper of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and turns down clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy; Described idleness is less than the lower of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and heightens clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy.
In above-mentioned implementation, the described signal according to described instruction CPU state determines the idleness of CPU in the fixed cycle, comprise: within the fixed cycle, statistics instruction CPU state is the number of idle clock period, calculating described instruction CPU state is the idleness that the idle number of clock period and the ratio of described fixed cycle number obtain CPU.
In above-mentioned implementation, the described fixed cycle is the optimum value obtained according to practical application.
In above-mentioned implementation, before described management clock, described method also comprises: the enable switch opening clock frequency adjustment.
The embodiment of the present invention also provides a kind of central microprocessor Clock management device, and described device comprises: acquisition module, determination module and administration module; Wherein,
Described acquisition module, for obtaining the signal of instruction CPU state;
Described determination module, for determining the idleness of CPU in the fixed cycle according to the signal of described instruction CPU state;
Described administration module, for managing clock according to described idleness and the cpu clock operating strategy prestored.
In above-mentioned implementation, described administration module, compare specifically for the idleness scope that described idleness is corresponding with current clock frequency in described cpu clock operating strategy, time within the scope of the described idleness idleness that current clock frequency is corresponding in described cpu clock operating strategy, keep current clock frequency; Described idleness is greater than the upper of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and turns down clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy; Described idleness is less than the lower of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and heightens clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy.
In above-mentioned implementation, described determination module, specifically for adding up the number that instruction CPU state is the idle clock period within the fixed cycle, calculating described instruction CPU state is the idleness that the idle number of clock period and the ratio of described fixed cycle number obtain CPU.
In above-mentioned implementation, the described fixed cycle is the optimum value obtained according to practical application.
In above-mentioned implementation, described administration module, also for before management clock, opens the enable switch of clock frequency adjustment.
The central microprocessor clock management method that the embodiment of the present invention provides and device, obtain the signal of instruction CPU state, the idleness of CPU in the fixed cycle is determined, according to described idleness and the cpu clock operating strategy management clock prestored according to the signal of described instruction CPU state; So, by the load state dynamic conditioning cpu clock frequency according to CPU, critically adjust cpu clock frequency, reduce the power consumption of CPU; Extra load can not be brought for CPU by the management of hardware implementing cpu clock, improve energy-saving effect.
Accompanying drawing explanation
Fig. 1 is the treatment scheme schematic diagram based on software adjustment cpu clock frequency in prior art of the present invention;
Fig. 2 is the base conditioning schematic flow sheet of embodiment of the present invention central microprocessor clock management method;
Fig. 3 a-Fig. 3 c is that the clock frequency that the embodiment of the present invention is different adjusts clock frequency adjustment schematic diagram corresponding to span;
Fig. 4 is the detailed process schematic diagram of embodiment of the present invention central microprocessor clock management method;
Fig. 5 is the composition structural representation of embodiment of the present invention central microprocessor Clock management device.
Embodiment
In the embodiment of the present invention, obtain the signal of instruction central microprocessor CPU state, determine the idleness of CPU in the fixed cycle according to the signal of described instruction CPU state, according to described idleness and the cpu clock operating strategy management clock prestored.
For understanding the technical scheme of the embodiment of the present invention better, simply introduce the treatment scheme based on software adjustment cpu clock frequency in prior art below, as shown in Figure 1: be operating as step 101 to step 103 for what judge whether to need to carry out cpu clock frequency adjustment, perform by software, not only cannot meet the requirement of real-time of cpu clock adjustment, and energy-saving effect is poor.
The base conditioning flow process of embodiment of the present invention central microprocessor clock management method, as shown in Figure 2, comprises the following steps:
Step 101, obtains the signal of instruction CPU state;
Particularly, self-adaptation cpu clock management (AdaptiveCPUClockManagement, ACCM) module obtains the signal of the instruction CPU state that CPU exports;
Wherein, described CPU state comprises that CPU is idle and CPU is busy.
Step 102, determines the idleness of CPU in the fixed cycle according to the signal of described instruction CPU state;
Particularly, ACCM module adds up the number that instruction CPU state is the idle clock period within the fixed cycle, and calculating described instruction CPU state is the idleness that the idle number of clock period and the ratio of described fixed cycle number obtain CPU;
Wherein, the described fixed cycle is carry out testing the best fixed cycle value obtained according to the requirement of real-time of practical application, can be 1024 clock period or other values.
Step 103, according to described idleness and the cpu clock operating strategy management clock prestored;
Particularly, the idleness scope that described idleness is corresponding with current clock frequency in described cpu clock operating strategy compares by ACCM module, time within the scope of the described idleness idleness that current clock frequency is corresponding in described cpu clock operating strategy, keep current clock frequency; Described idleness is greater than the upper of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and turns down clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy; Described idleness is less than the lower of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and heightens clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy;
Here, can according to the continuous idleness calculated within multiple fixed cycle be all greater than idleness corresponding to current clock frequency the upper limit or be less than idleness corresponding to current clock frequency lower in limited time, then adjust clock frequency; So, the frequent adjustment of the clock frequency caused because cpu load is unstable can be avoided;
Wherein, described cpu clock operating strategy can be stored in register, described cpu clock operating strategy comprises: N number of clock frequency, and N is greater than the upper and lower bound of idleness corresponding to the positive integer of 1, each clock frequency, clock frequency adjustment span, the cycle of computation-free rate and the condition of adjustment clock frequency; Described clock frequency adjustment span refers to the frequency rank once adjusted when carrying out clock adjustment, that is: once adjust Primary Clock frequency, or once adjust multi-level clock frequency; If the corresponding gear of each clock frequency, comprise eight clock frequencies for cpu clock operating strategy, eight corresponding eight gears of clock frequency are gear 0, gear 1 to gear 7 respectively, the clock frequency of gear 0 correspondence is the highest, and the clock frequency of gear 7 correspondence is minimum; Can configure use eight gears, what also can configure in use eight gears is several arbitrarily; The clock frequency that different clock frequency adjustment spans is corresponding adjusts schematic diagram as shown in Figure 3, Fig. 3 a be clock frequency heighten span and clock frequency turn down the clock frequency adjustment schematic diagram that span is a gear, Fig. 3 b be clock frequency heighten that span is two gears, clock frequency turn down the clock frequency adjustment schematic diagram that span is a gear, Fig. 3 c be clock frequency heighten that span is three gears, clock frequency turn down the clock frequency adjustment schematic diagram that span is a gear; In actual applications, cpu clock operating strategy can set flexibly according to practical application.
After execution step 103, described method also comprises: when the cycle of the determination idleness in cpu clock operating strategy arrives, then perform step 101 to step 103; In the embodiment of the present invention, when determining that the cycle of idleness arrives, cpu clock frequency can be adjusted in real time.
In the embodiment of the present invention, described ACCM module can be positioned at the system comprising arbitrarily CPU, when the cpu frequency after clock frequency adjustment is different from other frequencies of described system, described in the embodiment of the present invention, central microprocessor clock management method also comprises: carry out synchronous or asynchronous process to other frequencies of cpu frequency and described system.
The base conditioning flow process of embodiment of the present invention central microprocessor clock management method, as shown in Figure 4, comprises the following steps:
Step 201, the starting clock frequency of ACCM block configuration CPU and cpu clock operating strategy;
Wherein, starting clock frequency and the described cpu clock operating strategy of described CPU are configured in register, described cpu clock operating strategy comprises: N number of clock frequency, and N is the condition being greater than the upper and lower bound of idleness corresponding to the positive integer of 1, each clock frequency, clock frequency adjustment span, the cycle determining idleness and adjustment clock frequency.
Step 202, opens the enable switch of clock frequency adjustment;
Here, when ACCM module opens the enable switch of clock frequency adjustment, start to manage cpu clock.
Step 203, obtains the signal of CPU state;
Particularly, ACCM module obtains the signal of the instruction CPU state that CPU exports;
Wherein, described CPU state comprises that CPU is idle and CPU is busy.
Step 204, determines the idleness of CPU in the fixed cycle according to the signal of described instruction CPU state;
Particularly, ACCM module adds up the number that instruction instruction CPU state is the idle clock period within the fixed cycle, and calculating described instruction CPU state is the idleness that the idle number of clock period and the ratio of described fixed cycle number obtain CPU;
Here, the described fixed cycle is 1024 clock period, calculates the idleness of CPU in the fixed cycle for three times and is respectively 35%, 36% and 39%.
Step 205, according to described idleness and the cpu clock operating strategy management clock prestored;
Here, calculate the idleness of CPU in the fixed cycle in the embodiment of the present invention for three times and be respectively 35%, 36% and 39%, in cpu clock operating strategy, the upper limit of the idleness that current clock frequency is corresponding is 30%, and clock frequency adjustment span is one-level; Therefore, the idleness calculating CPU in the fixed cycle for three times is all greater than the upper limit of the idleness that current clock frequency is corresponding in cpu clock operating strategy, and clock frequency is turned down one-level.
In the embodiment of the present invention, when the cycle of the determination idleness in cpu clock operating strategy arrives, perform step 203.
For realizing above-mentioned central microprocessor clock management method, the embodiment of the present invention also provides a kind of central microprocessor Clock management device, and the composition structure of described device as shown in Figure 5, comprising: acquisition module 11, determination module 12 and administration module 13; Wherein,
Described acquisition module 11, for obtaining the signal of instruction CPU state;
Described determination module 12, for determining the idleness of CPU in the fixed cycle according to the signal of described instruction CPU state;
Described administration module 13, for managing clock according to described idleness and the cpu clock operating strategy prestored.
In above-mentioned implementation, described administration module 13, compare specifically for the idleness scope that described idleness is corresponding with current clock frequency in described cpu clock operating strategy, time within the scope of the described idleness idleness that current clock frequency is corresponding in described cpu clock operating strategy, keep current clock frequency; Described idleness is greater than the upper of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and turns down clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy; Described idleness is less than the lower of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and heightens clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy;
In above-mentioned implementation, the idleness that repeatedly can calculate within the fixed cycle be all greater than idleness corresponding to current clock frequency the upper limit or be less than idleness corresponding to current clock frequency lower in limited time, then adjust clock frequency; So, the frequent adjustment of the clock frequency caused because cpu load is unstable can be avoided;
Wherein, described cpu clock operating strategy can be stored in register, described cpu clock operating strategy comprises: N number of clock frequency, and N is the condition being greater than the upper and lower bound of idleness corresponding to the positive integer of 1, each clock frequency, clock frequency adjustment span, the cycle determining idleness and adjustment clock frequency; Described clock frequency adjustment span refers to the frequency rank once adjusted when carrying out clock adjustment, that is: once adjust Primary Clock frequency, or once adjust multi-level clock frequency.
In above-mentioned implementation, described determination module 12, specifically for adding up the number that instruction CPU state is the idle clock period within the fixed cycle, calculating described instruction CPU state is the idleness that the idle number of clock period and the ratio of described fixed cycle number obtain CPU.
In above-mentioned implementation, the described fixed cycle is carry out testing the best fixed cycle value obtained according to the requirement of real-time of practical application, can be 1024 clock period or other values.
In above-mentioned implementation, described administration module 13, also for before management clock, opens the enable switch of clock frequency adjustment.
In the embodiment of the present invention, described central microprocessor Clock management device can be positioned at the system comprising arbitrarily CPU, when the cpu frequency after clock frequency adjustment is different from other frequencies of described system, described administration module 13, for carrying out synchronous or asynchronous process to intrasystem cpu frequency and other frequencies intrasystem.
It should be noted that, in actual applications, the function of described acquisition module 11, determination module 12 and administration module 13 can by being positioned at the intrasystem central processing unit (CPU) or microprocessor (MPU) or digital signal processor (DSP) or programmable gate array (FPGA) realization that comprise arbitrarily CPU.
The foregoing is only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.
Claims (10)
1. a central microprocessor clock management method, is characterized in that, described method comprises:
Obtain the signal of instruction central microprocessor CPU state;
The idleness of CPU in the fixed cycle is determined according to the signal of described instruction CPU state;
According to described idleness and the cpu clock operating strategy management clock prestored.
2. central microprocessor clock management method according to claim 1, is characterized in that, described according to described idleness and the cpu clock operating strategy management clock that prestores, comprising:
The idleness scope that described idleness is corresponding with current clock frequency in described cpu clock operating strategy compares, and time within the scope of the described idleness idleness that current clock frequency is corresponding in described cpu clock operating strategy, keeps current clock frequency;
Described idleness is greater than the upper of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and turns down clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy;
Described idleness is less than the lower of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and heightens clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy.
3. central microprocessor clock management method according to claim 1, is characterized in that, the described signal according to described instruction CPU state determines the idleness of CPU in the fixed cycle, comprising:
Within the fixed cycle, statistics instruction CPU state is the number of idle clock period, and calculating described instruction CPU state is the idleness that the idle number of clock period and the ratio of described fixed cycle number obtain CPU.
4. central microprocessor clock management method according to claim 1, is characterized in that, the described fixed cycle is the optimum value obtained according to practical application.
5. central microprocessor clock management method according to claim 1, it is characterized in that, before described management clock, described method also comprises: the enable switch opening clock frequency adjustment.
6. a central microprocessor Clock management device, is characterized in that, described device comprises: acquisition module, determination module and administration module; Wherein,
Described acquisition module, for obtaining the signal of instruction CPU state;
Described determination module, for determining the idleness of CPU in the fixed cycle according to the signal of described instruction CPU state;
Described administration module, for managing clock according to described idleness and the cpu clock operating strategy prestored.
7. central microprocessor Clock management device according to claim 6, it is characterized in that, described administration module, compare specifically for the idleness scope that described idleness is corresponding with current clock frequency in described cpu clock operating strategy, time within the scope of the described idleness idleness that current clock frequency is corresponding in described cpu clock operating strategy, keep current clock frequency;
Described idleness is greater than the upper of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and turns down clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy;
Described idleness is less than the lower of the idleness that in described cpu clock operating strategy, current clock frequency is corresponding and prescribes a time limit, and heightens clock frequency according to the clock frequency adjustment span in described cpu clock operating strategy.
8. central microprocessor Clock management device according to claim 6, it is characterized in that, described determination module, specifically for adding up the number that instruction CPU state is the idle clock period within the fixed cycle, calculating described instruction CPU state is the idleness that the idle number of clock period and the ratio of described fixed cycle number obtain CPU.
9. central microprocessor Clock management device according to claim 6, is characterized in that, the described fixed cycle is the optimum value obtained according to practical application.
10. central microprocessor Clock management device according to claim 6, is characterized in that, described administration module, also for before management clock, opens the enable switch of clock frequency adjustment.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410528220.1A CN105487597A (en) | 2014-10-09 | 2014-10-09 | Clock management method and device of central processing unit |
| PCT/CN2015/076704 WO2016054902A1 (en) | 2014-10-09 | 2015-04-16 | Central processing unit clock management method, apparatus and storage medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410528220.1A CN105487597A (en) | 2014-10-09 | 2014-10-09 | Clock management method and device of central processing unit |
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| CN105487597A true CN105487597A (en) | 2016-04-13 |
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| CN201410528220.1A Withdrawn CN105487597A (en) | 2014-10-09 | 2014-10-09 | Clock management method and device of central processing unit |
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| CN (1) | CN105487597A (en) |
| WO (1) | WO2016054902A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112214099A (en) * | 2020-10-16 | 2021-01-12 | 苏州浪潮智能科技有限公司 | Dynamic clock adjusting system and method based on single-core CPU idle indication |
| WO2021109534A1 (en) * | 2019-12-03 | 2021-06-10 | 深圳开立生物医疗科技股份有限公司 | Clock configuration method and system for controller, and ultrasonic equipment |
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| US20130290768A1 (en) * | 2012-04-25 | 2013-10-31 | Fujitsu Limited | Arithmetic processing device, method for controlling arithmetic processing device, and system |
| CN103488532A (en) * | 2013-09-02 | 2014-01-01 | 华为技术有限公司 | Method and equipment for adjusting processor frequency |
| CN103543982A (en) * | 2012-07-16 | 2014-01-29 | 安凯(广州)微电子技术有限公司 | Clock frequency management method and mobile device |
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| CN100334527C (en) * | 2003-12-15 | 2007-08-29 | 仁宝电脑工业股份有限公司 | Method for dynamically adjusting CPU frequency |
| CN101853066A (en) * | 2009-02-11 | 2010-10-06 | 上海芯豪微电子有限公司 | Method and device for automatically adjusting clock frequency of system in real time |
| CN102402270A (en) * | 2010-09-08 | 2012-04-04 | 鸿富锦精密工业（深圳）有限公司 | Method and system for regulating frequency of central processing unit |
| US8601298B2 (en) * | 2010-09-15 | 2013-12-03 | Qualcomm Incorporated | System and method for determining optimal operating parameters for conserving power in a portable device from a hypersurface which represents optimal values of the operating parameters under various synthetic workloads |
| JP6042217B2 (en) * | 2013-01-28 | 2016-12-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device, electronic device, and control method of semiconductor device |
| CN103345296B (en) * | 2013-06-04 | 2016-08-10 | 三星半导体(中国)研究开发有限公司 | Dynamic voltage frequency adjustment trigger device and method |
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| US20130290768A1 (en) * | 2012-04-25 | 2013-10-31 | Fujitsu Limited | Arithmetic processing device, method for controlling arithmetic processing device, and system |
| CN103543982A (en) * | 2012-07-16 | 2014-01-29 | 安凯(广州)微电子技术有限公司 | Clock frequency management method and mobile device |
| CN103488532A (en) * | 2013-09-02 | 2014-01-01 | 华为技术有限公司 | Method and equipment for adjusting processor frequency |
Cited By (2)
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| WO2021109534A1 (en) * | 2019-12-03 | 2021-06-10 | 深圳开立生物医疗科技股份有限公司 | Clock configuration method and system for controller, and ultrasonic equipment |
| CN112214099A (en) * | 2020-10-16 | 2021-01-12 | 苏州浪潮智能科技有限公司 | Dynamic clock adjusting system and method based on single-core CPU idle indication |
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| WO2016054902A1 (en) | 2016-04-14 |
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