CN105471441A - Coding method for LDPC codes - Google Patents

Abstract

The invention provides a coding method for LDPC codes. The coding method comprises the steps that all check bits corresponding to check parts are initialized; information bits in an LDPC matrix are grouped according to the size of loop submatrixes so that multiple information bit groups are obtained; all the check bits are processed according to different accumulative modes of the first information bit and other information bits in each information bit group based on a preset code table; the check bits belonging to the first check parts are processed according to a first processing mode so that coded first check parts are obtained; and then the coded first check parts are grouped according to the size of the loop submatrixes so that multiple check bit groups are obtained, and second check bit parts are processed according to different accumulative modes of the first check bit and other check bits in each check bit group so as to form coded check parts. Compared with codewords of the same bitrate in the existing standards, low-bitrate codewords put forward in the technical scheme have performance of being closer to aromatic limit.

Description

The coding method of LDPC code

Technical field

The present invention relates to coding method field, particularly a kind of coding method of LDPC code.

Background technology

Low density parity check codewords (LowdensityParityCheck, LDPC) mainly two classes can be divided into according to its structure, one class is random code word, the most classical surely belongs to MacKay code, and he also has special webpage to provide his various code words (MacKay1999) (Richardson2001) (Luby2001) (RichardsonandUrbanke2001); An other class is the code word designed based on algebraic combination structure (Combinatorial).Random code word extraordinaryly can approach shannon limit, but due to ' 1 ' randomness distributed, cause the design of the design of encoder and decoder not have parallel or regularity can follow, so be not suitable for needs to possess certain throughput systems, be not therefore also just widely used.

And the appearance of the LDPC code word of structure based well solves the problem of this respect, this wherein, a class is had to have good performance (Y.KouandS.Lin2001) based on the code word that finite field (FiniteGeometry) designs, but the shortcoming of this kind of code word is due to its H matrix density higher (large row is rearranged heavy), so when using the class algorithm based on belief propagation, complexity is very high.And another kind of quasi-cyclic code word (Quasi-cyclicLDPC, QC-LDPC) to be a class very important based on the code word of algebraic combination structure.The main structure of QC-LDPC code word is based on quasi-cyclic unit submatrix.(J.L.Fan2000) (R.M.Tanner2001) (R.M.Tanner2001) (T.Okamura2003) (R.M.Tanner2004) this quasi-cyclic unit submatrix structure is applicable to the hardware realizing parallel work-flow very much, the decoder of the large and then high-throughput of such as realization of decoding degree of parallelism.Although traditional this QC-LDPC code word is applicable to degree of parallelism, high decoder realizes, improve throughput, but the generator matrix being obtained QC structure by reverse method may not be sparse, even if or it is sparse, it is encoded with generator matrix, and to obtain check bit be not obvious, will by asking system of linear equations to obtain, the encoder of therefore traditional QC-LDPC code word or relative complex.In order to address this problem, structurized repeat accumulated code (the StructuredIrregularRepeatAccumulatorcode that first scholar Zhang and Ryan propose, S-IRA) LDPC code word (ZhangandRyan2006), this structure, while the realization being applicable to high parallel decoder, can complete coding with the method for unusual simple and effective.

This kind of codeword structure has following features, and the matrix part corresponding to information bit is made up of standard circulation submatrix, and the matrix part corresponding to check bit is made up of bidiagonal matrix.

Current S-IRA code word has been widely used in each large communication standard, mainly comprises, European second generation digital broadcast television transmission standard DVB series (ETSI, 2006, DVBT22009, DVB-C22009, DVB-NGH2012); IEEE802.11n WLAN standard (IEEE802.11n2009); IEEE802.11e wireless wide area network standard (IEEE802.16e2006); China Digital TV ground transmission standard (DTTB) (GB20600-2006); Mobile Multimedia Broadcasting (CMMB2006); The near-earth deep space communication system (CCSDS2007) of North America CCSDS; And the standard of some disk storage devices etc.

Analyze adopt in present newest standards structurized and repeat cumulative code, we find at middle high code check, the LDPC code word of this kind can design by means of density evolution theory or external information figure (EXIT), and shows the performance of approaching aromatic limit.But at low bit-rate, such as 1/5,1/4,1/3,1/2 code check such as grade, adopts structurized repetition accumulation structure can not well approach aromatic limit.

Summary of the invention

The problem that the present invention solves is in prior art, adopts structurized repetition accumulation structure can not well approach aromatic limit.

For solving the problem, the embodiment of the present invention provides a kind of coding method of LDPC code, comprises the steps:

Obtain the information bit in LDPC matrix based on the bit stream after message sink coding, and set the size of check part and the size of circulation submatrix in described LDPC matrix; Wherein, described check part comprises the first check part and the second check part;

Each check bit described in initialization corresponding to check part;

According to described circulation submatrix large young pathbreaker described in information bit carry out dividing into groups to obtain multiple group of information bits, wherein each group of information bits correspondence presets a line check bit address in code table;

A line check bit address corresponding with default code table in each group of information bits first information bit is processed check bit according to the first accumulate mode, and the check bit address of other information bits in each group of information bits according to correspondence is processed check bit according to the second accumulate mode, to obtain the check part after accumulation process;

Process according to the first processing mode for the check bit belonging to the first check part in the check part after accumulation process, to obtain the first check part after encoding; The first check part after coding divided into groups according to the size of circulation submatrix, to obtain multiple check bit group, wherein each check bit group correspondence presets a line check bit address belonging to described second check part in code table;

A line check bit address belonging to described second check part in first check bit in each check bit group and default code table is processed the second check part according to the first accumulate mode, and this row check bit address to the second check part of other check bits in each check bit group is processed this second check bit part according to the second accumulate mode, to obtain the second check part after encoding;

Based on the check part after the second check part composition coding after the first check part after described coding and coding.

Optionally, the number of described information bit is K, the size of described circulation submatrix is q*q; Information bit described in the described large young pathbreaker according to described circulation submatrix carries out dividing into groups to obtain multiple group of information bits and comprises: arranging described information bit is I=(λ ₀, λ ₁..., λ _k-1); Described information bit is one group with q bit in order carry out dividing into groups to obtain multiple group of information bits.

Optionally, described a line check bit address that the information bit of first in each group of information bits is corresponding with default code table is carried out process according to the first accumulate mode to check bit and is comprised:

Sequentially the information bit of first in each group of information bits is carried out mould 2 accumulation process to the check bit that corresponding row numeral in default code table is address respectively.

Optionally, describedly a line check bit address belonging to described second check part in first check bit in each check bit group and default code table carried out process according to the first accumulate mode to the second check part comprise:

Sequentially first check bit in each check bit group is carried out mould 2 accumulation process to the check bit belonging to the second check part that corresponding row numeral in default code table is address respectively.

Optionally, describedly other information bits in each group of information bits and default code table carried out process according to the second accumulate mode comprise:

Other information bits in each group of information bits are carried out accumulation process to the check bit according to y1 being address respectively, and wherein, the expression formula of y1 is:

$y1=\left\{\begin{array}{cc}(x1+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}1<M_1\\ M_1+\left\{(x1-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}1\&GreaterEqual;M_1\end{array}\right.$

Wherein, x1 refers to address that the check bit relevant to first information bit in each group of information bits is corresponding, Q ₁be the ratio of the size of the first verification and the size of circular matrix, Q ₂be the ratio of the size of the second check part and the size of circular matrix, M1 represents the number of the check bit of the first check part, M2 represents the check bit of the second check part number, i represent the sequence number of the information bit in group of information bits except first information bit, the number range of sequence number is between 1 to q-1.

Optionally, describedly other check bits in each check bit group carried out process according to the second accumulate mode to the second check bit part according to the check bit address of correspondence comprise:

Other check bits in each check bit group are carried out accumulation process to the check bit according to y2 being address respectively, and wherein, the expression formula of y2 is:

$y2=\left\{\begin{array}{cc}(x2+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}2<M_1\\ M_1+\left\{(x2-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}2\&GreaterEqual;M_1\end{array}\right.$

Wherein, x2 refers to address that the check bit relevant to first check bit in each check bit group is corresponding, Q ₁be the ratio of the size of the first check part and the size of circular matrix, Q ₂be the ratio of the size of the second check part and the size of circular matrix, M1 represents the number (size) of the check bit of the first check part, M2 represents the check bit of the second check part number (size), i represent the sequence number of the check bit in each check bit group except first check bit (sequence number is 0), the number range of sequence number is between 1 to q-1.

Optionally, the code check of described default code table is 1/3; Code length n=57600; Information bit k=19200, the size m=38400 of check part, wherein the size of the first check part is M1=1280, the size of the second check part is M2=37120; The size q=320 of circular matrix; Q1=M1/q=4; Q2=M2/q=116.This default code table is:

Wherein, the check bit address belonging to described second check bit part is that the last Q1 in described default code table is capable, and wherein Q1 determines according to the ratio of the size of the first check part and the size of circular matrix.

Optionally, the described check bit for belonging to the first check part in the check part after accumulation process processes according to the first processing mode, refers to obtain the first check part after encoding:

The check bit belonging to the first check part in check part after accumulation process is processed according to formula.

Compared with prior art, technical solution of the present invention has following beneficial effect:

By a large amount of analogue simulation, find that the code word of the low bit-rate that the embodiment of the present invention proposes has than the performance of the same rate codewords in existing newest standards closer to aromatic limit.

Accompanying drawing explanation

Fig. 1 is the schematic flow sheet of the embodiment of the coding method of a kind of LDPC code of the present invention;

embodiment

Inventor finds in prior art, adopts structurized repetition accumulation structure can not well approach aromatic limit.

For the problems referred to above, inventor, through research, provides a kind of coding method of LDPC code, by a large amount of analogue simulation, finds that the code word of the low bit-rate that the embodiment of the present invention proposes has than the performance of the same rate codewords in existing newest standards closer to aromatic limit.

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.

As shown in Figure 1 be the schematic flow sheet of the embodiment of the coding method of a kind of LDPC code of the present invention.With reference to figure 1, this coding method comprises the steps:

Step S1: obtain the information bit in LDPC matrix based on the bit stream after message sink coding, and set the size of check part and the size of circulation submatrix in described LDPC matrix; Wherein, described check part comprises the first check part and the second check part;

Step S2: each check bit described in initialization corresponding to check part;

Step S3: according to described circulation submatrix large young pathbreaker described in information bit carry out dividing into groups to obtain multiple group of information bits, wherein each group of information bits correspondence presets a line check bit address in code table;

Step S4: a line check bit address corresponding with this group of information bits in default code table for the information bit of first in each group of information bits is processed check bit according to the first accumulate mode, and the check bit address of other information bits in each group of information bits according to correspondence is processed check bit according to the second accumulate mode, to obtain the check part after accumulation process;

Step S5: process according to the first processing mode for the check bit belonging to the first check part in the check part after accumulation process, to obtain the first check part after encoding;

Step S6: the first check part after coding is divided into groups according to the size of circulation submatrix, to obtain multiple check bit group, wherein each check bit group correspondence presets a line check bit address belonging to described second check part in code table;

Step S7: a line check bit address belonging to described second check part in first check bit in each check bit group and default code table is processed the second check part according to the first accumulate mode, and other check bits in each check bit group are processed the second check bit part according to the second accumulate mode according to the check bit address of correspondence, to obtain the second check part after encoding;

Step S8: based on the check part after the second check part composition coding after the first check part after described coding and coding.

Be described below in conjunction with the execution mode of specific embodiment to above-mentioned coding method.

As described in as described in step S1, obtain the information bit in LDPC matrix based on the bit stream after message sink coding, and set the size of check part and the size of circulation submatrix in described LDPC matrix; Wherein, described check part comprises the first check part and the second check part.

Described LDPC matrix comprises information bit part and check part.

The code word of LDPC is made to be c=(λ ₀, λ ₁..., λ _k-1, p ₀, p ₁..., p _m..., p _m-1); Wherein, (λ ₀, λ ₁..., λ _k-1) be information bit bit, be known { 1,0} sequence.(p ₀, p ₁, p ₂..., p _m-1) be check bit, be bit to be calculated.

In the present embodiment, in described LDPC matrix, the check bit of check part has M, comprises the first check part M1 and the second check part M2, i.e. M=M1+M2.The size of circulation submatrix is q*q.Usual described check part is positioned at the right-hand component of described low-density parity check (LDPC) matrix.

As described in step S2, each check bit described in initialization corresponding to check part.In the present embodiment, the initial value of each check bit corresponding to described check part is 0.

As described in step S3, according to described circulation submatrix large young pathbreaker described in information bit carry out dividing into groups to obtain multiple group of information bits, wherein each group of information bits correspondence presets a line check bit address in code table.

This step comprises:

1) arranging described information bit is I=(λ ₀, λ ₁..., λ _k-1);

2) described information bit is one group with q bit in order to carry out dividing into groups to obtain multiple group of information bits.

As described in step S4, a line check bit address corresponding with default code table in each group of information bits first information bit is processed check bit according to the first accumulate mode, and the check bit address of other information bits in each group of information bits according to correspondence is processed check bit according to the second accumulate mode, to obtain the check part after accumulation process.

Particularly, described a line check bit address that the information bit of first in each group of information bits is corresponding with default code table is carried out process according to the first accumulate mode to check bit and is comprised:

Sequentially the information bit of first in each group of information bits is carried out mould 2 accumulation process to the check bit that corresponding row numeral in default code table is address respectively.

Describedly other information bits in each group of information bits and default code table carried out process according to the second accumulate mode comprise:

Other information bits in each group of information bits are carried out accumulation process to the check bit according to y1 being address respectively, and wherein, the expression formula of y1 is:

$y1=\left\{\begin{array}{cc}(x1+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}1<M_1\\ M_1+\left\{(x1-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}1\&GreaterEqual;M_1\end{array}\right.$

Wherein, x1 refers to the address that the check bit relevant to first information bit in each group of information bits is corresponding, a line check bit address be in default code table corresponding to this group information bit, Q ₁be the ratio of the size of the first verification and the size of circular matrix, Q ₂be the ratio of the size of the second check part and the size of circular matrix, M1 represents the number of the check bit of the first check part, M2 represents the check bit of the second check part number, i represent the sequence number of other information in group of information bits except first information bit, value is between 1 to q-1.

The code check of described default code table is 1/3; Code length n=57600; Information bit k=19200, the size m=38400 of check part, wherein the size of the first check part is M1=1280, the size of the second check part is M2=37120; The size q=320 of circular matrix; Q1=M1/q=4; Q2=M2/q=116.This default code table is:

Wherein, the check bit address belonging to described second check bit part is that the last Q1 in described default code table is capable, and wherein Q1 determines according to the ratio of the size of the first check part and the size of circular matrix.

As described in step S5, process according to the first processing mode for the check bit belonging to the first check part in the check part after accumulation process, to obtain the first check part after encoding.

Particularly, this step refers to: for belonging to the check bit of the first check part in the check part after accumulation process according to formula process.

As described in step S6, the first check part after coding divided into groups according to the size of circulation submatrix, to obtain multiple check bit group, wherein each check bit group correspondence presets a line check bit address belonging to described second check part in code table.

Particularly, this step is similar to the process dividing into groups to obtain multiple group of information bits in above-mentioned steps S3 to information bit.It should be noted that each check bit group correspondence obtained presets a line check bit address belonging to described second check part in code table.

Such as, with reference to above-mentioned default code table, in this code table, last 4 row (i.e. the ratio of the size M1=1280 of the first check part and the size q=320 of circulation submatrix) are for belonging to the check bit address of described second check part.

As described in step S7, a line check bit address belonging to described second check part in first check bit in each check bit group and default code table is processed the second check part according to the first accumulate mode, and other check bits in each check bit group are processed the second check bit part according to the second accumulate mode according to the check bit address of correspondence, to obtain the second check part after encoding.

Particularly, a line check bit address belonging to described second check part in first check bit in each check bit group and default code table is carried out process according to the first accumulate mode to the second check part to comprise: sequentially first check bit in each check bit group is carried out mould 2 accumulation process to the check bit belonging to the second check part that corresponding row numeral in default code table is address respectively.

Describedly other check bits in each check bit group carried out process according to the second accumulate mode to the second check bit part according to the check bit address of correspondence comprise:

Other check bits in each check bit group are carried out accumulation process to the check bit according to y2 being address respectively, and wherein, the expression formula of y2 is:

$y2=\left\{\begin{array}{cc}(x2+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}2<M_1\\ M_1+\left\{(x2-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}2\&GreaterEqual;M_1\end{array}\right.$

Wherein, x2 refers to address that the check bit relevant to first check bit in each check bit group is corresponding, Q ₁be the ratio of the size of the first check part and the size of circular matrix, Q ₂be the ratio of the size of the second check part and the size of circular matrix, M1 represents the number of the check bit of the first check part, M2 represents the check bit of the second check part number, i represent the sequence number of the check bit in each check bit group except first check bit, the number range of sequence number is between 1 to q-1.

As described in step S8, based on the check part after the second check part composition coding after the first check part after described coding and coding.

Based on the coding method of above-mentioned LDPC code, inventor through providing an instantiation, and carries out analogue simulation.This instantiation is as follows:

By the bit stream after message sink coding, be split as block of information one by one, each block of information is made up of K information bit, is expressed as I=(λ ₀, λ ₁..., λ _k-1).

LDPC coding is exactly will according to I=(λ ₀, λ ₁..., λ _k-1) generate M ₁+ M ₂individual check bit $P=(p_0,p_1,...,p_{M_1+M_2-1})$

Namely the code word of N number of bit is obtained $\mathrm{\&Lambda;}=({\mathrm{\&lambda;}}_0,{\mathrm{\&lambda;}}_1,...,{\mathrm{\&lambda;}}_{K-1},p_0,p_1,...,p_{M_1+M_2-1}),$

First, according to the message bit stream initialization λ of input _i, i=0,1 ..., K-1.By complete zero mode initialization p _j=0, j=0,1 ..., M ₁+ M ₂-1

To information bit λ ₀, the check bit being address with the first row numeral in code table 1 (default code table namely mentioned above) is added up, because its first row numeral is:

6316561118608515617260262686531290330913502535420

$p_{631.}=p_{631}\&CirclePlus;{\mathrm{\&lambda;}}_0,p_{656}=p_{656}\&CirclePlus;{\mathrm{\&lambda;}}_0,p_{1118}=p_{1118}\&CirclePlus;{\mathrm{\&lambda;}}_0,......,$ $p_{35025}=p_{35025}\&CirclePlus;{\mathrm{\&lambda;}}_0,p_{35420}=p_{35420}\&CirclePlus;{\mathrm{\&lambda;}}_0$

For ensuing q-1 (such as, q=320) individual information bit, λ _m, i=1,2 ...., q-1, adds up with the check bit according to following y being address respectively by each information bit:

$y=\left\{\begin{array}{cc}(x+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}<M_1\\ M_1+\left\{(x-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}\&GreaterEqual;M_1\end{array}\right.$

Wherein, x refers to and λ ₀relevant check digit address, the numeral with reference to the first row in code table 1, x and code table 1:

6316561118608515617260262686531290330913502535420

Wherein $Q_1=\frac{M_1}{q}{Q}_2=\frac{M_2}{q}$

Such as, $Q_1=\frac{M_1}{q}=\frac{1280}{320}=4,Q_2=\frac{M_2}{q}=\frac{37120}{320}=116.$

$p_{635.}=p_{635}\&CirclePlus;{\mathrm{\&lambda;}}_1,p_{660}=p_{660}\&CirclePlus;{\mathrm{\&lambda;}}_1,p_{1122}=p_{1122}\&CirclePlus;{\mathrm{\&lambda;}}_1,......,$ $p_{35141}=p_{35141}\&CirclePlus;{\mathrm{\&lambda;}}_1,p_{35536}=p_{35536}\&CirclePlus;{\mathrm{\&lambda;}}_1$

For q information bit λ _q(i.e. first information bit of second group of information bits), adds up to check bit according to the second line number word address in code table 1.Same continues to add up to check bit according to the formula in step 4 described in Fig. 1 for other q-1 information bit in the second group of information bits.It should be noted that, in the formula now in described step 4, the numeric address of the second row in x and code table 1.

In like manner, for 2q, 3q, 4q ... iq ... individual information bit, respectively according to the 3rd row in code table 1, the 4th row, the 5th row ..., (i+1) row numeric address check bit is added up, and other q-1 information bit in each group of information bits adds up to check bit according to the formula in above-mentioned steps 4 respectively.Similar, row in the code table 1 that what the x in the formula now in described step 4 was corresponding is corresponding to a current i-th q information bit, q-1 bit after such as the i-th q information bit, when it adopts the formula in above-mentioned steps 4, the address of corresponding x be (i+1) in code table OK.

Then, utilize following formula to process the Part I check bit after accumulation process, to obtain the Part I check bit after encoding.

$\left\{\begin{array}{cc}{p}_i=p_i\&CirclePlus;p_{i-1}& \mathrm{ifi}\&le;M_1-1\\ p_i=p_i& \mathrm{else}\end{array}\right.$

Afterwards by the Part I check bit after coding be one group according to q bit to divide into groups, obtain Q1 group check bit, Q1=4.(the information Q1=M1/q=4 according to the present embodiment code table provides)

These 4 groups of Part I check bits distinguish the last 4 line number words in correspondence code table in order.These last 4 line number words correspond to the address of Part II check bit.

Then by first check bit in each check bit group according to a line address in the code table of this group correspondence, mould 2 is carried out to Part II check bit and adds up.

For example, first group of check bit is P=(p ₀, p ₁..., p _q-1), its corresponding numeral

13877195128721448322892250542707631340

Then, by p0, the check bit belonging to the second check part being address with this line number word is added up:

13877195128721448322892250542707631340

$p_{1387}=p_{1387}\&CirclePlus;p_0,p_{7195}=p_{7195}\&CirclePlus;p_0,...,p_{31340}=p_{31340}\&CirclePlus;p_0$

Then for the bit removed in first group of check bit outside first bit according to same as under type

$y=\left\{\begin{array}{cc}(x+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}<M_1\\ M_1+\left\{(x-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}\&GreaterEqual;M_1\end{array}\right.$

Carry out mould 2 to the bit belonging to the second check part taking y as address to add up.Wherein, x here refers to and p ₀relevant check digit address, with reference to code table, inverse the 4th line number word in x and code table 1:

13877195128721448322892250542707631340 with p ₁for example, at this time i=1,

$p_{1503}=p_{1503}\&CirclePlus;p_1,p_{7311}=p_{7311}\&CirclePlus;p_1,...,p_{31456}=p_{31456}\&CirclePlus;p_1$

To remaining (p ₂, p ₃..., p _q-1), make i=2 respectively, 3 ... q-1, substitutes into formula, obtains y, carries out mould 2 in the same way respectively add up to the check bit belonging to the second check part.

Same for the 2nd group, the 3rd, 4 group of check bit, carry out mould 2 according to same mode to the check bit belonging to the second check part and add up, different has just changed a line address.For example, the address belonging to the second check part that the 2nd group of check bit is corresponding is

350010667164752215223763321723433436356

The address belonging to the second check part that 3rd group of check bit is corresponding is:

4332649485161278019947257553143233043

The 4th group of address belonging to the second check part verifying special bit corresponding is:

35925203136121577417796220602922735035

Namely finally obtain after all operations complete after coding $P=(p_0,p_1,...,p_{M_1+M_2-1}).$

In conjunction with given information bit, finally obtain the LDPC code word after coding $\mathrm{\&Lambda;}=(s_0,s_1,...,s_{K-1},p_0,p_1,...,p_{M_1+M_2-1}).$ Namely LDPC has encoded.

Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.

Claims (8)

1. a coding method for LDPC code, is characterized in that, comprises the steps:

Obtain the information bit in LDPC matrix based on the bit stream after message sink coding, and set the size of check part and the size of circulation submatrix in described LDPC matrix; Wherein, described check part comprises the first check part and the second check part;

Each check bit described in initialization corresponding to check part;

According to described circulation submatrix large young pathbreaker described in information bit carry out dividing into groups to obtain multiple group of information bits, wherein each group of information bits correspondence presets a line check bit address in code table;

A line check bit address corresponding with default code table in each group of information bits first information bit is processed check bit according to the first accumulate mode, and the check bit address of other information bits in each group of information bits according to correspondence is processed check bit according to the second accumulate mode, to obtain the check part after accumulation process;

Process according to the first processing mode for the check bit belonging to the first check part in the check part after accumulation process, to obtain the first check part after encoding;

The first check part after coding divided into groups according to the size of circulation submatrix, to obtain multiple check bit group, wherein each check bit group correspondence presets a line check bit address belonging to described second check part in code table;

A line check bit address belonging to described second check part in first check bit in each check bit group and default code table is processed the second check part according to the first accumulate mode, and this row check bit address to the second check part of other check bits in each check bit group is processed this second check bit part according to the second accumulate mode, to obtain the second check part after encoding;

Based on the check part after the second check part composition coding after the first check part after described coding and coding.

2. the coding method of LDPC code as claimed in claim 1, is characterized in that, the number of described information bit is K, the size of described circulation submatrix is q*q;

Information bit described in the described large young pathbreaker according to described circulation submatrix carries out dividing into groups to obtain multiple group of information bits and comprises:

Arranging described information bit is I=(λ ₀, λ ₁..., λ _k-1);

Described information bit is one group with q bit in order carry out dividing into groups to obtain multiple group of information bits.

3. the coding method of LDPC code as claimed in claim 1, it is characterized in that, described a line check bit address that the information bit of first in each group of information bits is corresponding with default code table is carried out process according to the first accumulate mode to check bit and is comprised:

Sequentially the information bit of first in each group of information bits is carried out mould 2 accumulation process to the check bit that corresponding row numeral in default code table is address respectively.

4. the coding method of LDPC code as claimed in claim 1, it is characterized in that, describedly a line check bit address belonging to described second check part in first check bit in each check bit group and default code table is carried out process according to the first accumulate mode to the second check part comprise:

Sequentially first check bit in each check bit group is carried out mould 2 accumulation process to the check bit belonging to the second check part that corresponding row numeral in default code table is address respectively.

5. the coding method of LDPC code as claimed in claim 1, is characterized in that, describedly other information bits in each group of information bits and default code table are carried out process according to the second accumulate mode comprises:

Other information bits in each group of information bits are carried out accumulation process to the check bit according to y1 being address respectively, and wherein, the expression formula of y1 is:

$y1=\left\{\begin{array}{cc}(x1+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}1<M_1\\ M_1+\left\{(x1-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}1\&GreaterEqual;M_1\end{array}\right.$

Wherein, x1 refers to address that the check bit relevant to first information bit in each group of information bits is corresponding, Q ₁be the ratio of the size of the first check part and the size of circular matrix, Q ₂be the ratio of the size of the second check part and the size of circular matrix, M1 represents the number of the check bit of the first check part, M2 represents the check bit of the second check part number, i represent the sequence number of the information bit in each group of information bits except first information bit, the number range of sequence number is between 1 to q-1.

6. the coding method of LDPC code as claimed in claim 1, is characterized in that, describedly other check bits in each check bit group are carried out process according to the second accumulate mode to the second check bit part according to the check bit address of correspondence comprises:

Other check bits in each check bit group are carried out accumulation process to the check bit according to y2 being address respectively, and wherein, the expression formula of y2 is:

$y2=\left\{\begin{array}{cc}(x2+i\&times;Q_1)\mathrm{mod}{M}_1& \mathrm{ifx}2<M_1\\ M_1+\left\{(x2-M_1+i\&times;Q_2)\mathrm{mod}{M}_2\right\}& \mathrm{ifx}2\&GreaterEqual;M_1\end{array}\right.$

Wherein, x2 refers to address that the check bit relevant to first check bit in each check bit group is corresponding, Q ₁be the ratio of the size of the first check part and the size of circular matrix, Q ₂be the ratio of the size of the second check part and the size of circular matrix, M1 represents the number of the check bit of the first check part, M2 represents the check bit of the second check part number, i represent the sequence number of the check bit in each check bit group except first check bit, the number range of sequence number is between 1 to q-1.

7. the coding method of LDPC code as claimed in claim 1, it is characterized in that, the code check of described default code table is 1/3; Code length n=57600; Information bit k=19200, the size m=38400 of check part, wherein the size of the first check part is M1=1280, the size of the second check part is M2=37120; The size q=320 of circular matrix; Q1=M1/q=4; Q2=M2/q=116.This default code table is:

Wherein, the check bit address belonging to described second check bit part is that the last Q1 in described default code table is capable, and wherein Q1 equals the ratio of the size of the first check part and the size of circular matrix.

8. the coding method of LDPC code as claimed in claim 1, it is characterized in that, the described check bit for belonging to the first check part in the check part after accumulation process processes according to the first processing mode, refers to obtain the first check part after encoding:

For belonging to the check bit of the first check part in the check part after accumulation process according to formula process.