CN105469826B - A kind of flash memory and its control method - Google Patents
A kind of flash memory and its control method Download PDFInfo
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- CN105469826B CN105469826B CN201410465841.XA CN201410465841A CN105469826B CN 105469826 B CN105469826 B CN 105469826B CN 201410465841 A CN201410465841 A CN 201410465841A CN 105469826 B CN105469826 B CN 105469826B
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Abstract
The invention discloses a kind of flash memory and its control methods, the flash memory includes a big sector storage array and a small sector storage array, the big sector storage array and the small sector storage array are integrated to same storage array, the big sector storage array includes N bit line of column direction, M wordline of line direction and a source line, the small sector storage array column direction includes N bit line, it is divided into n group from column direction by the wordline of line direction and source line, every group includes a M/n wordline WL and source line SL, row decoding and level displacement circuit by word line driving circuit connect the M wordline, n source pullup drive circuit passes through the storage unit of the n source line connection each group respectively, the present invention is by removing small sector source line drop-down unit, so that in the case where not wasting area, realize bit line alignment, The electric current of small sector is back to ground by idle bit line.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, more particularly to a kind of flash memory and its control method.
Background technique
Since system on chip circuit is complicated, needing may be different using the possible more and sector-size of circuit of flash memory,
When the system integration, need to integrate the inconsistent storage array of these sector-sizes with share array decoding circuit, due to
Storage array is usually all located in a rectangular area, and the X-direction width of the small storage array in sector is necessarily narrower, in order to
It is aligned bit line, new storage array always still places storage unit in small sector array part after integrating, but does not use actually
These storage units, this segment chip area loss are serious.
Fig. 1 is that the flash array of different sectors size under a prior art integrates schematic diagram.Wherein, big array sector is
There are 4 wordline WL0/1/2/3_C, 1 source line SL_C and 1024 bit line BL0~BL1023 in 512 bytes, every sector, i.e., often
Row has 128 bytes (byte), and left side is corresponding row decoding and level shift circuit, wordline driving, source line pulling drive and source line
Drop-down driving；Small array sector be 64 bytes, every sector equally place 4 wordline WL0/1/2/3_D, 1 source line SL_D and
1024 bit line BL0~BL1023, every row equally have 128 bytes (byte), but the row that wordline WL0_D is controlled is used only
BL0~BL511 is used only in half, i.e. bit line, other storage units all do not use, and left side array is similarly corresponding row decoding and electricity
Translational shifting circuit, wordline driving, source line pulling drive and the drop-down driving of source line.
Exemplary source line decoding circuit (source line pulling drive and source line drop-down driving) is as shown in Figure 2.The pulling drive includes
One PMOS tube and a NMOS tube, control signal SEL connect the grid of the PMOS tube and NMOS tube, and PMOS tube source electrode connects high pressure
VSL, NMOS tube source electrode ground connection, the drain electrode of the PMOS tube and NMOS tube are source line SL；Drop-down driving is large-sized comprising one
NMOS tube, read control signal RDEN connect the grid of the NMOS tube, and NMOS tube source electrode ground connection, the drain electrode of the NMOS tube connects source line
SL.When operating to storage unit a, Y decoding circuit (column decoding is not shown) chooses bit line BLn, X decoding circuit (row decoding)
Selected word line WL, while line decoding in source exports setting voltage to SL, typical reading, programmed and erased voltage are as shown in table 1.Erasing
When, wordline WL adds 12V high pressure, and bit line BLn and source line SL connect 0V low pressure, and the high-intensity magnetic field that High Pressure Difference is formed draws the electronics on floating gate
It walks all to remove the information of storage unit and (correspond to high level " 1 " after general erasing)；When programming, wordline WL adds 1.5V electric
Pressure, bit line BLn export 0.3V low-voltage, and 8V high pressure is connected to source line SL to be low by SEL, and storage unit a forms source line SL and (connects source
Pole) to the electric current of bit line BLn (connecing drain electrode), while to the electrically realized write-in " 0 " in the memory unit of floating gate injection, (one writing is not
It operates)；When reading, wordline WL adds 2.5V voltage, and bit line BLn exports 0.8V voltage, and RDEN is that height connects source line SL with being pulled to
0V, storage unit a form bit line BLn (connecing drain electrode) to the electric current of source line SL (connecing source electrode), which passes through drop-down driving metal-oxide-semiconductor
Flow back into ground.
1 conventional flash memory storage unit of table reads and writes erasing voltage
| Storage unit Cell a | Read voltage | Program voltage | Erasing voltage |
| Wordline WL | 2.5 | 1.5 | 12 |
| Selection signal SL | 0 | 8 | 0 |
| Bit line BLn | 0.8 | 0.3 | 0 |
As it can be seen that conventional flash memory array architecture, the storage array of the sector of size different for two is integrated into same
In storage array, in order to be aligned bit line, chip area is wasted than more serious.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, one of present invention be designed to provide a kind of flash memory and its
Control method, by removing small sector source line drop-down unit, so that bit line alignment is realized in the case where not wasting area,
The electric current of small sector is back to ground by idle bit line (idle unit is all erase status unit).
In view of the above and other objects, the present invention proposes a kind of flash memory, including a big sector storage array and one
Small sector storage array, the big sector storage array and the small sector storage array are integrated to same storage array, the big sector
Storage array includes the M wordline and a source line of N bit line of column direction, line direction, the small sector storage array column side
To comprising N bit line, it is divided into n group from column direction by the wordline of line direction and source line, every group includes M/n wordline WL and one
Source line SL, row decoding and level displacement circuit connect the M wordline, n source pullup drive circuit point by word line driving circuit
The storage unit of each group is not connected by the source line of the n group.
Further, which includes a PMOS tube and a NMOS tube, and control signal SEL connection should
The grid of PMOS tube and NMOS tube, the PMOS tube source electrode connect high pressure, NMOS tube source electrode ground connection, the leakage of the PMOS tube and NMOS tube
Extremely source line.
Further, when carrying out read operation to the small sector storage array, each control line voltage is set, to choose a quilt
Storage unit a is selected, and selects the idle unit for making current row be in erase status in the conductive state, the selected storage unit a institute
The electric current that storage information is formed is chosen the source electrode that storage unit a drain electrode enters the selected storage unit a through this by bit line, then passes through
Source line enters source electrode, drain electrode and its bit line of the idle unit, is finally back to ground through array decoding circuit.
Further, the control line voltage include the selected storage unit column bit-line voltage, be expert at word line voltage,
The idle unit column bit-line voltage.
Further, when read operation, bit line BLm voltage where the idle unit is arranged is 0V low pressure, and the selected storage is single
The bit line BLn voltage of first a column is 0.5~0.8V, which is 2.2~2.8V,
In, m ≠ n.
In order to achieve the above objectives, the present invention also provides a kind of control method of flash memory, include the following steps:
Each control line voltage is first arranged before carrying out read operation to the small sector storage array of the memory in step 1, with choosing
In a selected storage unit a, and select so that current row is in erase status idle unit it is in the conductive state；
Step 2, when read operation, electric current that information stored by the selected storage unit a is formed is passed through by the bit line of its column
Selected storage unit a drain electrode enters the source electrode of the selected storage unit a, then through source line enter the idle unit source electrode,
Drain electrode and the idle unit column bit line, are finally back to ground through array decoding circuit.
Further, the control line voltage include the selected storage unit column bit-line voltage, be expert at word line voltage,
The idle unit column bit-line voltage.
Further, in step 1, bit line BLm voltage where the idle unit is arranged is 0V low pressure, and the selected storage is single
The bit line BLn voltage of first a column is 0.5~0.8V, which is 2.2~2.8V,
In, m ≠ n.
As it can be seen that a kind of flash memory of the present invention and its control method pass through in the different array of integrated sector-size
The row decoding circuit area that small sector source line drop-down unit saves 2/3 is removed, each control line electricity when by the way that read operation is rationally arranged
Pressure realizes normal reading, achievees the purpose that normal operating flash memory and saves chip area, realizes the alignment of size sector bit line.
Detailed description of the invention
Fig. 1 is that the flash array of different sectors size under a prior art integrates schematic diagram；
Fig. 2 is that the traditional decoding of source line and read current flow to schematic diagram；
Fig. 3 is a kind of structural schematic diagram of the preferred embodiment of flash memory of the present invention；
Fig. 4 is the pull-down current schematic diagram of small sector storage array in present pre-ferred embodiments；
Fig. 5 is a kind of step flow chart of the control method of flash memory of the present invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 3 is a kind of structural schematic diagram of the preferred embodiment of flash memory of the present invention.As shown in figure 3, the present invention one
Kind flash memory, including a big sector storage array and a small sector storage array, big sector storage array and the small sector
Storage array is integrated to same storage array, which includes the M item of N bit line BL of column direction, line direction
A wordline WL and source line SL, in the line direction of the big sector storage array, row decoding and level displacement circuit pass through wordline
Driving circuit connects those wordline WL, and source pullup drive circuit connect the big sector by source line with source drop-down driving circuit and respectively deposits
The source electrode of storage unit；The small sector storage array column direction includes N bit line BL, is divided into n group from column direction by wordline and source line,
Every group includes a M/n wordline WL and source line SL, and row decoding and level displacement circuit by word line driving circuit connect the M
Wordline, n source pullup drive circuit pass through the storage unit of the source line connection each group of the n item respectively.Of the invention preferably real
Apply in example, big sector is 512 bytes, and small sector is 64 bytes, size sector include 1024 bit lines (BL0~BL1023) with
And 4 wordline (WL0_C~WL3_C and WL0_D~WL3_D), big sector include a source line SL_C, small sector storage array
Be divided into two groups from column direction, first group of wordline is WL0_D and WL1_D, and source line is SL0_D, second group of wordline be WL2_D with
WL3_D, source line are SL1_D, and two groups use source line pulling drive 1 and source line pulling drive 2 to drive respective source line respectively, and existing
Have unlike technology, small sector storage array does not pull down driving circuit using large-sized source line.Herein it should be noted that,
Since the decoding circuit of column direction is same as the prior art, it is not shown in the figure, also it will not go into details herein.
Fig. 4 is the pull-down current schematic diagram of small sector storage array in present pre-ferred embodiments.Of the invention preferably real
It applies in example, source pullup drive circuit is same as the prior art, that is, includes a PMOS tube and a NMOS tube, control signal SEL
The grid of the PMOS tube and NMOS tube is connected, PMOS tube source electrode meets high pressure VSL, NMOS tube source electrode ground connection, the PMOS tube and NMOS
The drain electrode of pipe is source line SL.Illustrate the course of work of the present invention below in conjunction with Fig. 4.
When erasing, wordline WL (generally WL0_D) plus 12V high pressure, bit line BLn and source line SL (generally SL0_D) meet 0V
Electronics on floating gate is pulled away all to remove the information of storage unit (general to wipe by low pressure, the high-intensity magnetic field that High Pressure Difference is formed
High level " 1 " is corresponded to after removing), electric current flows back into ground by the stored unit of wordline WL and bit line BLn；When programming, wordline WL is (general
For WL0_D) plus 1.5V voltage, bit line BLn exports 0.3V low-voltage, and 8V high pressure is connected to source line SL (generally SL0_ to be low by SEL
D), storage unit a formed source line SL (connecing source electrode) arrive bit line BLn (connecing drain electrode) electric current, while to floating gate injection it is electrically realized
" 0 " (one writing does not operate) is written in the memory unit；It is driven when programming and is erasable since electric current is pulled down without source line, institute
It is not influenced with programming with erasable.When reading, it is 0V low pressure, selected cell a institute that bit line BLm (m ≠ n) voltage that do not choose, which is arranged,
Be 0.5~0.8V in the bit line BLn voltage of column, be expert at wordline WL (generally WL0_D) voltage of selected cell a for 2.2~
2.8V, to unselected cells (the wherein idle unit in erase status comprising not using largely) due to wordline WL and bit line
Voltage, that is, drain-to-gate voltage is sufficiently high and in the conductive state between BLm, and the electric current that information stored by selected cell a is formed will be by BLn
Stored unit a drain electrode enters the source electrode of storage unit a, then through source line SL0_D enter without using those of in erasing shape
Idle cell source, drain electrode and the BLm of state are finally back to ground through array decoding circuit (not shown), therefore are read by setting
Voltage is taken, it can be with effectively save chip area.Table 2 shows the read-write erasing of flash memory cell in present pre-ferred embodiments
Voltage.
The flash memory cell of the present invention of table 2 reads and writes erasing voltage
| Storage unit Cell a | Read voltage | Program voltage | Erasing voltage |
| Wordline WL | 2.5 | 1.5 | 12 |
| Selection signal SL | 0 | 8 | 0 |
| Bit line BLn | 0.8 | 0.3 | 0 |
As it can be seen that the present invention passes through the small sector source line drop-down unit saving of removal in the different array of integrated sector-size
2/3 row decoding circuit area respectively controls line voltage and realizes normal reading, reaches normal operating when by the way that read operation is rationally arranged
Flash memory and the purpose for saving chip area realize the alignment of size sector bit line.
Fig. 5 is a kind of step flow chart of the control method of flash memory of the present invention.As shown in figure 5, the present invention is a kind of
The control method of flash memory, includes the following steps:
Step 501, each control line voltage is set when read operation, to choose selected cell a, and selects that current row is made to be in erasing
The idle unit of state is in the conductive state, and control line here includes wordline, source line and bit line；
Step 502, the electric current that information stored by selected cell a is formed enters storage list by the stored unit a drain electrode of bit line
Then the source electrode of first a enters source electrode, drain electrode and its bit line of the idle unit through source line, is finally back to through array decoding circuit
Ground.
Specifically, bit line BLm (m ≠ n) voltage that non-selection unit is arranged first is 0V low pressure, by menu when reading
The bit line BLn voltage of first a column is 0.8V, and be expert at wordline WL (generally WL0_D) voltage of selected cell a is 2.5V, right
Unselected cells (the wherein idle unit in erase status comprising not using largely) are due to electric between wordline WL and bit line BLm
Pressure is that drain-to-gate voltage is sufficiently high and in the conductive state, and the electric current that information stored by selected cell a is formed will be by the stored list of BLn
First a drain electrode enters the source electrode of storage unit a, then through source line SL0_D enter without using those of it is idle in erase status
Cell source, drain electrode and BLm are finally back to ground through array decoding circuit, therefore read voltage by setting, can effectively save
About chip area.
As it can be seen that a kind of flash memory of the present invention and its control method pass through in the different array of integrated sector-size
The row decoding circuit area that small sector source line drop-down unit saves 2/3 is removed, each control line electricity when by the way that read operation is rationally arranged
Pressure realizes normal reading, achievees the purpose that normal operating flash memory and saves chip area, realizes the alignment of size sector bit line.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (6)
1. a kind of flash memory, including a big sector storage array and a small sector storage array, the big sector storage array
It is integrated to same storage array with the small sector storage array, which includes N bit line, row side of column direction
To M wordline and a source line, it is characterised in that: the small sector storage array column direction include N bit line, from column direction
The wordline of line direction and source line are divided into n group, every group includes a M/n wordline WL and source line SL, row decoding and level position
Shift circuit connects the M wordline by word line driving circuit, and it is each that n source pullup drive circuit passes through the n source line connection respectively
The storage unit of group, removal source line pull down driving circuit, and every group of source line is pulled up using the corresponding source line respectively
Driving circuit driving；
Wherein, the source pullup drive circuit include a PMOS tube and a NMOS tube, control signal SEL connect the PMOS tube and
The grid of NMOS tube, the PMOS tube source electrode connect high pressure, and NMOS tube source electrode ground connection, the drain electrode of the PMOS tube and NMOS tube is source
Line；
When carrying out read operation to the small sector storage array, each control line voltage is set, to choose a selected storage unit a,
And selecting the idle unit for making current row be in erase status in the conductive state, information stored by the selected storage unit a is formed
Electric current be chosen the source electrode that storage unit a drain electrode enters the selected storage unit a through this by bit line, then enter the spare time through source line
Source electrode, drain electrode and its bit line for setting unit, are finally back to ground through array decoding circuit.
2. a kind of flash memory as described in claim 1, it is characterised in that: the control line voltage includes that the selected storage is single
First column bit-line voltage, be expert at word line voltage, the idle unit column bit-line voltage.
3. a kind of flash memory as claimed in claim 2, it is characterised in that: when read operation, be arranged where the idle unit
Bit line BLm voltage is 0V low pressure, and the bit line BLn voltage of the selected storage unit a column is 0.5~0.8V, the selected storage
The be expert at word line voltage of unit a is 2.2~2.8V, wherein m ≠ n.
4. a kind of control method of flash memory, includes the following steps:
Before carrying out read operation to the small sector storage array of the memory each control line voltage is arranged, first to choose one in step 1
Selected storage unit a, and select the idle unit for making current row be in erase status in the conductive state, wherein the small sector
Storage array column direction includes N bit line, is divided into n group from column direction by the wordline of line direction and source line, every group includes M/n word
A line WL and source line SL, row decoding and level displacement circuit connect the M wordline by word line driving circuit, on n source
Driving circuit is drawn to pass through the storage unit of the n source line connection each group respectively, removal source line pulls down driving circuit, so that every group of source
Line can be driven using the corresponding source line pullup drive circuit respectively；
Step 2, when read operation, the electric current that information stored by the selected storage unit a is formed is by the bit line of its column through the quilt
It selects storage unit a drain electrode to enter the source electrode of the selected storage unit a, source electrode, the drain electrode of the idle unit is then entered through source line
And the idle unit column bit line, finally it is back to ground through array decoding circuit.
5. a kind of control method of flash memory as claimed in claim 4, it is characterised in that: the control line voltage includes should
Selected storage unit column bit-line voltage, be expert at word line voltage, the idle unit column bit-line voltage.
6. a kind of control method of flash memory as claimed in claim 5, it is characterised in that: in step 1, the spare time is arranged
Bit line BLm voltage where setting unit is 0V low pressure, and the bit line BLn voltage of the selected storage unit a column is 0.5~0.8V,
Selected the be expert at word line voltage of storage unit a is 2.2~2.8V, wherein m ≠ n.
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| CN201410465841.XA CN105469826B (en) | 2014-09-12 | 2014-09-12 | A kind of flash memory and its control method |
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| JP2008047189A (en) * | 2006-08-11 | 2008-02-28 | Matsushita Electric Ind Co Ltd | Semiconductor storage device |
| JP5127439B2 (en) * | 2007-12-28 | 2013-01-23 | 株式会社東芝 | Semiconductor memory device |
| JP5365028B2 (en) * | 2008-03-03 | 2013-12-11 | 富士通セミコンダクター株式会社 | Semiconductor memory device |
| CN102157206A (en) * | 2011-01-17 | 2011-08-17 | 上海宏力半导体制造有限公司 | Memory with redundant circuit and method for providing redundant circuit for memory |
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