CN105450324B - The ONU end method for synchronizing time and device of a kind of XG PON1 systems - Google Patents
The ONU end method for synchronizing time and device of a kind of XG PON1 systems Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
Abstract
The invention discloses a kind of ONU end method for synchronizing time of XG PON1 systems and device, this method to comprise the following steps：Judge whether the downlink data frame that ONU is received is synchronous, if asynchronous, corresponding 1PPS and TOD signals are exported by local crystal oscillator clock；When synchronous, the OMCI frames comprising TOD information are extracted from downlink data frame and parse the SFC values for obtaining the OMCI frames, this SFC value is compared with the multi-frame count value SFC of downlink data frame, it is if equal, then after compensation of delay, corresponding 1PPS and TOD signals are exported using frame head indication signal and corresponding temporal information；If SFC values are unequal, corresponding 1PPS and TOD signals are exported by line-recovered clock.The present invention, no matter when the synchronization of ONU end clock or step-out, ONU end can export accurate 1PPS and TOD signals exactly, system will not can not normal work because of no signal output.
Description
Technical field
The present invention relates to communication EPON field, and in particular to a kind of ONU end time synchronized side of XG-PON1 systems
Method and device.
Background technology
XG-PON1 has higher speed and splitting ratio, from G bit passive light as access network technology compared with GPON
The smooth evolution of network (GPON) technology, to full-service operation ability support etc. advantage, realize low cost, at a distance at a high speed
Access.
XG-PON1 access systems are made up of local side optical line terminal equipment OLT and optical network unit at remote side ONU equipment, its
Physical layer rate is asymmetric manner, i.e., downstream rate is 10Gbit/s, upstream rate 2.5Gbit/s.Join in international telecommunication
The XG-PON1 agreements that alliance telecommunication standards tissue ITU-T is formulated G.987.3 defined in time synchronized function, work as XG-
When PON1 equipment is used for the transmission network of mobile communication, ONU equipment can be connected with mobile base station, provided and moved back to for mobile base station
Biography business, XG-PON1 time synchronized function can provide the clock source of low cost for mobile base station.
When step-out occurs for ONU end clock, ONU end can not export 1PPS and TOD signals exactly, can cause system can not
Normal work.
In view of this, it is badly in need of providing a kind of ONU end precise synchronization of XG-PON1 systems and when ONU is in step-out
Also method and system of exportable relatively accurate 1PPS and TOD signals during state.
The content of the invention
The technical problems to be solved by the invention are how to realize the high-precision time synchronized of XG-PON1 system ONU ends, with
And when ONU is in desynchronizing state, also exportable relatively accurate 1PPS and TOD signals, to keep the normal operation of system.
In order to solve the above-mentioned technical problem, the invention provides a kind of ONU end method for synchronizing time of XG-PON1 systems,
Comprise the following steps：
A1, judge whether the downlink data frame that ONU is received is synchronous, if so, then turning A2, otherwise turns A5；
A2, extract from the downlink data frame OMCI frames comprising TOD information and parse and obtain the OMCI frames
SFC values, the SFC values of the OMCI frames are compared with the multi-frame count value SFC of downlink data frame, if the two is equal, turned
A3, otherwise turn A4；
A3, temporal information corresponding to the frame head of downlink data frame is obtained after compensation of delay, utilize frame head indication signal
Whole pps pulse per second signal and corresponding whole second temporal information are obtained with corresponding temporal information, turns A6；
A4, the whole pps pulse per second signal of existing temporal information acquisition and corresponding whole time second letter are based on using line-recovered clock
Breath, turns A6；
A5, the whole pps pulse per second signal of existing temporal information acquisition and corresponding whole time second letter are based on using local crystal oscillator clock
Breath；
A6, useful signal is exported after the whole pps pulse per second signal and whole second temporal information are sent into TOD serializer circuits, turned
To A1.
In the above-mentioned methods, the downlink data frame that ONU is received is being judged whether during synchronization, from described descending
The OMCI frames for belonging to the ONU are identified in data frame, message integrity detection (MIC) then is carried out to the OMCI frames,
If MIC detections are correct, A2 is gone to step, otherwise abandons the descending OMCI data frames.
In the above-mentioned methods, judging that the downlink data frame that ONU is received whether during synchronization, provides descending same
Walk indication signal.
In the above-mentioned methods, when the downlink data frame synchronization that ONU is received, extracted from the downlink data frame
The multi-frame count value SFC of header signal and the downlink data frame.
In the above-mentioned methods, the compensation of delay be downlink data frame head from OLT ends arrive at ONU end again through time synchronized at
Reason finishes resulting delay.
In the above-mentioned methods, the line-recovered clock is recovered to obtain by the downlink data of PON mouths, with OLT PON mouths
Tranmitting data register is homologous, only exists phase difference.
In the above-mentioned methods, the local crystal oscillator clock is generated by local crystal oscillator, the frequency with the line-recovered clock
It is equal, but frequency difference and difference be present.
In the above-mentioned methods, the line-recovered clock is generated whole with the local crystal oscillator clock by whole second timing mode
Pps pulse per second signal, and the whole second time value by corresponding to adds 1, obtains whole second temporal information corresponding to the whole pps pulse per second signal.
Present invention also offers a kind of ONU end time synchronism apparatus of XG-PON1 systems, including：
Line-recovered clock, recover to obtain using the downlink data of PON mouths, it is homologous with the tranmitting data register of OLT PON mouths,
Only exist phase difference；
Local crystal oscillator clock, generated by local crystal oscillator, it is equal with the frequency of the line-recovered clock, but exist frequency difference and
Difference；
Downlink data frame parser circuitry, the synchronous arbitration functions of downlink data frame are completed, and in downlink data frame synchronization,
Extract the multi-frame count value SFC of header signal and downlink data frame and the OMCI frames comprising TOD information；
CPU process circuits, SFC values and temporal information are extracted from OMCI frames；
Time synchronizing circuit, the multi-frame of the SFC values extracted in the OMCI frames and the downlink data frame is counted
Value SFC is compared；
Clock selection circuit, corresponding clock is selected according to the synchronous judged result of downlink data frame, if what ONU was received
The downlink data frame is asynchronous, and whole pps pulse per second signal and corresponding whole second temporal information are obtained using local crystal oscillator clock；It is no
Then, judge whether the SFC values of the OMCI frames of the TOD information are equal with the multi-frame count value SFC of the downlink data frame, if two
Person is equal, then temporal information corresponding to the frame head of downlink data frame is obtained after compensation of delay, using frame head indication signal and
Corresponding temporal information obtains whole pps pulse per second signal and corresponding whole second temporal information, if the two is unequal, utilizes the circuit
Recovered clock obtains whole pps pulse per second signal and corresponding whole second temporal information；
The present invention judges whether ONU with OLT is in clock synchronous regime by downlink data frame parser circuitry, if different
Step, clock selection circuit will lock local crystal oscillator clock processing and export corresponding 1PPS and TOD signals；When synchronous, time synchronized
Process circuit by the SFC values in CPU registers with extract downlink frame SFC values compared with, will be defeated if SFC values are equal
The time for going out the proposition of CPU process circuits adds the compensation of delay time, if SFC values, clock selection circuit are extensive by locked in line
Multiple clock processing exports corresponding 1PPS and TOD signals.No matter in this way, when the synchronization of ONU end clock or step-out, ONU end can be accurate
Really export accurate 1PPS and TOD signals, system will not can not normal work because of no signal output.
Brief description of the drawings
Fig. 1 is XG-PON1 systems ONU end time synchronized circuit of the present invention；
Fig. 2 is XG-PON1 systems ONU end time synchronized workflow diagram of the present invention.
Embodiment
The present invention is described in detail with reference to embodiment and Figure of description.
As shown in figure 1, for the invention provides a kind of ONU end time synchronism apparatus of XG-PON1 systems, including lower line number
According to frame parser circuitry 10, CPU process circuits 20, time synchronizing circuit 30, TOD serializer circuits 40, clock recovery circuitry
50 and clock selection circuit 60.
Downlink data frame parser circuitry 10 and clock recovery circuitry 50 all receive the downlink data of PON mouths, downlink data frame
The output end of parser circuitry 10 connects the input of CPU process circuits 20 and time synchronizing circuit 30, CPU processing electricity respectively
Road 20 connects TOD serializer circuits 40 through time synchronizing circuit 30, and the output end of clock recovery circuitry 50 connects down respectively
Row data frame parser circuitry 10 and clock selection circuit 60, clock selection circuit 60 have a local crystal oscillator clock information access,
And output end connects time synchronizing circuit 30 and TOD serializer circuits 40 respectively.
The meaning of each transmission signal and the operation principle of each circuit are as follows in Fig. 1：
Downlink data frame parser circuitry 10 completes three functions：First, under the synchronization field in downlink data frame is completed
The synchronous arbitration functions of row data frame, and down-going synchronous indication signal is provided, if synchronous, down-going synchronous indication signal is height,
If asynchronous, down-going synchronous indication signal is low.Second, when being in synchronous regime, frame head letter is extracted from downlink data frame
Number and downlink data frame multi-frame count value SFC.Third, from downlink data frame identification belong to this ONU comprising TOD information
OMCI frames, message integrity detection (MIC) is completed to the OMCI frames, if MIC is correct, the OMCI frames are sent to CPU processing, such as
Fruit MIC is incorrect, and discard processing is done to the OMCI frames.
CPU process circuits 20 complete the parsing to the OMCI frames comprising TOD information, from OMCI frames extract SFC values and when
Between information, the temporal information be downlink multiframes count value be SFC downlink data frame from OLT ends reach ONU end temporal information,
The temporal information is accurate to nanosecond (ns), and then the SFC values and temporal information extracted from OMCI frames are configured at time synchronized
Manage circuit 30 configuration register in, while also need to configure compensation of delay value, the compensation of delay value be downlink data frame head from
OLT arrives at end ONU end and finishes resulting delay through time synchronizing again.
Time synchronizing circuit 30 completes the function that local zone time is synchronized to the OLT times by ONU, when ONU is in synchronous
During state, the frame head indication signal and the multi-frame count value SFC of frame be sent into according to downlink data frame parser circuitry 10, at CPU
The SFC values that reason circuit 20 provides are compared, if SFC values are equal, then the time of frame head instruction is just CPU process circuits 20
The time drawn adds the compensation of delay time, because the time of frame head instruction is not whole time second, it is also necessary to indicates to believe by frame head
Number and frame head instruction time be converted to whole pps pulse per second signal and whole time second.If SFC values are unequal, believed based on the existing time
Breath carries out time holding operation.
TOD serializer circuits 40 complete the output of the 1PPS signals and TOD signals of China Mobile's TD TOD protocol specifications, root
According to the requirement of China Mobile's TD TOD protocol specifications, the whole pulse per second (PPS) indication signal that time synchronizing circuit 30 is sent into is changed
To meet the 1PPS signals of protocol specification requirements, whole second time data is converted to the TOD serial datas for meeting protocol specification.Together
When TOD work clocks are divided, the adjustable output clock of output frequency, for subsequent conditioning circuit use.
Clock recovery circuitry 50 complete the descending serial data of PON mouths clock extraction, outlet line recovered clock, this when
Clock and OLT PON mouths tranmitting data register are homologous clock, phase difference simply be present.When the descending serial datas of PON are normal, clock
The clock that restoring circuit 50 exports is normal clock, can be used for subsequent conditioning circuit, when PON mouth downlink datas are of poor quality or do not have
When having signal, the clock quality that clock recovery circuitry 50 exports is poor or without clock, it is impossible to gives subsequent conditioning circuit to use.
Clock selection circuit 60 completes the selection of the work clock to time synchronizing circuit 30, when downlink data frame solution
When the down-going synchronous indication signal that analysis circuit 10 is sent out is designated as synchronous regime, the output of clock selection circuit 60 is locked as circuit
Recovered clock.When the down-going synchronous indication signal that downlink data frame parser circuitry 10 is sent out is desynchronizing state, clock selecting electricity
The output on road 60 is locked as local crystal oscillator clock.
Above-mentioned technical term implication is as follows：
PON mouth downlink datas：Sent by OLT, the descending serial data that ONU is received.
TOD work clocks：Clock is selected using down-going synchronous indication signal, when down-going synchronous, after selection
Clock is line-recovered clock, and when descending step-out, the clock after selection is local crystal oscillator clock.
Down-going synchronous indicates：ONU does synchronous judgement according to receiving to downlink data, is to represent synchronous for height, when being low
Represent step-out.
The SFC values of downlink data frame：Low 32 bit of the multi-frame count value of indicating downlink data frame.
Downlink data frame frame head indicates：In down-going synchronous state, the frame head indication signal of the downlink data frame provided is
Pulse signal, effective width are a clock.
Whole pulse per second (PPS)：The signal is whole second persond eixis pulse signal, and effective width is a clock widths.
Whole time second：Temporal information corresponding to whole pps pulse per second signal, is parallel data, and the temporal information uses Greenwich
Time timing.
1PPS：Meet the pulse per second (PPS) of China Mobile's TD TOD protocol specifications.
TOD：Meet the Time of Day of China Mobile's TD TOD protocol specifications, i.e., time second corresponding to 1PPS rising edges.
Export clock：The clock of TOD work clocks frequency dividing output, the frequency-adjustable of the output clock.
Compensation of delay：Arrive at what ONU finished to time synchronizing from downlink data frame head according to what actual test obtained
Delay, the delay are configured in register by CPU.
The operation principle of XG-PON1 systems ONU end clock synchronization system of the present invention is as follows：
Downlink data frame parser circuitry 10 parses to the PON mouth downlink datas received, judges whether ONU is descending same
Step, and the down-going synchronous indication signal of clock selection circuit 60 is given, when signal is low, illustrate OUN ends step-out, clock selection circuit
60 selections lock local crystal oscillator clock and carry out whole second counting, and whole pps pulse per second signal, while whole second are generated when reaching whole second counting
Time adds 1；Obtained whole pps pulse per second signal is input to TOD serializer circuits 40, TOD serialization electricity with corresponding whole time second
Road 40 is converted to this whole pps pulse per second signal and whole time second the 1PPS signals and TOD for meeting China Mobile's TD TOD protocol specifications
The output of signal, while TOD work clocks are divided, the adjustable output clock of output frequency, used for subsequent conditioning circuit.
When signal is high, illustrate OUN down-going synchronous, now clock selection circuit 60 selects locked in line recovered clock,
Downlink data frame parser circuitry 10 extracts TOD OMCI frames and is sent to CPU process circuits 20 simultaneously, and CPU process circuits 20 are from TOD
OMCI frames extract temporal information corresponding to SFC values and the frame, and (downlink data frame head is from OLT by the information and compensation of delay value
End arrives at ONU end and finishes resulting delay through time synchronizing again) it is configured to the register of time synchronizing circuit 30
In, the SFC values in CPU registers are compared with the SFC values of the downlink data frame extracted, if equal, after compensation of delay
Frame head corresponding to temporal information input to TOD serializer circuits 40, because the time of frame head instruction is not whole time second, the time
The time that frame head indication signal and frame head indicate is converted to whole pps pulse per second signal and whole time second, TOD by synchronous processing circuit 30
Serializer circuit 40, which is again converted to this whole pps pulse per second signal and whole time second, meets China Mobile's TD TOD protocol specifications
The output of 1PPS signals and TOD signals, while TOD work clocks are divided, the adjustable output clock of output frequency, for after
Continuous circuit uses.
If unequal, clock selection circuit 60 will select line-recovered clock to carry out whole second counting, be counted when reaching the whole second
Whole pps pulse per second signal is generated during number, while whole time second adds 1, then the TOD serializer circuits 40 that are transferred to as described above are handled
Obtain corresponding effective information.
Clock selecting after above-mentioned judgement time synchronized is realized using clock phase-locked loop (PLL), can improve TOD processing electricity
Clock quality used in road.
Present invention also offers a kind of ONU end method for synchronizing time of XG-PON1 systems, as shown in Fig. 2 to be of the invention
Workflow diagram, comprise the following steps：
S1, ONU power-up initializing, provide whole second temporal information corresponding to a whole pps pulse per second signal and whole pps pulse per second signal
Initial value；
S2, judge that ONU is descending and whether be in synchronous regime, if so, then turning S3, otherwise turn S8；
S3, extract from downlink data frame the OMCI frames comprising TOD information and parse the SFC for obtaining the OMCI frames
Value, the SFC values of the OMCI frames are compared with the multi-frame count value SFC of downlink data frame, if the two is equal, turn S4,
Otherwise S6 is turned；
S4, according to corresponding to the temporal information that CPU process circuits extract plus the compensation of delay time obtains data frame frame head
Temporal information；
S5, temporal information corresponding to frame head indication signal and frame head indication signal is converted into whole pps pulse per second signal and whole second
After whole second temporal information corresponding to pulse signal, turn S10；
S6, utilize the whole second timing of line-recovered clock progress；
When S7, arrival whole second count, whole pps pulse per second signal is generated, while the whole second time value by corresponding to adds 1；And turn S10；
S8, utilize the whole second timing of local crystal oscillator clock progress；
When S9, arrival whole second count, whole pps pulse per second signal is generated, while the whole second time value by corresponding to adds 1；
S10, whole pps pulse per second signal and whole second temporal information are sent to useful signal after TOD serializer circuits, go to S1.
The operation principle of the flow chart of the present invention is as follows：
ONU power-up initializings, that is, provide whole second temporal information corresponding to a whole pps pulse per second signal and whole pps pulse per second signal
Initial value, then judge that ONU is descending and whether be in synchronous regime.
When ONU is in desynchronizing state, time holding processing is carried out, whole second timing is carried out using local crystal oscillator clock, arrives
When being counted up to the whole second, whole pps pulse per second signal is generated, while the whole second time value by corresponding to adds 1, by whole pps pulse per second signal and whole second
Temporal information is sent to TOD serializer circuits 40, be converted into meet China Mobile's TD TOD protocol specifications 1PPS signals and
The output of TOD signals, while TOD work clocks are divided, the adjustable output clock of output frequency, make for subsequent conditioning circuit
With；Handling process comes back to the judgement state of ONU down-going synchronous simultaneously, and whole pps pulse per second signal and whole second time value are updated
For last state.
When ONU is in synchronous regime, judge that the SFC values of downlink data frame carry with CPU from the OMCI frames comprising TOD information
Whether the SFC values of taking-up are equal, if equal, then temporal information corresponding to downlink data frame frame head just can obtain, the time
Information is that the compensation of delay time of CPU process circuits 20 is added from the temporal information of OMCI frames extraction, further indicates frame head
When temporal information corresponding to signal and frame head indication signal is converted to the whole second corresponding to whole pps pulse per second signal and whole pps pulse per second signal
Between information, whole pps pulse per second signal and whole second temporal information are sent to TOD serializer circuits 40 and carry out processing output, while processing stream
Journey comes back to the judgement state of ONU down-going synchronous, and whole pps pulse per second signal and whole time second are updated into last state；
If unequal, whole second timing is carried out using line-recovered clock, when reaching whole second counting, generates whole pulse per second (PPS) letter
Number, while the whole second time value by corresponding to adds 1, and whole pps pulse per second signal and whole second temporal information are sent into TOD serializer circuits 40
Carry out processing output, while handling process comes back to the judgement state of ONU down-going synchronous, and by whole pps pulse per second signal and whole second
Time is updated to last state.
The present invention is not limited to above-mentioned preferred forms, and anyone should learn that the knot made under the enlightenment of the present invention
Structure changes, and the technical schemes that are same or similar to the present invention, each falls within protection scope of the present invention.
Claims (9)
1. a kind of ONU end method for synchronizing time of XG-PON1 systems, it is characterised in that comprise the following steps：
A1, judge whether the downlink data frame that ONU is received is synchronous, if so, then turning A2, otherwise turns A5；
A2, extract from the downlink data frame OMCI frames comprising TOD information and parse the SFC for obtaining the OMCI frames
Value, the SFC values of the OMCI frames are compared with the multi-frame count value SFC extracted in downlink data frame, if the two is equal,
Then turn A3, otherwise turn A4；
A3, temporal information corresponding to the frame head of downlink data frame is obtained after compensation of delay, utilize frame head indication signal and right
The temporal information answered obtains whole pps pulse per second signal and corresponding whole second temporal information, turns A6；
A4, the existing temporal information whole pps pulse per second signal of acquisition and corresponding whole second temporal information are based on using line-recovered clock,
Turn A6；
A5, the existing temporal information whole pps pulse per second signal of acquisition and corresponding whole second temporal information are based on using local crystal oscillator clock；
A6, useful signal is exported after the whole pps pulse per second signal and whole second temporal information are sent into TOD serializer circuits, gone to
A1。
2. the method as described in claim 1, it is characterised in that judging whether the downlink data frame that ONU is received is synchronous
During, the OMCI frames for belonging to the ONU are identified from the downlink data frame, then the OMCI frames are reported
Literary integrity detection, if message integrity detection is correct, then A2 is gone to step, otherwise abandons the downlink data frame.
3. the method as described in claim 1, it is characterised in that judging whether the downlink data frame that ONU is received is synchronous
During, provide down-going synchronous indication signal.
4. the method as described in claim 1, it is characterised in that when the downlink data frame synchronization that ONU is received, from described
The multi-frame count value SFC of header signal and the downlink data frame is extracted in downlink data frame.
5. the method as described in claim 1, it is characterised in that the compensation of delay is that downlink data frame head arrives at from OLT ends
ONU end finishes resulting delay through time synchronizing again.
6. the method as described in claim 1, it is characterised in that the line-recovered clock is recovered by the downlink data of PON mouths
Obtain, it is homologous with the tranmitting data register of OLT PON mouths, only exist phase difference.
7. the method as described in claim 1, it is characterised in that the local crystal oscillator clock is generated by local crystal oscillator, and described
The frequency of line-recovered clock is equal.
8. the method as described in claim 1, it is characterised in that the line-recovered clock passes through with the local crystal oscillator clock
Whole second timing mode generates whole pps pulse per second signal, and the whole second time value by corresponding to adds 1, and it is corresponding to obtain the whole pps pulse per second signal
Whole second temporal information.
A kind of 9. ONU end time synchronism apparatus of XG-PON1 systems, it is characterised in that including：
Line-recovered clock, recover to obtain using the downlink data of PON mouths, it is homologous with the tranmitting data register of OLT PON mouths, only deposit
In phase difference；
Local crystal oscillator clock, generated by local crystal oscillator, it is equal with the frequency of the line-recovered clock；
Downlink data frame parser circuitry, the synchronous arbitration functions of downlink data frame are completed, and in downlink data frame synchronization, extraction
Go out the multi-frame count value SFC of header signal and downlink data frame and the OMCI frames comprising TOD information；
CPU process circuits, SFC values and temporal information are extracted from OMCI frames；
Time synchronizing circuit, by the SFC values extracted in the OMCI frames and the multi-frame count value SFC of the downlink data frame
It is compared；
Clock selection circuit, corresponding clock is selected according to the synchronous judged result of downlink data frame, if ONU receive it is described
Downlink data frame is asynchronous, and whole pps pulse per second signal and corresponding whole second temporal information are obtained using local crystal oscillator clock；Otherwise, sentence
Whether the SFC values of the OMCI frames for the TOD information of breaking are equal with the multi-frame count value SFC of the downlink data frame, if the two phase
Deng temporal information corresponding to the frame head of downlink data frame then being obtained after compensation of delay, using frame head indication signal and correspondingly
Temporal information obtain whole pps pulse per second signal and corresponding whole second temporal information, if the two is unequal, utilize the circuit recover
Clock obtains whole pps pulse per second signal and corresponding whole second temporal information；
TOD serializer circuits, the whole pulse per second (PPS) indication signal that the time synchronizing circuit is sent into is converted to and meets agreement
The 1PPS signals of code requirement and TOD information.
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| CN106603186A (en) * | 2016-12-19 | 2017-04-26 | 上海市共进通信技术有限公司 | ONU time synchronization processing system and method based on the GPON system in the class B PON protection |
| CN109981205B (en) * | 2019-02-22 | 2020-07-28 | 烽火通信科技股份有限公司 | Method and system for transmitting 1PPS + TOD signals |
| CN109981496B (en) * | 2019-03-27 | 2020-12-25 | 烽火通信科技股份有限公司 | OMCI framing device and method for XGPON OLT |
| CN111399418B (en) * | 2020-03-30 | 2021-02-26 | 中国电子科技集团公司第五十四研究所 | Low-power-consumption power-off time-keeping module |
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