CN105448915B - The forming method and gate structure of gate structure - Google Patents
The forming method and gate structure of gate structure Download PDFInfo
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- CN105448915B CN105448915B CN201410437368.4A CN201410437368A CN105448915B CN 105448915 B CN105448915 B CN 105448915B CN 201410437368 A CN201410437368 A CN 201410437368A CN 105448915 B CN105448915 B CN 105448915B
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Abstract
The present invention provides a kind of forming method and gate structure of gate structure, and the forming method of gate structure includes providing substrate, forms dielectric layer on substrate, and forms the first opening, the second opening in the dielectric layer；Form the first work-function layer；Only retain the first work-function layer being located in the first opening, to form the work-function layer of NMOS device；Form the second work-function layer in the second opening and in the first work-function layer in the first opening respectively；Form grid.Gate structure includes substrate, dielectric layer, the first opening in dielectric layer, the second opening；First work-function layer, the second work-function layer, grid.The beneficial effects of the present invention are the work-function layer for being initially formed NMOS device is conducive to accelerate technique progress, reduces the influence to other semiconductor devices in etching process；The technique for saving one of formation diffusion impervious layer；The space of the first opening, the second opening is increased, and then is conducive to the formation of grid.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of forming method and gate structure of gate structure.
Background technology
With being constantly progressive for semiconductor technology, the characteristic size of semiconductor devices tapers into.And semiconductor devices is special
Sign size tapers into that more stringent requirements are proposed to semiconductor fabrication process.
By taking complementary metal oxide semiconductor (CMOS) device as an example, this device includes PMOS device and NMOS devices
Part, due to property difference between both devices, the requirement when forming grid is also different, thus in manufacture craft it is generally necessary to
The grid being respectively formed in PMOS device and NMOS device, step is more complicated, this is caused to the making of entire cmos device
It influences.
Therefore, how to simplify and accelerate to form gate structure technique, become those skilled in the art's technology urgently to be resolved hurrily
Problem.
Invention content
Problems solved by the invention is to provide a kind of forming method and gate structure of gate structure, so as to make grid
The technique of structure becomes relatively easy quick.
To solve the above problems, the present invention provides a kind of forming method of gate structure, including：
Substrate is provided, the substrate has NMOS area and PMOS area；
Dielectric layer is formed in the NMOS area and PMOS area of the substrate, and is respectively formed in the dielectric layer
Positioned at the NMOS area and the first opening and the second opening of PMOS area；
The first work-function layer is formed in substrate and first opening and the second opening；
The first work-function layer of part is removed, only retains the first work-function layer being located in the first opening, to form NMOS devices
The work-function layer of part；
After the step of forming the work-function layer of NMOS device, respectively in second opening and in the first opening
The first work-function layer on form the second work-function layer, second work-function layer as PMOS device work-function layer and
The diffusion impervious layer of NMOS area and PMOS area；
Form the grid of filling first opening, the second opening.
Optionally, the step of the first work-function layer of formation includes：Made using the tantalum aluminium of titanium aluminium, the titanium aluminium of carbon dope or carbon dope
For the material of first work-function layer.
Optionally, the step of work-function layer for forming NMOS device includes：Part is removed by the way of wet etching
One work-function layer, to form the work-function layer of the NMOS device.
Optionally, include SC1 in the etching agent of wet etching.
Optionally, the step of forming the second work-function layer includes forming the second work(of titanium nitride or titanium silicon nitride material
Function layer.
Optionally, the step of forming the second work-function layer includes forming second work function of the thickness range at 25~60 angstroms
Layer.
Optionally, first work-function layer and the second work-function layer are formed by the way of atomic layer deposition.
Optionally, the step of formation grid includes：Form metal gates.
Optionally, the step of formation metal gates include：Form tungsten grid.
Optionally, formed first opening, second opening the step of after, formed the first work-function layer the step of before, institute
Stating forming method further includes：High-K dielectric layer, cap layer and stop-layer are sequentially formed in first opening, the second opening.
Optionally, the high-K dielectric layer of hafnium oxide material is formed.
Optionally, the cap layer of titanium nitride material is formed.
Optionally, the stop-layer of tantalum-nitride material is formed.
A kind of gate structure, including：
Substrate, the substrate have NMOS area and PMOS area；
Dielectric layer on substrate, the dielectric layer are respectively provided in the part of the NMOS area and PMOS area
First opening, the second opening；
There is the first work-function layer of the work-function layer as NMOS device in first opening；
The second work-function layer in the first work-function layer in first opening and in the second opening, described the
Two work-function layers are used as the work-function layer of PMOS device, also serve as the diffusion impervious layer of NMOS area and PMOS area；
It is filled in the grid of first opening, the second opening.
Optionally, the material of first work-function layer is the tantalum aluminium of titanium aluminium, the titanium aluminium of carbon dope or carbon dope.
Optionally, the material of second work-function layer is titanium nitride or titanium silicon nitride.
Optionally, the thickness of second work-function layer is in the range of 25~60 angstroms.
Optionally, between first open surfaces and the first work-function layer, second open surfaces and the second work content
Further include high-K dielectric layer, cap layer and stop-layer between several layers, the cap layer is located above the high-K dielectric layer, described
Stop-layer is located above the cap layer.
Optionally, the material of the high-K dielectric layer is hafnium oxide, and the material of the cap layer is titanium nitride, the stopping
The material of layer is tantalum nitride.
Optionally, the material of the grid is tungsten
Compared with prior art, technical scheme of the present invention has the following advantages：
After forming the first opening, the second opening, it is initially formed the work-function layer of NMOS device, because of the work(of NMOS device
Function layer is easier to be removed, and is initially formed the work-function layer for comparing the PMOS device for being difficult to be removed compared with the existing technology,
The work-function layer that the present invention is initially formed NMOS device is conducive to accelerate technique progress, and due to the work-function layer of NMOS device ratio
It is easier to etch, etch period is also unlikely to long, this advantageously reduces the influence to other semiconductor devices in etching process.
In addition, after the work-function layer for forming PMOS device, the work-function layer of the PMOS device be also used as NMOS area with
And the diffusion impervious layer of PMOS area, it means that the work of one of formation diffusion impervious layer can be saved compared to the prior art
Skill；Also, due to not having to re-form one layer of diffusion impervious layer in the first opening, the second opening, this increases to a certain extent
The space of first opening, the second opening, and then be conducive to the formation of grid.
Description of the drawings
Fig. 1 to Fig. 5 is the structural schematic diagram of each step when forming cmos device gate structure in the prior art；
Fig. 6 to Figure 13 be gate structure of the present invention one embodiment of forming method in each step structural schematic diagram.
Specific implementation mode
Since PMOS device is different from the property of NMOS device, need to be respectively formed PMOS device and NMOS in the prior art
The gate structure of device.Show referring to figs. 1 to the structure that Fig. 5 is each step when forming cmos device gate structure in the prior art
It is intended to, referring initially to Fig. 1, the dielectric layer 2 with opening 3,4 is formed on substrate 1, opening 3,4 is in subsequent steps
It is respectively formed the gate structure of PMOS device and NMOS device.
With continued reference to Fig. 2 and Fig. 3, PMOS work-function layers 5 are formed in the opening 3,4, then remove part PMOS
Work-function layer 5, only retain be located at PMOS area it is corresponding opening 3 in PMOS work-function layers 5.Specifically, the prior art is general
The etching mask such as photoresist is formed on needing the PMOS work-function layers 5 retained, and removal is etched cruelly by etching agent
The PMOS work-function layers 5 to expose outside.
In general, the material of the PMOS work-function layers 5 of the prior art is relatively difficult to be etched, this can cause to etch PMOS
The process of work-function layer 5 becomes very slow, needs to take a long time the PMOS work-function layers 5 that could remove expose portion, a side
Face increases taking for entire technique, affects yield (through-put), increases cost, on the other hand, prolonged to carve
Erosion can impact device, for example, leading to a degree of variation of pattern generation that is open, this can subsequently be filled in the opening
Material is affected with forming grid.
With reference to figure 4 and Fig. 5, NMOS work-function layers 6 are formed in forming the PMOS work-function layers 5 and opening 4,
After this, it is also necessary to barrier layer 7 etc. is formed in the NMOS work-function layers 6, to form grid.
The prior art forms grid in opening 3,4.Whole process is made slow progress and complex procedures, and cost, output etc. are equal
It is affected.
In order to overcome the above problem, the present invention to provide a kind of forming method of gate structure, include the following steps：
Substrate is provided, the substrate has NMOS area and PMOS area；The substrate NMOS area and
Dielectric layer is formed in PMOS area, and be respectively formed in the dielectric layer positioned at the NMOS area and PMOS area
One opening and the second opening；The first work-function layer is formed in substrate and first opening and the second opening；Remove part
First work-function layer only retains the first work-function layer being located in the first opening, to form the work-function layer of NMOS device；In shape
At NMOS device work-function layer the step of after, respectively it is described second opening in and first opening in the first work function
The second work-function layer, work-function layer and NMOS area and PMOS of second work-function layer as PMOS device are formed on layer
The diffusion impervious layer in region；Form the grid of filling first opening, the second opening.
The present invention is initially formed the work-function layer of NMOS device, because of NMOS devices after forming the first opening, the second opening
The work-function layer of part is easier to be removed, and is initially formed the work content for comparing the PMOS device for being difficult to be removed compared with the existing technology
Several layers, the work-function layer that the present invention is initially formed NMOS device is conducive to accelerate technique progress, and due to the work content of NMOS device
Number is easier to etch, and etch period is also unlikely to long, this is advantageously reduced in etching process to other semiconductor devices
It influences.In addition, after the work-function layer for forming PMOS device, the work-function layer of the PMOS device is also used as NMOS area
The diffusion impervious layer of domain and PMOS area, it means that one formation diffusion impervious layer can be saved compared to the prior art
Technique；Also, due to not having to re-form one layer of diffusion impervious layer in the first opening, the second opening, this increases to a certain extent
Add the space of the first opening, the second opening, and then is conducive to the formation of grid.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
It is shown with reference to figure 6 to Figure 13, for the knot of each step in one embodiment of forming method of gate structure of the present invention
Structure schematic diagram.
Referring initially to Fig. 6, substrate 40 is provided, the substrate 40 has NMOS area 200 and PMOS area 100, is used for
It is respectively formed NMOS device and PMOS device.
Dielectric layer 60 is formed in the NMOS area and PMOS area of the substrate 40, and respectively positioned at the NMOS
The first opening 201 and the second opening 101 are formed in the dielectric layer 60 of region 200 and PMOS area 100.First opening 201
And second opening 101 in be used to form grid.
In the present embodiment, it before forming the dielectric layer 60, is also formed on the substrate 40 corresponding to described the
The gate dielectric layer 50 of one opening 201 and the second opening 101.It is the prior art herein, the present invention does not repeat this, while
It is not limited in any way.
With reference to figure 7 to Fig. 9, in the present embodiment, before forming first work-function layer, in first opening
201 and second opening 101 be formed with high-K dielectric layer 110 (with reference to figure 7), cap layer 120 (with reference to figure 8) and stop-layer 130
(with reference to figure 9).
Referring initially to Fig. 7, high-K dielectric layer 110 is formed in 201 and second opening 101 of wherein first opening.Institute
State electric property of the high-K dielectric layer 110 for improving grid.
Specifically, HfO may be used as material in the high-K dielectric layer 110.But this is not limited by the present invention,
His material such as LaO, AlO, BaZrO, HfZrO, HfZrON, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO,
HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4Etc. the material that can also be used as the high-K dielectric layer 110, how is specific choice
Kind material should be depending on actual conditions.
Then referring to Fig. 8, lid is formed in the high-K dielectric layer 110 in first opening, 201 and second opening 101
Cap layers 120 (capping layer).It includes mobility, electrical and gate reliability that the cap layer 120, which is mainly used for improving,
Deng device performance.
Specifically, TiN may be used as material in the cap layer 120.But this is not limited by the present invention, other materials
Expect such as La2O3、AL2O3、Ga2O3、In2O3, MoO, Pt, Ru, TaCNO, Ir, TaC, MoN, WN etc. can also be used as the block
120 material of layer, being specifically chosen which kind of material should be depending on actual conditions.
Referring next to Fig. 9, stop-layer is formed in the cap layer 120 in first opening, 201 and second opening 101
130.The stop-layer 130 is used for during being subsequently formed first work-function layer, as block in PMOS area 100
The etching barrier layer of layer 120.
In the present embodiment, the stop-layer 130 uses tantalum nitride as material.
With reference to figure 10, the first work-function layer 210 is formed in substrate 40 and 201, second opening 101 of the first opening
(Figure 10 illustrates only the first work-function layer 210 in first the 201, second opening 101 of opening).
Stop specifically, the first work-function layer 210 in the present embodiment is formed in the first opening 201, second opening 101
Only on layer 130.
In the present embodiment, the material as first work-function layer 210 using titanium aluminium (TiAl) may be used.But
This is not limited by the present invention, and the titanium aluminium (TiAlC) of other materials such as carbon dope or the tantalum aluminium (TaAlC) of carbon dope can also be made
For the material of first work-function layer 210.
In the present embodiment, the mode shape of atomic layer deposition (Atomic Layer Deposition, ALD) may be used
At first work-function layer 210.This mode is easy to accurately control the thickness for the first work-function layer 210 to be formed, and is formed
The first work-function layer 210 it is also relatively uniform, covering power is also relatively good.
But the present invention is not construed as limiting for which kind of mode to form first work-function layer 210 using.
In conjunction with reference to figure 11, the first work-function layer of part 210 is removed, the first work(being located in the first opening 201 is only retained
Function layer 210, to form the work-function layer of NMOS device.
As it was noted above, the work-function layer of NMOS device is easier to be etched, it is initially formed PMOS compared to the prior art
The work-function layer of device, this step save the time to a certain extent；Simultaneously as not needing described in excessive time etching
The work-function layer of NMOS device, that is, etch period opposite can shorten, and the other parts of device are also not readily susceptible to influence,
For example, the pattern of second opening 101 is also not readily susceptible to influence.
Specifically, the present embodiment removes the first work-function layer of part 210 by the way of wet etching, described in formation
The work-function layer of NMOS device.This etching mode is easier to control, it is possible to reduce the influence to device other parts.
But this is not limited by the present invention, other etching modes such as dry etching can be used for etching described first
Work-function layer 210.
Further, in the present embodiment, include SC1 in the etching agent of wet etching.The SC1 is a kind of composite chemical
Agent, main component NH4OH、H2O2With H2O。
Removal first work-function layer 210 that etching agent can be as quickly as possible is summarized using this, in the present embodiment, removal
Rate can reach 200 angstroms~400 angstroms it is per minute.
With reference to figure 12, after the work-function layer for forming NMOS device, respectively in second opening 101 and first
The second work-function layer 220 is formed in the first work-function layer 210 in opening 201, second work-function layer 220 is as the areas PMOS
The work-function layer in domain 100 and the diffusion impervious layer of NMOS area 200 and PMOS area 100.
In the prior art after being respectively formed the work-function layer of PMOS and NMOS, it is also necessary to be additionally formed one layer of diffusion
Barrier layer (barrier layer), to prevent the metal gates being subsequently formed from spreading downwards.The second work function that the present invention is formed
Itself the just diffusion impervious layer as NMOS area 200 and PMOS area 100 of layer 220 not only saves one of formation diffusion and hinders
The process of barrier also saves the space of the first opening 201 and second opening 101, this is conducive to subsequent formation grid
Material is filled into first opening, 201 and second opening 101.
In the present embodiment, second work-function layer 220 is used as material using titanium nitride (TiN).But the present invention couple
This is not construed as limiting, and other materials such as titanium silicon nitride (TiSiN) can also be used as the material of second work-function layer 220.
In order to keep second work-function layer 220 sufficiently thick to play the role of diffusion impervious layer, while being unlikely to again
Thickness influences device architecture, and in the present embodiment, the thickness range of second work-function layer 220 is at 25~60 angstroms.
It should be noted that the above thickness range is only an example of the present embodiment, when specific operation, described second
The thickness of work-function layer 220 can be adjusted according to actual conditions.
In the present embodiment, the mode shape of atomic layer deposition (Atomic Layer Deposition, ALD) may be used
At second work-function layer 220.As it was noted above, this mode is easy to accurately control the second work-function layer 220 to be formed
Thickness, and the second work-function layer 220 formed is also relatively uniform, covering power is also relatively good.
But the present invention is not construed as limiting for which kind of mode to form second work-function layer 220 using.
With reference to figure 13, after forming second work-function layer 220, in first work-function layer 210, the second work content
The grid 202,102 of filling 201, second opening 101 of the first opening is formed on several layers 220.
In the present embodiment, it is described be grid 202,102 be metal gates.Specifically, the metal gates are tungsten grid.
In the present embodiment, second work-function layer 220 is also used as the tungsten grid and the first work function of lower section
Adhesion layer (glue layer) between layer 210 or stop-layer 130, that is, increase the tungsten grid and the first work function of formation
Binding performance between layer 210 or stop-layer 130.
In addition, continue to refer to figure 13, the present invention also provides a kind of gate structure, it is described in the present embodiment, the grid
Structure includes：
Substrate 40, the substrate 40 have NMOS area 200 and PMOS area 100；
Dielectric layer 60 on substrate 40, the dielectric layer 60 is positioned at the NMOS area 200 and PMOS area
100 part is respectively provided with the first opening 201, second opening 101；
There is the first work-function layer 210 of the work-function layer as NMOS device in first opening 201；
In the present embodiment, the material of first work-function layer 210 is titanium aluminium, the titanium aluminium of carbon dope or the tantalum of carbon dope
Aluminium.
Have as PMOS device in the first work-function layer 210 in first opening and in the second opening 101
Second work-function layer 220 of the diffusion impervious layer of work-function layer, NMOS area 200 and PMOS area 100；
In the present embodiment, the material of second work-function layer 220 is titanium nitride or titanium silicon nitride.
Further, in order to keep second work-function layer 220 sufficiently thick to play the role of diffusion impervious layer, while again not
As for blocked up influence device architecture, in the present embodiment, the thickness range of second work-function layer 220 is at 25~60 angstroms.
There are the grid for filling first opening, the second opening in first work-function layer 210 and the second work-function layer 220
Pole 202,102.
In the present embodiment, the material of the grid 202,102 is tungsten.
In the present embodiment, between first open surfaces and the first work-function layer, the second open surfaces and the second work(
Further include high-K dielectric layer 110, cap layer 120 and stop-layer 130 between function layer, the cap layer 120 is located at the high K
110 top of dielectric layer, the stop-layer 130 are located at 120 top of the cap layer.
Wherein, the high-K dielectric layer 110 is used to improve the electric property of grid, specifically, the high K in the present embodiment is situated between
The material of matter layer 110 is hafnium oxide.But this is not limited by the present invention, other materials such as LaO, AlO, BaZrO, HfZrO,
HfZrON、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4
Etc. the material that can also be used as the high-K dielectric layer 110, being specifically chosen which kind of material should be depending on actual conditions.
The cap layer 120 is mainly used for the device performance that improvement includes mobility, electrical and gate reliability etc., tool
Body, TiN may be used as material in the cap layer 120 in the present embodiment.But this is not limited by the present invention, other materials
Such as La2O3、AL2O3、Ga2O3、In2O3, MoO, Pt, Ru, TaCNO, Ir, TaC, MoN, WN etc. can also be used as the cap layer
120 materials, being specifically chosen which kind of material should be depending on actual conditions.
The stop-layer 130 is used for as etching stop layer when forming first work-function layer 210.In the present embodiment
In, the stop-layer 130 is using tantalum nitride as material.
In addition it should be noted that the gate structure of the present invention can be, but not limited to the formation using above-mentioned gate structure
Method is formed.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of gate structure, which is characterized in that including：
Substrate is provided, the substrate has NMOS area and PMOS area；
Dielectric layer is formed in the NMOS area and PMOS area of the substrate, and is respectively formed and is located in the dielectric layer
The first opening and the second opening of the NMOS area and PMOS area；In substrate and first opening and the second opening
The first work-function layer of middle formation；
The first work-function layer of part is removed, only retains the first work-function layer being located in the first opening, to form NMOS device
Work-function layer；
After the step of forming the work-function layer of NMOS device, the in second opening and in the first opening respectively
The second work-function layer, work-function layer and NMOS area of second work-function layer as PMOS device are formed in one work-function layer
The diffusion impervious layer in domain and PMOS area；
Form the grid of filling first opening, the second opening.
2. forming method as described in claim 1, which is characterized in that formed the first work-function layer the step of include：Using titanium
Material of the tantalum aluminium of aluminium, the titanium aluminium of carbon dope or carbon dope as first work-function layer.
3. forming method as described in claim 1, which is characterized in that the step of work-function layer for forming NMOS device includes：
The first work-function layer of part is removed by the way of wet etching, to form the work-function layer of the NMOS device.
4. forming method as claimed in claim 3, which is characterized in that include SC1 in the etching agent of wet etching.
5. forming method as described in claim 1, which is characterized in that the step of forming the second work-function layer includes forming nitrogen
Change the second work-function layer of titanium or titanium silicon nitride material.
6. forming method as described in claim 1, which is characterized in that the step of forming the second work-function layer includes forming thickness
Spend second work-function layer of the range at 25~60 angstroms.
7. forming method as described in claim 1, which is characterized in that form first work(by the way of atomic layer deposition
Function layer and the second work-function layer.
8. forming method as described in claim 1, which is characterized in that formed grid the step of include：Form metal gates.
9. forming method as claimed in claim 8, which is characterized in that formed metal gates the step of include：Form tungsten grid.
10. forming method as described in claim 1, which is characterized in that after the step of forming the first opening, the second opening,
Before the step of forming the first work-function layer, the forming method further includes：The shape successively in first opening, the second opening
At high-K dielectric layer, cap layer and stop-layer.
11. forming method as claimed in claim 10, which is characterized in that form the high-K dielectric layer of hafnium oxide material.
12. forming method as claimed in claim 10, which is characterized in that form the cap layer of titanium nitride material.
13. forming method as claimed in claim 10, which is characterized in that form the stop-layer of tantalum-nitride material.
14. a kind of gate structure, which is characterized in that the gate structure is by claim 1 to claim 13 any one institute
The forming method for the gate structure stated is formed, including：
Substrate, the substrate have NMOS area and PMOS area；
Dielectric layer on substrate, the dielectric layer are respectively provided with first in the part of the NMOS area and PMOS area
Opening, the second opening；
There is the first work-function layer of the work-function layer as NMOS device in first opening；
The second work-function layer in the first work-function layer in first opening and in the second opening, second work(
Function layer is used as the work-function layer of PMOS device, also serves as the diffusion impervious layer of NMOS area and PMOS area；
It is filled in the grid of first opening, the second opening.
15. gate structure as claimed in claim 14, which is characterized in that the material of first work-function layer is titanium aluminium, mixes
The titanium aluminium of carbon or the tantalum aluminium of carbon dope.
16. gate structure as claimed in claim 14, which is characterized in that the material of second work-function layer be titanium nitride or
Person's titanium silicon nitride.
17. gate structure as claimed in claim 14, which is characterized in that the thickness of second work-function layer is at 25~60 angstroms
In the range of.
18. gate structure as claimed in claim 14, which is characterized in that first open surfaces and the first work-function layer it
Between, between second open surfaces and the second work-function layer further include high-K dielectric layer, cap layer and stop-layer, the lid
Cap layers are located above the high-K dielectric layer, and the stop-layer is located above the cap layer.
19. gate structure as claimed in claim 18, which is characterized in that the material of the high-K dielectric layer is hafnium oxide, described
The material of cap layer is titanium nitride, and the material of the stop-layer is tantalum nitride.
20. gate structure as claimed in claim 14, which is characterized in that the material of the grid is tungsten.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103378008A (en) * | 2012-04-27 | 2013-10-30 | 中国科学院微电子研究所 | Bimetallic grid CMOS device and manufacturing method thereof |
| CN103531538A (en) * | 2012-07-02 | 2014-01-22 | 中芯国际集成电路制造(上海)有限公司 | Forming method of complementary type metal-oxide semiconductor tube |
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| US7682891B2 (en) * | 2006-12-28 | 2010-03-23 | Intel Corporation | Tunable gate electrode work function material for transistor applications |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103378008A (en) * | 2012-04-27 | 2013-10-30 | 中国科学院微电子研究所 | Bimetallic grid CMOS device and manufacturing method thereof |
| CN103531538A (en) * | 2012-07-02 | 2014-01-22 | 中芯国际集成电路制造(上海)有限公司 | Forming method of complementary type metal-oxide semiconductor tube |
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