CN105448839A - Semiconductor device photoetching method, flash memory device manufacturing method, and flash memory device - Google Patents
Semiconductor device photoetching method, flash memory device manufacturing method, and flash memory device Download PDFInfo
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Abstract
The invention discloses a semiconductor device photoetching method, a flash memory device manufacturing method, and a flash memory device. A semiconductor device comprises a to-be-etched region and a non-etched region. The semiconductor device photoetching method comprises steps of: forming a mask layer on the semiconductor device; forming a first photoresistive adhesive layer subjected to ion implantation on a mask in the non-etched region; forming a second photoresistive adhesive layer on the first photoresistive adhesive layer and a mask in the to-be-etched region; and exposing and etching the second photoresistive adhesive layer in the to-be-etched region. According to the method, before the second photoresistive adhesive layer in the to-be-etched region is exposed and etched, the first photoresistive adhesive layer subjected to ion implantation is formed on the mask in the non-etched region. The first photoresistive adhesive layer is capable of reducing damage to the non-etched region in a photoetching process so as to improve the performance of the semiconductor device.
Description
Technical field
The present invention relates to semiconductor integrated circuit technical field, in particular to manufacture method and the flush memory device of a kind of photoetching method of semiconductor device, flush memory device.
Background technology
In the manufacturing process of semiconductor integrated circuit, the height of some device is not identical, forms isolation, and then improve anti-puncture voltage and other performances of transistor between the device making to have different performance.But the device of differing heights can cause chip to top bar the generation of structure, and this ledge structure can affect the technical processs such as follow-up photoetching and ion implantation usually, the manufacturing process of especially step-like grid.Such as, when the grid lower to position carries out the technique such as photoetching and etching, the higher grid in position can sustain damage, and then affects the stability of chip.
Ledge structure is present in flash memory equally.Flash memory comprises memory cell areas and logic circuit area, and wherein memory cell areas comprises the floating boom and control gate that set gradually along the direction away from memory cell areas, and logic circuit area comprises logic gate.Wherein, floating boom and control gate than logic gate height about 100nm, thus define step-like grid structure.When the processing procedure of flash memory is greater than 55nm, usual utilization has the KrF light source (wavelength is 248nm) of larger wavelength or I-line light source (wavelength is 365nm) carries out photoetching to logic gate, in order to avoid control gate is by overetch, face is coated with the photoresistance glue (0.4 μm ~ 3 μm) that last layer has adequate thickness on the control gate usually.When flash memory reach 55nm even less processing procedure time, usually select ArF LASER Light Source (wavelength is 193nm) to carry out photoetching to logic gate.But, in order to improve the thickness equalization of chip entirety, when utilizing ArF LASER Light Source to carry out photoetching, usually the thickness less (0.2 μm ~ 0.5 μm) of required photoresistance glue, therefore carrying out in photoetching and etching process to logic circuit area, damage will certainly caused to the floating boom of memory cell areas and control gate.
In order to avoid photoetching and etching process cause damage to memory cell areas, there are two kinds of ways at present: one is deposit the hard mask of one deck on the control gate as protective layer, but need after photoetching and etching technics complete to remove hard mask with wet etching, wet-etching technology can cause grid to damage further; Two is deposit multilayer photoresistance glue on the control gate, stops the infringement of subsequent technique, but can dissolve between photoresistance glue when utilizing ArF LASER Light Source to carry out photoetching, cause blocking effect not obvious.
Summary of the invention
The application aims to provide a kind of photoetching method of semiconductor device, the manufacture method of flush memory device and flush memory device, to reduce the damage that photoetching process causes device.
In order to solve the problem, this application provides a kind of photoetching method of semiconductor device, this semiconductor device comprises district to be etched and non-etched area, and this photoetching method comprises: form mask layer on the semiconductor device; The mask being positioned at non-etched area is formed the first optical resistance glue layer through ion implantation process; The first optical resistance glue layer and be positioned at district to be etched mask on form the second optical resistance glue layer; The second optical resistance glue layer being positioned at district to be etched is exposed and etched.
Further, in above-mentioned photoetching method, the step forming the first optical resistance glue layer comprises: on mask layer, form the first photoresistance glue preparation layers; Ion implantation process is carried out to the first photoresistance glue preparation layers, forms the first photoresistance glue transition zone; Remove the first photoresistance glue transition zone be positioned in district to be etched, form the first optical resistance glue layer.
Further, in above-mentioned photoetching method, in the step of ion implantation process, injection ion energy is 15keV ~ 50keV, and injection ion concentration is 1E+13atoms/cm
3~ 1E+16atoms/cm
3.
Further, in above-mentioned photoetching method, inject ion and be preferably phosphonium ion or boron ion.
Further, in above-mentioned photoetching method, in the step of formation first optical resistance glue layer, form the first optical resistance glue layer that thickness is 0.2 ~ 3 μm; In the step of formation second optical resistance glue layer, form the second optical resistance glue layer that thickness is 50 ~ 200nm.
Further, in above-mentioned photoetching method, after forming the first optical resistance glue layer, the first optical resistance glue layer is toasted.
Further, in above-mentioned photoetching method, in the step of baking, the temperature of baking is 100 ~ 300 DEG C, and the time of baking is 1 ~ 3min.
Further, in above-mentioned photoetching method, mask layer is antireflecting coating or amorphous carbon layer.
Present invention also provides a kind of manufacture method of flush memory device, this manufacture method comprises: substrate is divided into core memory district and logic circuit area; Core memory district forms first grid, and in logic circuit area, forms second grid preparation layers, the upper surface of first grid is higher than the upper surface of second grid preparation layers; Carry out photoetching and etching to form second grid to second grid preparation layers, the method for photoetching is the above-mentioned photoetching method of the application.
Further, in above-mentioned manufacture method, first grid comprises floating boom and is positioned at the control gate on floating boom, and second grid is logic gate.
Present invention also provides a kind of flush memory device, this flush memory device is made by the manufacture method of the above-mentioned flush memory device of the application.
Application technical scheme, is exposing the second optical resistance glue layer being positioned at district to be etched and before the step etched, the mask being positioned at non-etched area is forming the first optical resistance glue layer through ion implantation process.The intermolecular distance of the first optical resistance glue layer can be shortened by injecting ion, the compact structure of the first optical resistance glue layer is improved.Therefore, this first optical resistance glue layer can stop the etching ion in follow-up photoetching process to enter non-etched features district, thus the damage that minimizing photoetching process causes device, and then improve the performance of semiconductor device.
Accompanying drawing explanation
The accompanying drawing forming a part of the present invention is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 shows the schematic flow sheet of the photoetching method of the semiconductor device that the application's execution mode provides;
Fig. 2 shows in the photoetching method of the semiconductor device that the application's execution mode provides, and forms the cross-sectional view of the matrix after mask layer on the semiconductor device;
Fig. 3 shows the cross-sectional view forming the matrix after the first optical resistance glue layer of ion implantation process on the mask being positioned at the non-etched area shown in Fig. 2;
Fig. 3-1 shows the cross-sectional view of the matrix to form the first photoresistance glue preparation layers on the mask layer shown in Fig. 2 after;
Fig. 3-2 shows and carries out to the first photoresistance glue preparation layers shown in Fig. 3-1 cross-sectional view that ion implantation process forms the matrix after the first photoresistance glue transition zone;
Fig. 4 show the first optical resistance glue layer shown in Fig. 3 and be positioned at district to be etched mask on form the second optical resistance glue layer after the cross-sectional view of matrix;
Fig. 5 shows and to expose the second optical resistance glue layer being positioned at the district to be etched shown in Fig. 4 and the cross-sectional view of matrix after etching.
Embodiment
Describe in more detail below with reference to accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.But the multitude of different ways that the present invention can be defined by the claims and cover is implemented.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
From background technology, photoetching process can cause damage to step-like device.Present inventor studies for the problems referred to above, proposes a kind of photoetching method of semiconductor device, and this semiconductor device comprises district to be etched and non-etched area, and as shown in Figure 1, this photoetching method comprises: form mask layer on the semiconductor device; The mask being positioned at non-etched area is formed the first optical resistance glue layer through ion implantation process; The first optical resistance glue layer and be positioned at district to be etched mask on form the second optical resistance glue layer; The second optical resistance glue layer being positioned at district to be etched is exposed and etched.
In above-mentioned photoetching method, the second optical resistance glue layer being positioned at district to be etched is being exposed and before the step etched, the mask being positioned at non-etched area is forming the first optical resistance glue layer through ion implantation process.Inject the intermolecular distance that ion can shorten the first optical resistance glue layer, the compact structure of the first optical resistance glue layer is improved.Therefore, this first optical resistance glue layer can stop the etching ion in follow-up photoetching process to enter non-etched features district, thus the damage that minimizing photoetching process causes device, and then improve the performance of semiconductor device.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
Fig. 2 to Fig. 5 shows the cross-sectional view formed after each step in the photoetching method of the semiconductor device that the application provides.In order to further illustrate the photoetching method that the application provides, set forth the photoetching method of the semiconductor device that the application provides further below in conjunction with Fig. 2 to Fig. 5.
First, form mask layer 30 on the semiconductor device, and then form basal body structure as shown in Figure 2.Above-mentioned mask layer 30 can be mask material common in this area, and in a preferred embodiment, the material of above-mentioned mask layer 30 is antireflecting coating BARC or agraphitic carbon.The technique forming above-mentioned mask layer 30 can be spin coating etc.When adopting spin coating to form above-mentioned mask layer 30, in a kind of optional execution mode, comprising the following steps: mask material is dripped on wafer, accelerating to rotate, mask material is evenly coated on district 23 to be etched and non-etched area 21.Above-mentioned semiconductor device is formed with on substrate 10, alternatively, above-mentioned semiconductor device is grid, and the non-etched area 21 of semiconductor device is first grid, the district to be etched 23 of semiconductor device is second grid preparation layers, and the upper surface of non-etched area 21 is higher than the upper surface of etched area.Exemplarily, be described with the structure shown in Fig. 2 below.
After completing the step forming mask layer 30 on the semiconductor device, the mask being positioned at non-etched area 21 forms the first optical resistance glue layer 40 through ion implantation process, and then form basal body structure as shown in Figure 3.In a preferred embodiment, the step forming the first optical resistance glue layer 40 comprises: on mask layer 30, form the first photoresistance glue preparation layers 40 ', and then forms basal body structure as shown in figure 3-1; Ion implantation process is carried out to the first photoresistance glue preparation layers 40 ' and forms the first photoresistance glue transition zone 40 ", and then form basal body structure as shown in figure 3-2; Remove the first photoresistance glue transition zone 40 be positioned in district 23 to be etched ", form the first optical resistance glue layer 40, and then form basal body structure as shown in Figure 3.
The material of above-mentioned first photoresistance glue preparation layers 40 ' can be DUV248nm photoresistance or DUV365nm photoresistance, and the technique forming above-mentioned first photoresistance glue preparation layers 40 ' can be spin coating etc.When adopting spin coating to form above-mentioned first photoresistance glue preparation layers 40 ', in a kind of optional execution mode, comprise the following steps: dripped on wafer by photoresist, accelerate to rotate, photoresist is evenly coated on district 23 to be etched and non-etched area 21.
Above-mentioned photoresist mixes primarily of resin, emulsion and solvent three kinds of compositions.In the spin coating proceeding of existing multilayer photoresist, the solvent in the photoresist of rear coating can dissolve the resin in front one deck photoresist, makes to dissolve each other between photoresist, affects the accuracy of subsequent optical carving technology.In order to reduce dissolving each other between above-mentioned photoresist, the application carries out ion implantation to the first photoresistance glue preparation layers 40 ', its technical process principle is: the ion produced by ion source is high fast direction first photoresistance glue preparation layers 40 ' surface after accelerating, when ion enters surface, by with the atomic collision in the first photoresistance glue preparation layers 40 ', thus enter in the first photoresistance glue preparation layers 40 '; There is cross-linking reaction in injection ion and the first photoresistance glue preparation layers 40 ', forms X-C
6h
5(X is for injecting ion), thus at the middle formation " X-C of the first photoresistance glue preparation layers 40 '
6h
5cross-linked layer ".At " X-C
6h
5cross-linked layer " in; inject ion and can occupy the position of the molecule of part first photoresistance glue preparation layers 40 '; thus shorten the intermolecular distance of the first photoresistance glue preparation layers 40 '; make the middle network configuration of the first photoresistance glue preparation layers 40 ' finer and close, thus make the first photoresistance glue preparation layers 40 ' can not by the dissolution with solvents in the photoresist of rear coating.Preferably, the process conditions of above-mentioned ion implantation are: injection ion energy is 15 ~ 50keV, and injection ion concentration is 1E+13atoms/cm
3~ 1E+16atoms/cm
3, inject ion and be preferably phosphonium ion or boron ion.
In the optional execution mode of one, the step removing the above-mentioned first photoresistance glue preparation layers 40 ' be positioned in district 23 to be etched comprises: carry out exposure-processed to the first photoresistance glue preparation layers 40 ' after ion implantation, remove the photoresistance glue on etched area, form the first optical resistance glue layer 40.Preferably, the thickness of the first optical resistance glue layer 40 is 0.2 ~ 3 μm.
After above-mentioned first optical resistance glue layer 40 of formation, can also toast the first photoresistance glue, to improve the compactness of the first optical resistance glue layer 40, and strengthen the adhesion between the first optical resistance glue layer 40 and district to be etched 23.The step of above-mentioned bake process comprises: be placed in by the chip comprising the first photoresistance glue to make chip surface contact with hot plate on hot plate, then toast the first photoresistance glue under uniform temperature condition, evaporate the solvent in the first optical resistance glue layer 40.Preferably, the temperature of baking is 100 DEG C ~ 300 DEG C, and the time of baking is 1 ~ 3min.
Complete and formed after the step of the first optical resistance glue layer 40 of ion implantation process on the mask being positioned at non-etched area 21, the first optical resistance glue layer 40 and be positioned at district 23 to be etched mask on form the second optical resistance glue layer 50, and then form basal body structure as shown in Figure 4.The material of above-mentioned second optical resistance glue layer 50 can be DUV193nm photoresistance, and the technique forming above-mentioned second optical resistance glue layer 50 can be spin coating etc.When adopting spin coating to form above-mentioned second optical resistance glue layer 50, in a kind of optional execution mode, comprise the following steps: photoresist is dripped on wafer, accelerate rotating wafer, photoresist is coated be evenly coated on district 23 to be etched and non-etched area 21, thus forms the second optical resistance glue layer 50.Preferably, the thickness of the second photoresistance glue is 50 ~ 200nm.
The second optical resistance glue layer 50 being positioned at district 23 to be etched is exposed and etched, and then forms basal body structure as shown in Figure 5.Above-mentioned steps comprises: carry out exposure imaging to the second photoresist layer, then with the second optical resistance glue layer 50 after exposure imaging for mask, etch to form required device to mask layer 30 and district to be etched 23.Above-mentioned etching can be wet etching, and above-mentioned technique is state of the art, does not repeat them here.
Present invention also provides a kind of manufacture method of flush memory device, this manufacture method comprises: substrate is divided into core memory district and logic circuit area; Core memory district forms first grid, and in logic circuit area, forms second grid preparation layers, the upper surface of first grid is higher than the upper surface of second grid preparation layers; Carry out photoetching and etching to form second grid to second grid preparation layers, the method for photoetching is the above-mentioned photoetching method of the application.The grid structure of the flush memory device that the photoetching method adopting the application to provide obtains stands intact, and the stability of device is improved.
In a preferred embodiment, above-mentioned first grid comprises floating boom and is positioned at the control gate on floating boom, and above-mentioned second grid is logic gate.Above-mentioned manufacture method comprises further: in the above-mentioned making bit line in the core memory district of Semiconductor substrate and wordline, interlayer dielectric layer, planarization, deposit passivation layer and subsequent encapsulating process.These techniques are state of the art, do not repeat them here.
Present invention also provides a kind of flush memory device, this flush memory device is made by the manufacture method of the above-mentioned flush memory device of the application.The grid structure of this flush memory device stands intact, and the stability of device is improved.
The manufacture method of photoetching method that the application provides and flush memory device will be further illustrated below with specific embodiment.
Embodiment 1
The manufacture method of the flush memory device that the present embodiment provides comprises the following steps:
Substrate is divided into core memory district and logic circuit area, and forms first grid in core memory district, and in logic circuit area, form second grid preparation layers, the upper surface of first grid is higher than the upper surface of second grid preparation layers;
First grid and second grid preparation layers are formed antireflecting coating and the first photoresistance glue preparation layers (DUV248nm photoresistance) successively, and wherein the thickness of antireflecting coating is 0.4 μm, and the thickness of the first photoresistance glue preparation layers is 0.2 μm; Carry out ion implantation process to the first photoresistance glue preparation layers, form the first photoresistance glue transition zone, injection ion is phosphonium ion, and injection ion energy is 15keV, and injection ion concentration is 1E+13atoms/cm
3; Remove the first photoresistance glue transition zone be positioned in second grid preparation layers, form the first optical resistance glue layer; Toast the first optical resistance glue layer, the temperature of wherein toasting is 100 DEG C, and the time of described baking is 3min;
The first optical resistance glue layer and be positioned at logic circuit area mask on form the second optical resistance glue layer, wherein the thickness of the second optical resistance glue layer is 50nm; The second optical resistance glue layer being positioned at logic circuit area is exposed and carries out etching and form opening, and form second grid along opening etching antireflecting coating and second grid preparation layers.
Embodiment 2
The manufacture method of the flush memory device that the present embodiment provides comprises the following steps:
Substrate is divided into core memory district and logic circuit area, and forms first grid in core memory district, and in logic circuit area, form second grid preparation layers, the upper surface of first grid is higher than the upper surface of second grid preparation layers;
First grid and second grid preparation layers are formed antireflecting coating and the first photoresistance glue preparation layers (DUV248nm photoresistance) successively, and wherein the thickness of antireflecting coating is 0.4 μm, and the thickness of the first photoresistance glue preparation layers is 3 μm; Carry out ion implantation process to the first photoresistance glue preparation layers, form the first photoresistance glue transition zone, injection ion is phosphonium ion, and injection ion energy is 50keV, and injection ion concentration is 1E+16atoms/cm
3; Remove the first photoresistance glue transition zone be positioned in second grid preparation layers, form the first optical resistance glue layer; Toast the first optical resistance glue layer, the temperature of wherein toasting is 300 DEG C, and the time of described baking is 1min;
The first optical resistance glue layer and be positioned at logic circuit area mask on form the second optical resistance glue layer, wherein the thickness of the second optical resistance glue layer is 200nm; The second optical resistance glue layer being positioned at logic circuit area is exposed and carries out etching and form opening, and form second grid along opening etching antireflecting coating and second grid preparation layers.
Embodiment 3
The manufacture method of the flush memory device that the present embodiment provides comprises the following steps:
Substrate is divided into core memory district and logic circuit area, and forms first grid in core memory district, and in logic circuit area, form second grid preparation layers, the upper surface of first grid is higher than the upper surface of second grid preparation layers;
First grid and second grid preparation layers are formed antireflecting coating and the first photoresistance glue preparation layers (DUV248nm photoresistance) successively, and wherein the thickness of antireflecting coating is 0.4 μm, and the thickness of the first photoresistance glue preparation layers is 1 μm; Carry out ion implantation process to the first photoresistance glue preparation layers, form the first photoresistance glue transition zone, injecting ion is boron ion, and injection ion energy is 30keV, and injection ion concentration is 1E+15atoms/cm
3; Remove the first photoresistance glue transition zone be positioned in second grid preparation layers, form the first optical resistance glue layer; Toast the first optical resistance glue layer, the temperature of wherein toasting is 200 DEG C, and the time of described baking is 2min;
The first optical resistance glue layer and be positioned at logic circuit area mask on form the second optical resistance glue layer, wherein the thickness of the second optical resistance glue layer is 100nm; The second optical resistance glue layer being positioned at logic circuit area is exposed and carries out etching and form opening, and form second grid along opening etching antireflecting coating and second grid preparation layers.
Embodiment 4
The manufacture method of the flush memory device that the present embodiment provides comprises the following steps:
Substrate is divided into core memory district and logic circuit area, and forms first grid in core memory district, and in logic circuit area, form second grid preparation layers, the upper surface of first grid is higher than the upper surface of second grid preparation layers;
First grid and second grid preparation layers are formed antireflecting coating and the first photoresistance glue preparation layers (DUV248nm photoresistance) successively, and wherein the thickness of antireflecting coating is 0.4 μm, and the thickness of the first photoresistance glue preparation layers is 3.2 μm; Carry out ion implantation process to the first photoresistance glue preparation layers, form the first photoresistance glue transition zone, injection ion is phosphonium ion, and injection ion energy is 52keV, and injection ion concentration is 1.2E+16atoms/cm
3; Remove the first photoresistance glue transition zone be positioned in second grid preparation layers, form the first optical resistance glue layer; Toast the first optical resistance glue layer, the temperature of wherein toasting is 320 DEG C, and the time of described baking is 4min;
The first optical resistance glue layer and be positioned at logic circuit area mask on form the second optical resistance glue layer, wherein the thickness of the second optical resistance glue layer is 220nm; The second optical resistance glue layer being positioned at logic circuit area is exposed and carries out etching and form opening, and form second grid along opening etching antireflecting coating and second grid preparation layers.
Comparative example 1
The manufacture method of the flush memory device that the present embodiment provides comprises the following steps:
Substrate is divided into core memory district and logic circuit area, and forms first grid in core memory district, and in logic circuit area, form second grid preparation layers, the upper surface of first grid is higher than the upper surface of second grid preparation layers;
First grid and second grid preparation layers are formed antireflecting coating and optical resistance glue layer (DUV248nm photoresistance) successively, and wherein the thickness of antireflecting coating is 0.4 μm, and the thickness of optical resistance glue layer is 2 μm;
The optical resistance glue layer being positioned at logic circuit area is exposed and carries out etching and form opening, and form second grid along opening etching antireflecting coating and second grid preparation layers.
Test: adopt scanning electron microscopic observation embodiment 1 to 4 and comparative example 1 to obtain the microscopic appearance of device, and the degree of depth measuring first grid pothole on the surface, to characterize the damage that photoetching process causes first grid.Dependence test result asks for an interview table 1.
Table 1
| The degree of depth of pothole | |
| Embodiment 1 | 12nm |
| Embodiment 2 | 11nm |
| Embodiment 3 | 13nm |
| Embodiment 4 | 16nm |
| Comparative example 1 | 54nm |
Data as can be seen from table 1, the degree of depth of the first grid that embodiment 1 to 4 obtains pothole is on the surface 11 ~ 16nm, and the degree of depth of the first grid that comparative example 1 obtains pothole is on the surface 54nm.Visible, in embodiment 1 to 4, photoetching process is significantly less than to the damage that first grid causes the damage that in comparative example 1, photoetching process causes first grid.
As can be seen from the above embodiments, the above-mentioned example of the application achieves following technique effect: exposing the second optical resistance glue layer being positioned at district to be etched and before the step etched, the mask being positioned at non-etched area forming the first optical resistance glue layer through ion implantation process.Inject the intermolecular distance that ion can shorten the first optical resistance glue layer, the compact structure of the first optical resistance glue layer is improved.Therefore, this first optical resistance glue layer can stop the etching ion in follow-up photoetching process to enter non-etched features district, thus decreases the damage that photoetching process causes device, and then improves the performance of semiconductor device.
These are only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (11)
1. a photoetching method for semiconductor device, described semiconductor device comprises district to be etched and non-etched area, it is characterized in that, described photoetching method comprises:
Described semiconductor device forms mask layer;
The mask being positioned at described non-etched area is formed the first optical resistance glue layer through ion implantation process;
Described first optical resistance glue layer and be positioned at described district to be etched mask on form the second optical resistance glue layer;
The second optical resistance glue layer being positioned at described district to be etched is exposed and etched.
2. photoetching method according to claim 1, is characterized in that, the step forming described first optical resistance glue layer comprises:
Described mask layer is formed the first photoresistance glue preparation layers;
Ion implantation process is carried out to described first photoresistance glue preparation layers, forms the first photoresistance glue transition zone;
Remove the described first photoresistance glue transition zone be positioned in described district to be etched, form described first optical resistance glue layer.
3. photoetching method according to claim 1 and 2, is characterized in that, in the step of described ion implantation process, injection ion energy is 15keV ~ 50keV, and injection ion concentration is 1E+13atoms/cm
3~ 1E+16atoms/cm
3.
4. photoetching method according to claim 3, is characterized in that, described injection ion is preferably phosphonium ion or boron ion.
5. photoetching method according to claim 1 and 2, is characterized in that,
In the step forming described first optical resistance glue layer, form described first optical resistance glue layer that thickness is 0.2 ~ 3 μm;
In the step forming described second optical resistance glue layer, form described second optical resistance glue layer that thickness is 50 ~ 200nm.
6. photoetching method according to claim 1 and 2, is characterized in that, before forming the step of described second optical resistance glue layer, toasts described first optical resistance glue layer.
7. photoetching method according to claim 6, is characterized in that, in the step of described baking, the temperature of described baking is 100 ~ 300 DEG C, and the time of described baking is 1 ~ 3min.
8. photoetching method according to claim 1 and 2, is characterized in that, described mask layer is antireflecting coating or amorphous carbon layer.
9. a manufacture method for flush memory device, is characterized in that, described manufacture method comprises:
Substrate is divided into core memory district and logic circuit area;
Described core memory district forms first grid, and form second grid preparation layers in described logic circuit area, the upper surface of described first grid is higher than the upper surface of described second grid preparation layers;
Photoetching is carried out to described second grid preparation layers and etches to form second grid, the photoetching method of method according to any one of claim 1 to 9 of described photoetching.
10. manufacture method according to claim 9, is characterized in that, described first grid comprises floating boom and is positioned at the control gate on described floating boom, and described second grid is logic gate.
11. 1 kinds of flush memory devices, is characterized in that, described flush memory device is made by the manufacture method described in claim 9 or 10.
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| CN107437547A (en) * | 2016-05-26 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of semiconductor devices |
| CN108288581A (en) * | 2018-01-26 | 2018-07-17 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
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| CN102034691A (en) * | 2009-09-24 | 2011-04-27 | 上海华虹Nec电子有限公司 | Method for applying deep-UV photoresist to wet etching |
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| CN108288581A (en) * | 2018-01-26 | 2018-07-17 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
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