CN105448811A - Double-aluminium technology - Google Patents
Double-aluminium technology Download PDFInfo
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- CN105448811A CN105448811A CN201410295532.2A CN201410295532A CN105448811A CN 105448811 A CN105448811 A CN 105448811A CN 201410295532 A CN201410295532 A CN 201410295532A CN 105448811 A CN105448811 A CN 105448811A
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Abstract
The invention discloses a double-aluminium technology, and the technology comprises the steps: taking a silicon wafer as a substrate, and forming a first oxidation layer on the substrate; forming a first metal layer on the first oxidation layer; forming an intermetallic dielectric layer on the first metal layer; etching and filling a through hole in the intermetallic dielectric layer; forming a second metal layer on the intermetallic dielectric layer; forming a passivation layer on the surface of the second metal layer, and exposing a bonding pad window. The material of the first metal layer and the material of the second metal layer are aluminium or aluminium copper alloys. The technology can design a large-current channel.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to a kind of two aluminium technique.
Background technology
Along with the development of integrated circuit processing technique, high power device is more and more stricter to the requirement of its rated current, and this constantly has new technology to support with regard to needing the product requirement constantly promoted.
For existing aluminum manufacturing procedure integrated circuit technology, only have layer of metal to adopt thick aluminium technique, the high power device designed like this can't realize big current passage.
Summary of the invention
Based on this, be necessary to provide a kind of two aluminium techniques that can realize big current passage.
A kind of two aluminium technique, comprising:
Using silicon wafer as substrate, form the first oxide layer over the substrate;
Described first oxide layer forms the first metal layer;
Described the first metal layer forms metal intermetallic dielectric layer;
Etching also filling vias in described metal intermetallic dielectric layer;
Described metal intermetallic dielectric layer is formed the second metal level;
Passivation layer is formed at described second layer on surface of metal, and exposed pad window;
Wherein, the material of described the first metal layer and the second metal level is aluminium or aluminium copper.
Wherein in an embodiment, the generation type of described first oxide layer, the first metal layer, the second metal level, passivation layer is CVD (Chemical Vapor Deposition) method or sputtering method.
Wherein in an embodiment, the thickness of described the first metal layer is greater than 600 nanometers.
Wherein in an embodiment, the thickness of described second metal level is greater than 600 nanometers.
Wherein in an embodiment, the step that described the first metal layer is formed metal intermetallic dielectric layer comprises:
Deposit silicon rich oxide on described the first metal layer, forms silicon rich oxide layer;
Deposit fluorine silex glass on described silicon rich oxide layer, forms fsg film;
Deposit tetraethoxysilane on described fsg film, forms the second oxide layer;
The mode of chemico-mechanical polishing is adopted described metal intermetallic dielectric layer to be polished.
Wherein in an embodiment, the thickness of described silicon rich oxide layer, fsg film, the second oxide layer is respectively 35 nanometers, 600 nanometers, 350 nanometers.
Wherein in an embodiment, the step etching also filling vias in described metal intermetallic dielectric layer comprises:
Make the litho pattern mask of through hole by lithography, adopt dry etch process to form through hole;
Form barrier layer at the surface sputtering method of described through hole, then use CVD (Chemical Vapor Deposition) method deposition tungsten filling vias.
Wherein in an embodiment, described barrier layer comprises titanium and titanium nitride.
Wherein in an embodiment, the Si oxide formed when described first oxide layer is tetraethoxysilane deposition.
Wherein in an embodiment, the step forming passivation layer at described second metal level comprises:
Deposit fluorine silex glass on described second metal level, forms fsg film;
Deposit silicon rich oxide on described fsg film, forms silicon rich oxide layer;
Deposited silicon nitride layer on described silicon rich oxide layer;
Described silicon nitride is formed the litho pattern mask of pad openings, adopts dry etch process to form pad openings.
Above-mentioned pair of aluminium technique makes it have two-layer aluminium or aluminium copper by formation the first metal layer and the second metal level, which decreases conductor resistance, can design big current passage.
Accompanying drawing explanation
Fig. 1 is two aluminium process charts of an embodiment;
Fig. 2 is the schematic diagram after middle formation the first metal layer embodiment illustrated in fig. 1;
Fig. 3 is the schematic diagram after middle etching through hole embodiment illustrated in fig. 1;
Fig. 4 is the schematic diagram after middle formation second metal level embodiment illustrated in fig. 1;
Fig. 5 is middle formation passivation layer embodiment illustrated in fig. 1 and schematic diagram after exposed pad window.
Embodiment
Please see figures.1.and.2 respectively ~ 5, be two aluminium process chart of an embodiment and the schematic diagram of correspondence thereof.
This pair of aluminium technique comprises:
Step S110: using silicon wafer as substrate, forms the first oxide layer over the substrate.
In the present embodiment, the size of silicon wafer 110 is 8 inches, with CVD (Chemical Vapor Deposition) method (CVD, ChemicalVaporDeposition) deposit tetraethoxysilane (TEOS) on silicon wafer 110, form by chemical reaction the first oxide layer 120 that thickness is 700 nanometers.
Step S120: form the first metal layer in described first oxide layer.
In the present embodiment, adopt sputtering method (Sputter) in the first oxide layer 120, form the first metal layer 130 that thickness is 800 nanometers.Wherein, the first metal layer 130 is the aluminium being mixed with a small amount of copper, and the content of copper is 0.5% in the present embodiment.
Be appreciated that the present invention also can be applied to the silicon wafer of other sizes according to actual needs, the generation type of the first oxide layer 120 and the first metal layer 130 can be any one mode in CVD (Chemical Vapor Deposition) method and sputtering method, is not construed as limiting here.In addition, the thickness of the first metal layer 130 is also not limited to 800 nanometers, and the thickness of the first metal layer 130 should be greater than 600 nanometers.The first metal layer 130 can be also fine aluminium, namely only uses aluminum metal.
Step S130: form metal intermetallic dielectric layer on described the first metal layer.
In the present embodiment, metal intermetallic dielectric layer (IMD, InterMetalDielectric) 140 comprise the silicon rich oxide (SRO that thickness is 35 nanometers, SiliconRichOxide), the fluorine silex glass (FSG, FluorinSiliconGlass) of 600 nanometers and the second oxide layer of 350 nanometers.
Step S130 is specially:
Deposit silicon rich oxide on the first metal layer 130, forms silicon rich oxide layer;
Deposit fluorine silex glass on described silicon rich oxide layer, forms fsg film;
Deposit tetraethoxysilane on described fsg film, forms the second oxide layer;
The mode of chemico-mechanical polishing is adopted metal intermetallic dielectric layer 140 to be polished.
Step S140: etching also filling vias in described metal intermetallic dielectric layer.
In the present embodiment, step S140 is specially:
Make the litho pattern mask of through hole by lithography, adopt dry etch process to form through hole 150;
Form barrier layer at the surface sputtering method of described through hole 150, then use CVD (Chemical Vapor Deposition) method deposition tungsten filling vias.
Wherein, described barrier layer comprises titanium and 6 Nano titanium nitrides of 15 nanometers, and the lateral dimension on described through hole 150 surface is 360 nanometers, and tungsten is filled from the sidewall of through hole 150, and the lateral dimension of tungsten is 400 nanometers.
Step S150: form the second metal level in described metal intermetallic dielectric layer.
In the present embodiment, adopt sputtering method in metal intermetallic dielectric layer 140, form the second metal level 160 of 800 nanometers.Wherein, the second metal level 160 is the aluminium being mixed with a small amount of copper, and the content of copper is 0.5% in the present embodiment.
Be appreciated that in other embodiments, the generation type of the second metal level 160 can also be CVD (Chemical Vapor Deposition) method, is not construed as limiting here.In addition, the thickness of the second metal level 160 is also not limited to 800 nanometers, and the thickness of the second metal level 160 should be greater than 600 nanometers.Second metal level 160 can be also fine aluminium, namely only uses aluminum metal.
Step S160: form passivation layer at described second layer on surface of metal, and exposed pad window.
In the present embodiment, passivation layer 170 comprises the silicon nitride layer of the fluorine silex glass of 1000 nanometers, the silicon rich oxide of 150 nanometers and 500 nanometers.
Step S160 is specially:
Deposit fluorine silex glass on the second metal level 160, forms fsg film;
Deposit silicon rich oxide on described fsg film, forms silicon rich oxide layer;
Deposited silicon nitride layer on described silicon rich oxide layer;
Described silicon nitride is formed the litho pattern mask of pad (PAD) window 180, adopts dry etch process to form pad openings 180.
Be appreciated that in other embodiments, the metal level that multilayer uses aluminium or aluminium copper material can also be designed.
Above-mentioned pair of aluminium technique makes it have two-layer aluminium or aluminium copper by formation the first metal layer and the second metal level, which decreases conductor resistance, can design big current passage.
About above-mentioned technique, have selected 5 different test points respectively to the square resistance of the first metal layer and the second metal level, two-layer between electric leakage, two-layer between through hole resistance three electrical parameters test.Concrete outcome please refer to table 1.In the design size of resolution chart, 0.44/0.46 represent the first metal layer and the second metal level width and two-layer between distance, 0.36/0.36 represents the spacing of through-hole surfaces width and through hole.Test point 1, test point 2, test point 3, test point 4, test point 5 represent same pair of structural five the different test positions of aluminum-copper alloy layer, and the numeral below it is the test data of parameters.
Table 1 pair aluminium copper Rotating fields electrical parameter test chart
As can be seen from above test data, the parameters of the first metal layer and the second metal level all meets technological specification.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a two aluminium technique, is characterized in that, comprising:
Using silicon wafer as substrate, form the first oxide layer over the substrate;
Described first oxide layer forms the first metal layer;
Described the first metal layer forms metal intermetallic dielectric layer;
Etching also filling vias in described metal intermetallic dielectric layer;
Described metal intermetallic dielectric layer is formed the second metal level;
Passivation layer is formed at described second layer on surface of metal, and exposed pad window;
Wherein, the material of described the first metal layer and the second metal level is aluminium or aluminium copper.
2. according to claim 1 pair of aluminium technique, is characterized in that, the generation type of described first oxide layer, the first metal layer, the second metal level, passivation layer is CVD (Chemical Vapor Deposition) method or sputtering method.
3. according to claim 1 pair of aluminium technique, is characterized in that, the thickness of described the first metal layer is greater than 600 nanometers.
4. according to claim 1 pair of aluminium technique, is characterized in that, the thickness of described second metal level is greater than 600 nanometers.
5. according to claim 1 pair of aluminium technique, is characterized in that, the step that described the first metal layer is formed metal intermetallic dielectric layer comprises:
Deposit silicon rich oxide on described the first metal layer, forms silicon rich oxide layer;
Deposit fluorine silex glass on described silicon rich oxide layer, forms fsg film;
Deposit tetraethoxysilane on described fsg film, forms the second oxide layer;
The mode of chemico-mechanical polishing is adopted described metal intermetallic dielectric layer to be polished.
6. according to claim 5 pair of aluminium technique, is characterized in that, the thickness of described silicon rich oxide layer, fsg film, the second oxide layer is respectively 35 nanometers, 600 nanometers, 350 nanometers.
7. according to claim 1 pair of aluminium technique, is characterized in that, the step etching also filling vias in described metal intermetallic dielectric layer comprises:
Make the litho pattern mask of through hole by lithography, adopt dry etch process to form through hole;
Form barrier layer at the surface sputtering method of described through hole, then use CVD (Chemical Vapor Deposition) method deposition tungsten filling vias.
8. according to claim 7 pair of aluminium technique, is characterized in that, described barrier layer comprises titanium and titanium nitride.
9. according to claim 1 pair of aluminium technique, is characterized in that, the Si oxide formed when described first oxide layer is tetraethoxysilane deposition.
10. according to claim 1 pair of aluminium technique, is characterized in that, the step forming passivation layer at described second metal level comprises:
Deposit fluorine silex glass on described second metal level, forms fsg film;
Deposit silicon rich oxide on described fsg film, forms silicon rich oxide layer;
Deposited silicon nitride layer on described silicon rich oxide layer;
Described silicon nitride is formed the litho pattern mask of pad openings, adopts dry etch process to form pad openings.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040155349A1 (en) * | 2003-01-07 | 2004-08-12 | Naofumi Nakamura | Semiconductor device and method of fabricating the same |
| CN101533767A (en) * | 2008-12-31 | 2009-09-16 | 昆山锐芯微电子有限公司 | Semiconductor device, metal-insulator-metal capacitor and method for manufacturing same |
| CN101752296A (en) * | 2008-12-10 | 2010-06-23 | 和舰科技(苏州)有限公司 | Method for improving flatness of dielectric layer between metal layers |
| CN102130091A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Composite through-hole interconnecting structure for integrated circuit chip and preparation method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040155349A1 (en) * | 2003-01-07 | 2004-08-12 | Naofumi Nakamura | Semiconductor device and method of fabricating the same |
| CN101752296A (en) * | 2008-12-10 | 2010-06-23 | 和舰科技(苏州)有限公司 | Method for improving flatness of dielectric layer between metal layers |
| CN101533767A (en) * | 2008-12-31 | 2009-09-16 | 昆山锐芯微电子有限公司 | Semiconductor device, metal-insulator-metal capacitor and method for manufacturing same |
| CN102130091A (en) * | 2010-12-17 | 2011-07-20 | 天津理工大学 | Composite through-hole interconnecting structure for integrated circuit chip and preparation method thereof |
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