CN105431861A - Charge distribution control for secure systems - Google Patents

Charge distribution control for secure systems Download PDF

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Publication number
CN105431861A
CN105431861A CN201480029850.2A CN201480029850A CN105431861A CN 105431861 A CN105431861 A CN 105431861A CN 201480029850 A CN201480029850 A CN 201480029850A CN 105431861 A CN105431861 A CN 105431861A
Authority
CN
China
Prior art keywords
charge
power supply
storage device
charge storage
logical block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201480029850.2A
Other languages
Chinese (zh)
Inventor
丹尼尔·F·亚尼特
布伦特·阿诺德·迈尔斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chaologix Inc
Original Assignee
Chaologix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/906,542 external-priority patent/US8912814B2/en
Priority claimed from US14/184,088 external-priority patent/US8912816B2/en
Application filed by Chaologix Inc filed Critical Chaologix Inc
Priority to CN202011140986.4A priority Critical patent/CN112165251A/en
Publication of CN105431861A publication Critical patent/CN105431861A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/20—Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Abstract

Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device (12), a logic block (10), and connections to a power supply (14). The charge storage device may be a capacitor (12). The capacitor or other charge storage device (12) can be disconnected from the logic block (10) and a power supply (14) to discharge the capacitor (12), and then connected to the power supply (14), via the power supply connections (18, 20), to charge the capacitor (12). The capacitor (12) can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply (14), the capacitor (12) can also be disconnected from the power supply (14), including ground, and connected to the logic block (10) to power the logic block.

Description

Electric charge for security system distributes control
Background technology
Nowadays there are many safety applications, wherein protect Electronic saving and/or process data to be very important.Safety applications now can be carried out in a lot of fields, comprises atm card, I.D., stored value card, credit card, mobile phone (such as, SIM card), and computer access controls, pay TV, and medical information stores.The safety of these cards and application often depends on the cryptographic calculations of the key of the storer (or other circuit) embedding card.Assailant attempts from card, extract these keys, so that the content of amendment card, creates a card copied, or produces a undelegated transaction.Active attack can leave the mark of apparent interference, and passive attack can not leave mark usually.
In a passive attack, information and reader mutual time, information is collected from card.Passive attack can be the form of bypass attack.Bypass attack comprises in the physics realization based on card or circuit decodes key, and this is that power consumption, electromagnetic field, even sound realizes by noting temporal information.Such as, the electric current during the switching of logic gate is changed (and the power signal caused) and can be monitored by supply line, and for decoding key, wherein logic gate is the ingredient of smart card.The attack of this type, is also referred to as Differential Power Analysis (DPA), has many negative effects (such as to the holder of smart card, one atm card can be invaded, and for the account from card owner, without the mandate of card owner, extract cash).Keep data security, and protect it to avoid bypass attack, comprise DPA and attack, continue to become an important design consideration.
Summary of the invention
The invention discloses a kind of safety circuit, system and method.Logical block can protect the safety of different application, comprises the cryptographic block providing and run cryptographic algorithm.
Describing a kind of electric charge herein and distribute control, buffer circuit system can be carried out by suppressing the mode of signal and function,
This signal and function are that the circuit that detected by power supply or ground wire or logical block are produced.In certain embodiments, electric charge distributes control can be a clock charging mechanism.The timing of clock charging mechanism can be cycle or random (or comprising the random cycle).At some in other embodiment, electric charge distributes control can comprise a self clock circuit, such as, can use asynchronous, based on the network postponed.According to the present invention, provide a clock charging mechanism, it has isolated logical block from power supply, and in a kind of mode that the state of logical block can be made not to be decrypted, leakproof be logical block charging.The clock charging mechanism of logical block inhibits the power signal of logical block to be read out, and this is by comprising in supply voltage and grounding connection from outside, and simultaneously the height of isolation logic unit and low power cable realize.
Embodiments of the invention provide capacitive charging, for running a logical block (with other circuit modules).Capacitive charging, by least one logical transition or switching cycle, is set up in a kind of mode of abundance, with the equipment of operation logic block.Charging controlling mechanism relates to one or more clock and/or self clock circuit.In a specific clock example, provide at least two clocks, a clock is used for the logic of a certain speed performance element, and another clock is used for being a charge storage device discharge and recharge between logical operation.In the embodiment of a non-timing, self-timing circuit can be used for the charging and discharging of a control Electricity storage device.
A digital logic unit of embodiments of the invention can comprise an electric capacity, the charging and discharging that electric capacity can be controlled, to provide one " isolation " or " decoupling " between the logical block and power supply of digital logic unit.
Control to describe in detail in this article although the electric charge of digital logic unit and circuit distributes, embodiment is not limited to digital logic unit and block.Various embodiment is included in the mimic channel run same supply voltage is connected isolation during with ground.
The method of control capacitance discharge and recharge is undertaken by blocked operation, comprises the steps: when electric capacity is opened from logical block and power interruption, connects the two ends of electric capacity, so that short circuit capacitance, and allows capacitor discharge; After capacitor discharge completes, connect electric capacity to power supply, think capacitor charging; Be, after capacitor charging completes, electric capacity is opened from power interruption at power supply; And be after capacitor charging completes at power supply, connect electric capacity to logical block, think that logical block provides electric power.In an embodiment, in the guide rail of the logical block of isolation, also may comprise add-on assemble, support that electric capacity is not connected to the operation (if or electric capacity do not carry enough electricity) of logical block.
This explanation selectively describes some concepts in a kind of mode of simplification, and these concepts can further be described in detail below.The key feature or the essential characteristic that mark this theme are not attempted in this explanation, do not attempt the scope for limiting this theme yet.
Accompanying drawing explanation
According to the present invention, Fig. 1 is the schematic diagram of clock charging territory logic (CCDL) unit.
Fig. 2 A-2C shows the example of use mos field effect transistor (MOSFET) discharge switch of some embodiment of the present invention.
According to the present invention, Fig. 3 A-3D describes a clock charging territory logic unit operation method.
According to the present invention, Fig. 4 is the schematic diagram of a clock charging territory logical block example.
According to the present invention, Fig. 5 is the clock sequence of logical block.
According to the present invention, Fig. 6 is the structure simulation figure of logical block.
Fig. 7 capacitor discharge figure.
According to the present invention, Fig. 8 is a circuit diagram.
According to the present invention, it is the circuit diagram that a 2bit cryptographic block is implemented that Fig. 9 A-9D combines.
Figure 10 is the signal graph of the cryptographic block operation of Figure 11.
According to the present invention, Figure 11 is the output signal diagram of internal logic electric wire in a CCDL unit.
According to the present invention, Figure 12 is an AES encryption core power signal graph of composition CCDL unit.
Figure 13 shows that an illustration that can be used for electric charge and distribute the synchronous electric charge distribution clock generator controlled.
Figure 14 shows that an illustration that can be used for electric charge and distribute the incoherent CHARGE DISTRIBUTION clock generator controlled.
Figure 15 shows that an illustration that can be used for electric charge and distribute the determinacy CHARGE DISTRIBUTION clock generator controlled.
Figure 16 shows that an illustration that can be used for electric charge and distribute the asynchronous CHARGE DISTRIBUTION clock generator controlled.
Embodiment
The invention discloses a kind of safety circuit, system and technology.Electric charge distributes the isolation features controlled for realizing chip circuit.In certain embodiments, electric charge distributes control can be a kind of clock charging mechanism.The timing of clock charging mechanism can be cycle or random (or comprising the random cycle).At some in other embodiment, electric charge distributes control can comprise a self clock circuit, such as, can use asynchronous based on the network postponed.Logical block and other circuit block may be used for various application, comprise the cipher application of the block relating to " encryption " or " password ", such as cryptographic block, authentication engine, hardware arithmetic accelerator, and coprocessor.Except improving the security of circuit operation, the various enforcement of CHARGE DISTRIBUTION as described herein and the enforcement of control can reduce the current component containing security information, reduce or the information that obtains from device current is leaked that hiding circuit operation is relevant, improve wing passage and suppress and reduce power consumption.
Some embodiment also can be used for preventing security information by side Multiple Channel Analysis attack detect.Bypass attack relates to a kind of attack method, and the method obtains sensitive information based on the physical implementation of cryptographic system, instead of obtains sensitive information by the mathematical analysis of cryptographic algorithm or violence.Various types of bypass attack may suppress by the system and method that describes in this, they comprise but are not limited only to, one of at least following analysis, analysis comprises: Differential Power Analysis, simple power analysis, leakage current is analyzed, differential electrical magnetic field analysis, time series analysis, heat, acoustic analysis, direct fault location and differential fault analysis.
Described electric charge distributes some enforcement of control and security logic/circuit block, can prevent this kind of by the bypass attack from other assembly (distributed by electric charge and control) isolation logic/circuit module, and thus suppress acoustics, electromagnetism, heat and/or power consumption analysis, fault is injected, and even physics invades (just some examples).
Embodiments of the invention provide a kind of capacitor charging, for running a logical block.This capacitor charging is based upon one to pass through, and at least one logical transition or switching circulation, run in the mode of enough operation logic block devices in some cases.Charge controlled mechanism can comprise one or more clock and/or self-timing circuit.In a clock is implemented, at least need two clocks, a clock is used for the logic of a certain speed performance element, and another clock is used for being a charge storage device discharge and recharge between logical operation.In non-clock is implemented, a self-timing circuit can be used for the charging and discharging of a control charge storage device.
According to an embodiment, provide a kind of charging mechanism, it has isolated a logical block from power supply, and in a kind of mode that the state of logical block can be made not to be decrypted, what do not show electric leakage is logic power charging.The charging controlling mechanism of logical block inhibits the power signal of logical block to be read out, and this is by comprising in supply voltage and grounding connection from outside, and simultaneously the height of isolation logic unit and low power cable realize.
Cryptographic block in hardware, such as smart card, close range wireless communication (NFC) controller (and other wireless communication controller and processor), field programmable gate array (FPGA), and special IC (ASIC) is usually by be encrypted or the logical block of other cryptographic algorithm is formed.
In the cryptographic block with standard static logical circuit, changing of the logic state in these circuit can be detected by the power supply of powering into cryptographic block (and ground connection) line.In addition, logical block has from the conversion of low paramount logic state the power signal being different from and changing from high to low.Therefore, by monitoring that the operation of cryptographic block can be decoded for the supply lines that cryptographic block is powered.The method can be described as Differential Power Analysis (DPA).Similar, the electromagnetic leakage during logical transition can monitor by the decode operation in cryptographic block.Use this bypass attack, the encryption key in cryptographic block can interiorly be decoded, and this generates an a breach of security of data processing in cryptographic block.
Embodiments of the invention may be provided in relay protective scheme block when avoiding disclosing the conversion of logic state, minimum region funds.In addition, be not only embodiment and isolated the operation of logical block, to such an extent as to during the operation of logical block, prevent perception power consumption from power transmission line, and system and method for the present invention also protects charging and avoids being read from ground wire.Also I/O bus and other signal wire can be protected to avoid the threat of bypass attack detector, and this is by stoping the switching signal decoded on signal wire to realize.
In one embodiment, charge storage device is used for providing a working voltage for a logical block, and is set to the medium in power supply and logical block.In certain embodiments, each logical block block can comprise it self charge storage device, for independently lifting or reduce voltage.In one embodiment, charge storage device is an electric capacity; But embodiment is not limited in this.Therefore, " capacitor " of description can be understood as, and any suitable charge storage device can in capacitor.In addition, be understandable that, a capacitor can realize in every way, includes but not limited to metal-oxide semiconductor (MOS), the metal of metal oxide, metal-insulator-metal type, and the configuration of capacitor on other sheet.In addition, in certain embodiments, although " charge storage device " and " capacitor " is also referred to as each cell block of odd number, electric power also can be supplied to cell block by multiple device or parts in some implementations.
Because at charge storage device, after such as, often cover logical operation on electric capacity, remaining charge packet contains by the complete electrical consumption information of logical block during often overlapping logical operation, the system only disconnected from the logical block (or when using, a charging capacitor) power supply is easily subject to passive attack (such as DPA) by ground wire.Embodiments of the invention, avoid suffering so a kind of pregnable danger from ground portion decoupling logical block and charging capacitor by simultaneously.
According to different embodiment of the present invention, along with each logical transition of logical block (or along with the logical transition of a predetermined number, cycle At All Other Times, or in a kind of random mode), charge storage device by allow it terminal short circuit and carry out being discharged to a certain electromotive force.
In one embodiment, one or more digital logic unit can be provided.Each digital logic unit can comprise a charge storage device, power connector, and a logical block.Each logical block can be arranged for connecting identical power supply.The electric charge of described one or more digital logic unit distributes control, can cross enforcement, to isolate the operation of digital logic unit from power supply.Advantageously, by charge storage device being distributed in an integrated circuit (IC) chip, the electric charge that charge storage device provides is sufficient, and distributes control and electric capacity without the need to customizing electric charge.
A digital logic unit can so be arranged, to such an extent as to its charge storage device can break from power supply and logical block, thinks that charge storage device discharges.Charge storage device can break (such as, power and ground) from two electric wires.Charge storage device can be connected to power supply subsequently, and still breaks from logical block, thinks that charge storage device charges.Then, charge storage device can be opened from power interruption, and is connected to logical block, using the power supply as logical block.Subsequently, the input of logical block can allow to change, and the electric power that conversion needs can be provided by charge storage device.This process can start at any point and/or can continue in one-period.
When charge storage device is opened from power interruption, charge storage device breaks from the grounding connection of power supply.Charge storage device can use any known suitable mode connect with power supply and disconnect, and comprises one or more switch.Further, charge storage device can use any known suitable mode connect with logical block and disconnect, and comprises one or more switch.
In certain embodiments, transistor can be used as switch, to connect charge storage device, and charge storage device be broken from power supply and/or logical block.Any known suitable transistor can be used, such as, a bipolar junction transistor, a mos field effect transistor (MOSFET), or they combination.Namely the MOSFET of each use can be a p-type MOSFET (PMOS), or a N-shaped MOSFET (NMOS).In one embodiment, a transmission gate configuration can be used.In another embodiment, diode can be used as one or more switch.In another embodiment, the switch based on microelectromechanical systems can be used.
In certain embodiments, a mosfet transistor can be used as a charge storage device.In one embodiment, charge storage device is mosfet transistor, and when breaking electric capacity from power supply and logical block, when thinking capacitor discharge, the grid of MOSFET can be connected to the source electrode of MOSFET, and drain electrode and/or base stage, discharge completely to allow electric capacity.The grid of capacity MOS FET can use known any suitable mode to be connected to the source electrode of MOSFET, and drain electrode and (in some cases) base stage, comprise one or more switch, switch can be the transistor described in this.Subsequently, when electric capacity connects power supply, and still keep breaking from logical block, when thinking capacitor charging, the grid of electric capacity can from the source electrode of the MOSFET used as electric capacity, and drain electrode and base stage break.
In another embodiment, charge storage device can be a discrete electric capacity.In another embodiment, charge storage device can be charge-coupled image sensor, or the charge storage device of other active.
Each logical block can be any known suitable logical block, and can comprise one or more input end, one or more output terminal, one or more wire ends, and/or one or more earth terminal.
Logical block can be any known suitable logic gate configuration.Such as, logical block can use a NAND logic gate, an AND logic gate, a NOR logic gate, an OR logic gate, an xor logic door, an XNOR logic gate, a NOT logic gate, an ONE logic gate, a ZERO logic gate, or they combination.This at least one logical block can use any and logical device that is that be, comprises transistor and assembles.Transistor can be field effect transistor, has source electrode, drain electrode, base stage and grid.
In one embodiment, logical block can so configure, to such an extent as to the base stage of each transistor can be coupled to electric capacity, and input is connected to the conversion of at least one logical block, and base stage is coupled to electric capacity (such as floating), and electric capacity can carry out discharging and charging.
In another embodiment, such a transistor does not assemble in common bulk CMOS process, and at least one transistor can be formed in isolation well.Such as, the p trap of N channel device can be isolated from the substrate of a n well layer.
Other circuit block can be configured in digital logic block in a similar fashion.Such as, the anti-cloning function of Physical layer (PFU), randomizer, entropy source, mimic channel (such as, operational amplifier, comparer), look-up table, storer, and signal circuits, can run under described electric charge distributes the control controlling to arrange.Thus, at " logical block " accompanying drawing place, can be understood as, numeral, simulation, and the integrated circuit unit of hybrid circuit may be positioned at logical block.
According to the present invention, Fig. 1 is the schematic diagram of clock charging territory logic (CCDL) unit.With reference to figure 1, in one embodiment, a digital logic unit can comprise: a logical block 10 and a charge storage device (representing with electric capacity 12 in this embodiment), and charge storage device is used for powering for logical block 10, and decoupling logical block 10 from power supply 14 completely.Electric capacity 12 is by using discharge switch 16 decoupling logical block 10 from power supply 14; One switch 18, connects electric capacity 12 to one power supplys and connects (such as, high voltage electric wire); One switch 20, connects electric capacity 12 and connects (such as, low-voltage electric wire or ground connection) to another power supply; And two switches 22,24, connect electric capacity 12 in the power lead of logical block 10 and ground wire.
In order to discharge to electric capacity 12, discharge switch 16 can be closed, and other switch 18,20,22,24 can be opened, to such an extent as to electric capacity 12 breaks from logical block 10 and power supply 14, comprises and breaking from the grounding connection of power supply 14.In order to charge to electric capacity 12, discharge switch 16 can together with switch 22, and 24 open together, and switch 18 and 20 can cut out, to such an extent as to electric capacity 12 is connected to power supply 14, and still breaks from logical block 10.Subsequently, switch 18 and 20 can be opened, and to break electric capacity 12 from power supply 14, and switch 22 and 24 can cut out, to connect electric capacity 12 to logical block 10.Before switch 22 and 26 cuts out, switch 18 and 20 can be opened, and thus ensure that logical block 10 directly connects the power supply connection of power supply 14 or logical block.
Then, the input of logical block 10 can allow to change, and the electric power that conversion needs can be provided by electric capacity 12.This process can start in arbitrfary point, and/or continues in one-period.
Switch 16,18,20,22 and 24 is controllable, such as, is comprised the electric charge distribution controller of signal generator, provide switching signal to switch by one.Control signal can be provided according to various control mode by electric charge distribution controller.
In certain embodiments, a clock scheme can be used.Figure 13 and 14 shows for an example, and clock-signal generator may be used for electric charge and distributes control.One clock plan can comprise three clock signal-mono-gauge tap, 16, gauge tap 18 and 20, and a gauge tap 22 and 24.
In further embodiments, the electric charge dispensing controller comprising a self-timing circuit can be used for gauge tap 16,18,20,22, and 24.Figure 15 shows the example that electric charge distributes control circuit.Self-timing circuit includes, but are not limited to delay element (analog or digital), such as, based on the lag line of inverter, voltage controlled delay line, numerical control delay line, Two-way Cycle delay lock loop, differential amplifier delay cell, analog delay locked loop, their combination and analog.Therefore, although the schematic diagram shown in Fig. 1 is called as the charging territory logical block of " clock ", the electricity arriving and flow through unit can be controlled by non-timely method.
Although charge storage device is described to electric capacity 12, is to be understood that charge storage device can be any suitable charge storage device, comprises initiatively or passive element.
Each switch 16,18,20,22,26 can be any known suitable switch.In certain embodiments, transistor, diode, based on the switch of MEMS, waits and may be used for one or all switches.For use transistor as the embodiment of switch, any known suitable transistor can be used, such as, bipolar junction transistor, MOSFET, or they combination.According to various embodiments of the invention, Fig. 2 A-2C shows the example of discharge switch (16).With reference to figure 2A-2C, discharge switch 16 can be, such as, and a PMOS (Fig. 2 A), NMOS (Fig. 2 B), or the transmission gate (Fig. 2 C) of a use PMOS and nmos pass transistor.
According to an embodiment of the present, Fig. 3 A is the schematic diagram of the CCDL unit during the first stage.With reference to figure 3A, electric capacity C1 (or other charge storage device) can break from power supply V1 and logical block, thinks that electric capacity C1 charges.The two ends of electric capacity C1 can be connected to each other, and discharge to help electric capacity C1.This can by using, and such as, switch, such as transistor has come.Electric capacity C1 can use any known suitable mode to break from power supply V1, comprises one or more switch.Further, electric capacity C1 can use any known suitable mode to break from logical block, comprises one or more switch.
Electric capacity C1 can break a period of time from power supply V1 and logical block, and enough to make electric capacity C1 be discharged to a known or potential charge level, it can be 0 volt (V) or closely 0V.According to certain embodiment, electric capacity is discharged to one lower than the voltage of maximum discharge level, for logical transition, and can be discharged to about 0V.Further, when electric capacity C1 breaks from power supply V1, electric capacity C1 breaks from the grounding connection of power supply V1.
Electric capacity can break to allow the time of capacitor discharge to be from power supply and logical block, such as any following value, any approximately following value, at least any following value, any following value at the most, or using any following value as in any scope of critical point, although embodiment is not limited in this (all values is all in units of nanometer): 0.0001，0。001，0。01，0。1,1,2,3,4,5,6,7,8,9,10,15,20,25,30,40,50,100,150,200,250,300,350,400,410,420,430,440,450,460,470,480,490,500,550,600,650,700,750,800,850,900,950,1000,1500,2000,3000,4000,5000,6000,7000,8000,9000,10 4, 10 5, 10 6, 10 7, 10 8, or 10 9.Such as, electric capacity can break to allow the time of capacitor discharge can be about 3 nanoseconds or about 455 nanoseconds from power supply and logical block.In certain embodiments, the two ends of electric capacity C1 can be connected to each other in this discharge process.
According to embodiments of the invention, Fig. 3 B is the schematic diagram of the CCDL unit during a second-phase.With reference to figure 3B, electric capacity C1 can connect power supply V1, and still keeps breaking from logical block, thinks that electric capacity C1 charges.Electric capacity C1 can use any known suitable mode to connect power supply V1, comprises one or more switch.In one embodiment, electric capacity C1 can be in parallel with connecting power supply V1.Electric capacity C1 can connect the power supply V1 sufficiently long time, thinks that electric capacity C1 charges, and makes it as logical block charging.
Electric capacity can connect power supply, such as any following value, any approximately following value, at least any following value, any following value at the most, or using any following value as in any scope of critical point, although embodiment is not limited in this (all values is all in units of nanometer): 0.0001，0。001，0。01，0。1,1,2,3,4,5,6,7,8,9,10,15,20,25,30,40,50,100,150,200,250,300,350,400,410,420,430,440,450,460,470,480,490,500,550,600,650,700,750,800,850,900,950,1000,1500,2000,3000,4000,5000,6000,7000,8000,9000,10 4, 10 5, 10 6, 10 7, 10 8, or 10 9.
In one embodiment, a MOSFET can be used as electric capacity C1, and when electric capacity C1 breaks from power supply V1 and logical block, when thinking that electric capacity C1 discharges, the grid of electric capacity C1 can be connected to the source electrode of MOSFET, drain electrode and base stage, MOSFET can be used as electric capacity C1, discharges completely to allow electric capacity.The grid of electric capacity C1 can use known any suitable mode to be connected to the source electrode of MOSFET, and drain electrode and base stage, comprise one or more switch, switch can be the transistor described in this.Subsequently, when electric capacity C1 connects power supply V1, and still keep breaking from logical block, when thinking that electric capacity C1 charges, the grid of electric capacity C1 can from the source electrode of the MOSFET used as electric capacity C1, and drain electrode and base stage break.In another embodiment, MOSFET is connected to the grounding connection (such as, the CP_GD of Fig. 4) of logical block as the base stage that electric capacity uses.Subsequently, the grid of MOSFET used as electric capacity C1 is connected to its source electrode and drain electrode, and its base stage still keeps the grounding connection of same logical block to be connected.
According to embodiments of the invention, Fig. 3 C is the schematic diagram of the CCDL unit during a third phase.With reference to figure 3C, electric capacity C1 can break from power supply V1, and connects logical block, to serve as the power supply of logical block.Electric capacity C1 can use any known suitable mode to connect logical block, comprises one or more switch.In one embodiment, electric capacity C1 can be in parallel with logical block.Further, when electric capacity C1 breaks from power supply V1, electric capacity C1 also breaks from the grounding connection of power supply V1.
According to embodiments of the invention, Fig. 3 D is the circuit diagram during one the 4th phase.With reference to figure 3D, the input of logical block can allow to be converted (such as, signal can be provided to input), and needs the electric power carrying out changing can be provided by electric capacity C1.
In certain embodiments, such as, in bulk CMOS application, during logical transition, in logical block, the base stage of each transistor can be connected to electric capacity, thus inhibits electric current (for nmos pass transistor) or the N trap electric current (for PMOS transistor) of the substrate of inflow or outflow from power supply.Otherwise these electric currents may be used for the logical transition in discrimination logic block.In another embodiment, isolated trap, has wherein at least welded a transistor, can be used for the electric current suppressing substrate.
Electric capacity can connect logical block, such as any following value, any approximately following value, at least any following value, any following value at the most, or using any following value as in any scope of critical point, although embodiment is not limited in this (all values is all in units of nanometer): 10 -6, 10 -5, 10 -4, 10 -3, 0.01，0。1,1,2,3,4,5,6,7,8,9,10,15,20,25,30,40,50,100,150,200,250,300,350,400,410,420,430,440,450,460,470,480,490,500,550,600,650,700,750,800,850,900,950,1000,1500,2000,3000,4000,5000,6000,7000,8000,9000,10 4, 10 5, 10 6, 10 7, 10 8, or 10 9.
With reference to figure 3A-3D, the basic operation of the CCDL logical block of embodiments of the invention has been described.In the first phase, time=T1, power supply V1 and logical block can break from electric capacity C1.The two ends of electric capacity C1 can be connected to each other, and electric capacity C1 can discharge.This step, within each cycle that CCDL logical circuit operates, is discharged to a known charge level electric capacity C1.
In subordinate phase, time=T2, logical block keeps breaking from the residual circuit of CCDL.The two ends of electric capacity C1 can disconnect mutually, and in parallel with power supply V1.Electric capacity C1 keeps the parallel connection power supply V1 sufficiently long time, with the electromotive force allowing electric capacity C1 to charge to needs, such as, with the electromotive force that the voltage of power supply V1 is equal or close.
In the phase III, time=T3, electric capacity C1 can break from power supply V1 and be connected to logical block.In this way, electric capacity C1 can be used as the power supply of logical block.
In fourth stage, time=T4, the input of logical block can allow to be converted, and the electric power required for conversion can be provided by electric capacity C1.In logical block, the base stage of each transistor can be connected to electric capacity, thus inhibits electric current (for nmos pass transistor) or the N trap electric current (for PMOS transistor) of the substrate of inflow or outflow from power supply.Otherwise these electric currents may be used for the logical transition in discrimination logic block.Operating cycle can be back to the first stage subsequently, and this process can repeat.This process can start in any stage and/or can continue in one-period.
By within the first stage for electric capacity C1 discharges, because the electric charge remained in after fourth stage in electric capacity C1 is removed by from the electric capacity C1 in period first stage (wherein electric capacity discharges before taking back power supply), the charge level removed from electric capacity C1 during a logical transition is isolated by from power supply, to prevent from being felt.This configuration that embodiments of the invention provide can solve the problem of the different electricity in electric capacity, because can be changed with the generation of logical block internal conversion by the electricity that logical block consumes at every turn in electric capacity C1 during the first stage, and the conversion in logical block changes according to the input in logical block, which results in the electricity removing varying number from electric capacity C1, can provide some information thus, these information may disclose the action type of carrying out in logical block.
In addition, use CCDL method, all can break from logical circuit to the positive pole of power supply and loop, thus contribute to removing any path from the charge or discharge node current of power supply in logical block.The electricity of all logical operation used by logical block all comes from or is attributed to electric capacity.
Can carry out under the control of electric charge dispensing controller at the four-stage shown in Fig. 3 A-3D.Electric charge dispensing controller is transmitted control signal to switch by the mode of timing or non-timing.For any one specific time of four-stage, be all based on any amount of factor.Such as, in some cases, charge storage device can be monitored, and whether electric discharge and charging can be controlled lower than a certain specific voltage threshold level based on the voltage on Electricity storage device.
In addition, in certain embodiments, switch connects and other stage of disconnecting can be implemented, and (or) some stage can repeat.Give one example, electric charge dispensing controller provides signal to carry out gauge tap in some way, in this mode, electric capacity is connected with power supply, and disconnect with power supply when not being connected to logical block, or discharge and recharge repeatedly (such as, duplication stages 1 and 2) when not connecting logical block.As another example, a kind of situation may be there is: control because random electric charge distributes, electric capacity is connected with power supply and logical block simultaneously.
In one embodiment, a non-overlapping clock circuit produces five Non-overlapping clock signal and drives a CCDL logical block repeatedly recharge.Certainly, different embodiments can in conjunction with more or less clock signal.Such as, at least two signals can be used, and a clock runs with the speed of execution logic unit, and another clock is used for connecting and the charging device equipment of disconnection between power supply and logical block.In certain embodiments, clock is not necessary to each independent logical block institute.This can allow basic static logic and CCDL power switch unit core to arrange in pairs or groups to use.
Embodiment can utilize the clock period further, the clock period based on a logical transition, multiple transform, even random clock.
In certain embodiments, comprise charge holding device (the transistor M9 see Fig. 4) for the formation of the circuit of safety and the unit of system, it can be used for keeping electric charge on guide rail, even if the same isolated from power of circuit.Keep the electric charge stored in battery that logical block can be allowed to run, even if do not apply power on guide rail, noise, or variable power.Therefore, when connect the time of isolated location, so that it can be connected to a power supply is not must distribute between control circuit and logical block at electric charge to carry out regulating.Embodiments of the invention can carry out in an AES encryption block.Fig. 4 and Fig. 6 is similar chart, shows the exemplary construction of logical block, and wherein basic static logical block (AND in example) can be matched with a CCDL electrical source exchange unit core.With reference to figure 6, left circle shows the CCDL electrical source exchange core of unit.A single nmos pass transistor (Fig. 4) can be provided by electric capacitor, thinks that it discharges, and thus defines the quantity of capacitor discharge to the threshold voltage (Vth) of nmos device, and nmos device is used for the two ends of short circuit power electric capacity.Additional PMOS device, thus as a transmission gate (Fig. 6), can allow voltage to be applied on electric capacitor, with in each discharge cycle, be discharged to 0V (or closely to 0V) completely.
Fig. 7 is a capacitor discharge figure.With reference to figure 7, which show the improvement of capacitor discharge level.Central area (pointing out as " capacitor discharge ") shows during the discharge portion of the recharging period of CCDL unit, the every side voltage because electric capacity is shorted on electric capacitor.In discharge cycle, every side of electric capacitor reaches identical voltage potential (such as, do not have or almost do not have electricity to remain in electric capacitor).Which ensure that within each cycle of CCDL unit, need identical electricity, think that electric capacitor charges.
Circle zone on the right side of Fig. 6 shows the logical gate of CCDL unit.In the case, logical circuit uses as the AND door of a basic dual input.In CCDL unit, allow for one with the ability of static logic operation logic deposited, lower powered, the use of the logic family that low area consumes.Therefore, a unique logical circuit, for performing the basic logic functions that AES core needs, optional.
In one embodiment, can protection ring be used, be centered around around an AES core, to provide the junction isolation of some levels, to reduce the ability that substrate current arrives at power supply further.In one further embodiment, in non-bulk process, N trap bathtub (one in the intrabasement relatively dark N-shaped active region of p-type) under the part of CCDL unit can provide further from the isolation of the power supply of logical operation, and logical operation produces from the substrate current of CCDL unit.
In one embodiment, at CCDL circuit interface, a Schmitt trigger with inner hysteresis can be used with standard CMOS static logic block (such as, those static logic blocks used in a testing integrated circuits).The triggering one that the anti-interference that hysteresis produces can suppress CCDL output signal to avoid mistake has the CMOS logical block of interface standard.
The number appearing at the digital logic unit in one piece of digital logic unit can be, such as any following value, any approximately following value, at least any following value, any following value at the most, or using any following value as in any scope of critical point, although embodiment is not limited in this: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000, 1500, 2000, 3000, 4000, 5000, 6000, 7000, 8000, 9000, or 10000.Such as, 20 digital logic units described in this can be comprised in one piece of digital logic unit.
Clock frequency in digital logic unit can be, such as any following value, any approximately following value, at least any following value, any following value at the most, or using any following value as in any scope of critical point, although embodiment is not limited in this (all numerical value all represents with megahertz): 10 -6, 10 -5, 10 -4, 10 -3, 0.01，0。1,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,25,30,35,40,45,50,55,60,65,70,75,80,85,90,95,100,150,200,250,300,350,400,450,500,550,600,650,700,750,800,850,900,950,1000,1500,2000,3000,4000,5000,6000,7000,8000,9000, or 10000.Such as, the clock frequency of a digital logic unit can be 10MHz or about 10MHz.
In certain embodiments, charge storage device upgrades within each clock period (such as, charging) once, and recharging period is from the negative edge of system clock.Therefore, when the clock period of digital logic unit is 10MHz, the logical transition in all AES unit all completes being less than in 50ns.Suppose that the trigger of clock edge uses in AES encryption core, with this understanding, the logical transition of each transmission in an AES encryption block must complete in 25ns.In other embodiments, charge storage device upgrades after the clock period of predetermined number, can carry out multiple logical transition in the single charging of charge storage device one.In one suchembodiment, that the numeral of clock period can be random or change by a kind of style.Such as, the numeral of the clock period between charge period controls (therefore charging with the generation of random interval) by a random number generator.
In one embodiment of the invention, a kind of method of digital logic unit can comprise the formation of a charge storage device, the connection of a power supply, and the logical block described in this.The method can be included in upper formation one switch of an electric wire (or metal interconnected) further, for being connected to each other charge storage device two ends, be also included within the switch between the terminal of charge storage device and power supply, and the switch between the terminal of charge storage device and logical circuit.Each switch can be, such as a MOSFET.In one particular embodiment, by forming a mos capacitance (or connecting in some way to provide electric capacity), a MOSFET can be used as charge storage device, and can by the source electrode of the grid to MOSFET that connect MOSFET at the upper switch connecting capacitative end of electric wire (or metal interconnected), the electric wire of drain electrode and (optionally) base stage provides.The method also can comprise formation one power supply, connects to connect power supply.Multiple such digital logic unit can be formed.In one embodiment, a single power supply can be formed, to connect all logical blocks.In another embodiment, one or more logical block can share identical power supply (such as, all logical blocks can share identical power supply).
According to embodiments of the invention, a series of configurable digital logic unit, so that during each logical transition of unit, each unit is powered by an electric capacity (or other charge storage device).With each logical transition (or time of the logical transition of a predetermined number or the logical transition of random number or a random quantity), the two ends of electric capacity are connected to each other, and electric capacity is opened from logical block and any power interruption, thus allow for capacitor discharge to known level (such as, 0V or closely 0V).Electric capacity can be connected to a power supply subsequently, with again for capacitor charging.During all logical transition of logical block, this process opens each logical block from power interruption, thus provide for logical block at voltage and avoid power consumption during electric power and be felt, and inhibit the bypass attack in logical block greatly, such as DPA.
According to embodiments of the invention, logical block by completely from decoupling zero power supply, and is only connected to a charge storage device.After logical transition in logical block is carried out, the electric discharge of charge storage device is a kind of preferred mode covering up electric quantity consumption within each CCDL logical operation cycle.During logical transition, in logical block, the base stage of each transistor can connect charge storage device, thus inhibits electric current (for nmos pass transistor) or the N trap electric current (for PMOS transistor) of the substrate of inflow or outflow from power supply.Otherwise these electric currents may be used for the logical transition in discrimination logic block.
Prevent from except protecting safe information being read (in the operating process of whether leaking at cut-off current) from electric current; described CHARGE DISTRIBUTION controls and the setting of circuit may be used for protection information safety; prevent from coming from acoustics; electromagnetism; heat, and/or the information of power consumption is detected.In fact, embodiment can prevent any amount of bypass attack.
Following embodiment is for enumerating some configurations that can use in the present invention.The citing of the following example may not be interpreted as limit, and some Typical Disposition of instruction manual hardly.Other configuration also can be included in scope and spirit of the present invention.
In a first embodiment, provide a secure digital logical block, comprise a logical block; And a charge storage device, for during logical operation, for logical block provides electric power, charge storage device is controllable is connected to a power supply during a charging operations, and logical block is connected during a logical operation, wherein during logical operation, charge storage device does not connect the grounding connection of power supply and power supply.Charge storage device can be a discrete electric capacity, a mos capacitance, a MOS transistor, a charge-coupled image sensor, etc.Similar configuration can be used for simulation, other circuit of digital or analog-and digital-elements combination and system.
In a second embodiment, the secure digital logical block of the first embodiment comprises one first switch further, for being charge storage device electric discharge.First switch can be, such as a transistor or a transmission gate.
In the third embodiment, the charge storage device of the first or second embodiment between each logical operation of logical block, or during the logical operation of the predetermined number of logical block, is periodically discharged completely.
In the fourth embodiment, in the first to the 3rd embodiment, the secure digital logical block of any one comprises a second switch further, is connected with the power supply of power supply for connecting or disconnecting charge storage device; One the 3rd switch, for connecting or disconnect the grounding connection of charge storage device and power supply; One the 4th switch, is connected with the power supply of logical block for connecting or disconnecting charge storage device; And one the 5th switch, for connecting or disconnect the grounding connection of charge storage device and logical block.The first, second, the three, four and five switch is each comprises a transistor for this.
In the 5th embodiment, in first to fourth embodiment, the secure digital logical block of any one comprises extra disconnector further, between supply line and power supply, and earth conductor cable, connect secure digital logical block.Disconnector can be at least the tandem tap of 1/6th, connects power supply and connects and second switch, and be at least the tandem tap of 1/7th, connect grounding connection and the 3rd switch.
In the sixth embodiment, in first to the 5th embodiment, the logical block of any one can comprise multiple transistor, each have a base stage, and the described base stage of each transistor wherein in each logical block power supply that at least connects logical block connects and one of them in the grounding connection of logical block.
In the 7th embodiment, provide a kind of method being a logical block of a digital logic unit and powering, wherein digital logic unit comprises logical block, and a charge storage device, and the method comprises the steps:
A () breaks charge storage device from the grounding connection of logical block and power supply and power supply;
B () connects charge storage device and power supply;
C () opens charge storage device from power interruption, comprise and break charge storage device from the grounding connection of power supply; And
D () connects charge storage device and logical block, for providing power supply for logical block.Charge storage device can be a discrete electric capacity, a mos capacitance, a MOS transistor, a charge-coupled image sensor, etc.
In the 8th embodiment, the method for the 7th embodiment can comprise a step (e) further, and to allow when charge storage device connects logical block, the input of logical block can be changed.
In the 9th embodiment, the logical block used in the 8th embodiment comprises multiple transistor, and each have a base stage, and wherein in step (e) period, the base stage of each transistor in logical block connects charge storage device.
In the tenth embodiment, the logical block used in the 8th embodiment is manufacture like this, so that at least one transistor is arranged in an isolation well.Such as, can use a PN junction, to isolate a trap from substrate, so that a n trap is isolated from substrate by a p shape layer, and/or a p trap is isolated from substrate by a n shape layer.
In the 11 embodiment, in the 7th to the tenth embodiment, the method for any one comprises a step (f) further, for breaking charge storage device from logical block after allowing the input of logical block conversion.Before disconnection, charge storage device can connect the conversion that logical block carries out predetermined number.
In the 12 embodiment, in the 7th to the 11 embodiment, the method for any one can comprise further and repeats all steps (such as step (a) to (f)), as long as logical block is powered.
In the 13 embodiment, in the 7th to the 12 embodiment in any one method, step (a) can comprise disconnection charge storage device, and charge storage device breaks from the grounding connection of logical block and power supply and power supply.
In the 14 embodiment, in the 7th to the 13 embodiment in any one method, step (b), for after charge storage device is discharged, is charge storage device charging; And after charge storage device is by power source charges, step (c) has been performed.
In the 15 embodiment, in 7th to the 14 embodiment in any one method, charge storage device can comprise at least two end points, and wherein the electric discharge of charge storage device comprises two end points being connected to each other charge storage device, and charge storage device still keeps the disconnection from logical block and power supply.Two end points of charge storage device can be connected to each other, and charge storage device still keeps the one sufficiently long period of disconnection from logical block and power supply, with substantially, complete or effectively to discharge for charge storage device.
In the 16 embodiment, in 12 to the 15 embodiment in any one method, be connected to each other charge storage device two end points and comprise closed one first switch, first switch connects two end points of charge storage device, and wherein disconnects mutually charge storage device two end points and comprise and open one first switch.First switch can be a transistor, transmission gate, etc.
In the 17 embodiment, in 7th to the 16 embodiment in any one method, connect charge storage device to power supply and comprise a closed second switch and one the 3rd switch, second is connected charge storage device and power supply with the 3rd switch, it breaks charge storage device and power supply and comprises and open a second switch and one the 3rd switch, and wherein connection charge storage device and logical block comprise closed 1 the 4th switch and one the 5th switch, and the 4th is connected charge storage device and logical block with the 5th switch.Second, three, the 4th and the 5th switch is each comprises a transistor, diode, mems switch device, etc.
In the 18 embodiment, in 8th to the 17 embodiment in any one method, step (e) can comprise further isolates digital logic unit from the power supply of power supply connects, and this is that 1/6 tandem tap connected between second switch by opening all power supplys at power supply reaches; And digital logic unit is isolated from the grounding connection of power supply, this is reached by 1/7 tandem tap opened between all grounding connections at power supply and the 3rd switch.
In the 19 embodiment, electric charge distributes control and goes for any one in the first to the 18 embodiment, for the CHARGE DISTRIBUTION of control module.Electric charge distribute control to relate to timing and/or non-clocking method and synchronous or asynchronous method.As limiting examples, electric charge distributes the synchronous electric charge distribution clock generator controlling to comprise and use system clock generation control signal, an incoherent CHARGE DISTRIBUTION clock generator, CHARGE DISTRIBUTION clock generator use on a chip and/or independently oscillator to produce control signal, a determinacy CHARGE DISTRIBUTION clock generator being provided with feedback circuit, and an asynchronous CHARGE DISTRIBUTION clock generator, this generator is incorporated to a randomizer, to produce control signal oscillator or system clock.
Embodiments of the invention can be used for safety applications.
In certain embodiments of the present invention, can on a smart card or similar devices or within, the one or more circuit described in this are provided.A smart card like this or similar devices can be used for, such as atm card, I.D., stored value card, credit card, mobile phone, and computer access controls, pay TV, and/or medical information stores.
For a better understanding of the present invention and its many advantage that may have, following example is enumerated.Following example, for illustration of certain methods of the present invention, is applied, embodiment and change thereof.Thus they be not considered to any restriction of the present invention.For the present invention, the change that can carry out and revise too numerous to enumerate.
example 1
According to embodiments of the invention, Fig. 4 is the schematic diagram of the enforcement of CCDL circuit.With reference to figure 4, employ MOSFETM1, M2, M11, M12 and M13 are using as the switch as shown in Fig. 1 and Fig. 3 A-3D.MOSFETM5 is used for as electric capacity C1.MOSFETM3, M4, M6, M7, M8 and M10 are as a static logic " AND door ".
Within the first stage, MOSFETM1, M2, M11 and M12 (can not be closed) decoupling logical block and power supply from electric capacity M5.And then, M13 can (be opened) connect M5 grid to the source electrode of M5 and drain electrode, thus allow M5 electric discharge.
In subordinate phase, M2, M11 and M13 can not from logical block decoupling M5.MOSFETM11 with M12 can be connected M5 subsequently to power lead VDD and VSS, thus allows M5 charging.
Within the phase III, MOSFETM1, M2 and M13 can not break M5 from power lead VDD and VSS.And then, MOSFETM2 and M11 is activated, and thus connects M5 to logical block.
In fourth stage, if passable, input A and B is allowed to conversion, and allows the electricity required for the conversion of the logic state in logical block to come from M5.It should be noted that the base stage of the fast interior each PMOS device of logic connects back panel wiring end (CP_RL), and the base stage of the fast interior each PMOS device of logic connects inner ground end (CP_GD).Every root supply lines, such as CP_RL and CP_GD, is positioned at each CCDL logical block, and can be connected to the corresponding supply lines in another CCDL logical block in a larger CCDL block.Therefore, within a CCDL operating cycle, the device in logical block is connected alternately unsettled with their base stage, such as, in the first and second stages, and connects supply electric capacity M5 subsequently, such as, in the third and fourth stage.During logical transition, the isolation of base stage removes the important path that electric current inflow is the power supply that a CCDL unit is powered, and produces when wherein electric current changes in logic is fast.
That also do not describe in figure is MOSFETM9.An assembly, such as M9 can occur in certain embodiments.Here, M9, for storing some electricity, with when logical block breaks from charge storage device, helps to maintain CP_RL and CP_GD voltage potential poor.
example 2
Fig. 5 shows the clock sequence of a CCDL logical block.Signal SL_CLK represents the output to a CCDL unit, and output can cause logical transition.The conversion of signal CLK1 and CLK1B opens logical block from supply electric capacity and power interruption.Determine that a CCDL unit or limiting factor based on the maximum operational speed of the circuit block of CCDL are that the necessity of all logical transition in CCDL block determines, wherein logical transition completed before CLK1 and CLK1B signal disconnects with the logical block in CCDL unit from the supply electric capacity of powering for logical block.
Once CLK1 and CLK1B signal decoupling logical block from supply electric capacity, CLK3 is convertible does not supply capacitor discharge.Finally, CLK2 and CLK2B signal is changed, to allow supply electric capacity by power source charges.It should be noted that the transform strike slip boundary of each CLK signal is not overlapping.This non-overlapped clock inhibits, the power lead of such as coupled logic block at any time or when the end points of power supply lid is shorted, the power supply lid of connecting power line.
example 3
In Fig. 6, have detected a CCDL unit.In this example, the discharge switch of unit make use of the transmission gate of nmos pass transistor M13 and PMOS transistor M14.In a larger circuit, the detection of CCDL unit demonstrates the small but excellent electric current causing level, such as a tens of ampere, during the switching of CCDL logic, flows into power supply by the substrate of circuit.Although very little, the information of some levels may extract from these electric currents about the logical operation of CCDL circuit.There are two kinds of methods can reduce this impact.First, the base stage connection of each device in CCDL logical block (right side circle) is bound on the internal power cord of CCDL unit, such as CP_RL and CP_GND.This attempts to make the electric current of the substrate produced during logical operation as much as possible flow into and/or flow out electric capacitor.
The second shows with the method for electric current on ground wire in fig. 8 for reducing on power supply.According to embodiments of the invention, circuit diagram during Fig. 8, show a series of switches during logic switch, switch is used for from providing VDD and the VSS electric wire of isolating CCDL unit the external power source of electric power for CCDL circuit, thus inhibits the substrate power supply from flowing between the two.Although Fig. 8 plants two electric capacity (switch) of display for every wire, embodiment is not limited in this, and can comprise more or less switch.
example 4
Create the dibit cryptographic block with CCDL unit, to detect the function of the CCDL unit in a larger circuit.Composition graphs 9A-9D, it is the schematic diagram of the CCDL embodiment of a dibit cryptographic block.Figure 10 is some signals of the operation about cryptographic block.
Two signals of Figure 10 middle and upper part are that the electric current reaching the power supply of powering for dibit cryptographic block exports and ground return current.Two signals of Figure 10 middle and lower part are two output bits of cryptographic block.With reference to Figure 10, an a large amount of ripple is had to rest on the top of digital output signal.Although ripple is comparatively large, suppose that CCDL unit has a low noise tolerance limit, this is that two output signals owing to relating to earthing power supply cause.Because the logical block recharged in period each CCDL unit run at CCDL is unsettled, the logical block in unit no longer relates to power supply.
Figure 11 shows the identical dibit output signal relating to internal logic electric wire in CCDL unit.With reference to Figure 11, when watching in this way, noise margin is significantly increased.Because the internal power cord of each CCDL is connected in cryptographic block together, the clearer noise margin illustrating a CCDL signal in CCDL circuit of the signal in Figure 11.
According to one embodiment of present invention, Figure 12 is the power supply signal figure of an AES encryption core, and AES encryption core is made up of CCDL unit.
example 5
Electric charge distribute control by any amount of controller, comprise numeral, simulation and mixed signal based on controller implemented.Some controllers may based on clock, and some comprise self-timing circuit, and other controller can comprise based on safety circuit or the logic state of system or the feedback mechanism of specific operation.Figure 13-16 shows some nonrestrictive examples.
Figure 13 shows the synchronous electric charge distribution clock generator illustration that may be used for electric charge and distribute control.With reference to Figure 13, a clock distribution network 1300 can receive a system clock 1301, and by a delay block 1311,1312,1313 and single (pulse width) generator 1321,1322,1323 distribution clocks, to export three control signals (with once pass through phase inverter 1331,1332, corresponding inverse signal when 1333).By single generator 1321,1322,1323 cause delay block 1311,1312, and 1313 and the delay of each parallel control signal line that causes of corresponding pulse width adjust, select by designing.
Figure 14 shows the figure that may be used for the incoherent CHARGE DISTRIBUTION clock generator that CHARGE DISTRIBUTION controls.With reference to Figure 14, propose a similar designs with synchronous electric charge distribution clock generator, but, what replace use system clock 1301 is, one independently oscillator and timing generator 1401 provide a signal, signal is dispensed to Postponement module 1411 thereupon, and 1412,1413, and control signal (such as CLK1 is provided, CLK2, CLK3) single (pulse width) generator 1421,1422,1423, and once by corresponding designature time phase inverter (1431,1432,1433).
Figure 15 shows the figure that may be used for the deterministic CHARGE DISTRIBUTION clock generator that CHARGE DISTRIBUTION controls.Powered by a CCDL CHARGE DISTRIBUTION network 1510 see Figure 15, CCDL logical block, the clock distribution network 1520 namely by being controlled by controll block 1530 operates.Controll block 1530 can be considered when controlling clock distribution network 1520 and CHARGE DISTRIBUTION network 1510 switch, through the voltage of insulating power supply line.Such as, a differential amplifier 1540 can be configured to a buffer zone, measures the voltage through the power lead of powering to logical block 1500.The output of differential amplifier 1540 can as the noninverting input being input to comparer 1550, the voltage that comparer compares power lead and the reference voltage 1555 of inverting input being connected to comparer 1550.Some or all power rails can connect by this way.Comparer 1550 can be a hysteresis amplifier.
Figure 16 shows the figure that may be used for electric charge and distribute the asynchronous CHARGE DISTRIBUTION clock generator of control.With reference to Figure 16, oscillator or system clock 1610 and a randomizer 1620 can be imported into totalizer 1630, and it is used to control clock distribution network 1640.Clock distribution network 1640 can provide signal, to control the CHARGE DISTRIBUTION network of charge storage device, for each block (logical OR simulation) of system.
Any " embodiment " relating to this instructions, " citing embodiment " etc. all mean the special feature that same embodiment is relevant, and structure or attribute, this embodiment at least comprises in one embodiment of the invention.The appearance in these stages of the diverse location in this instructions, for all identical embodiments not necessarily.In addition, any element of any the present invention or embodiment wherein or restriction can combine with any element of other invention any or embodiment wherein or restriction (independently or by any way combining), and all these combine all unrestricted containing within the scope of the invention.
Should be appreciated that the example that describes in this and embodiment just for illustration of, and for those skilled in the art, different amendments and change all should be included in the application spirit and scope within.

Claims (11)

1. an electric charge distributes control system, comprising:
Multiple charge storage device, each charging and storing device provides power supply to circuit component during the operation of circuit component; And
An electric charge dispensing controller, wherein said electric charge dispensing controller connects each charge storage device and power supply between charge period, and connect each charge distributor part and circuit component at circuit component run duration, wherein in the operational process of circuit component, charge storage devices does not connect the grounding connection of power supply and power supply.
2. electric charge according to claim 1 distributes control system, and it is characterized in that, described circuit component comprises an analog module.
3. electric charge according to claim 1 distributes control system, and it is characterized in that, described circuit component comprises a digital logic block.
4. distribute control system according to the arbitrary described electric charge of claim 1-3, it is characterized in that, the connection of described CHARGE DISTRIBUTION controller further deenergization and circuit component and charge storage device in discharge process.
5. distribute control system according to the arbitrary described electric charge of claim 1-4, it is characterized in that, described electric charge dispensing controller comprises a clock generator, and clock generator controls the connection of described charge storage device.
6. electric charge according to claim 5 distributes control system, it is characterized in that, described clock generator produces one first clock, for the first switch, think that charge storage device discharges, a second clock, for second switch, be connected with the power supply of disconnection charge storage device to power supply to connect, and one the 3rd switch, for connecting and disconnecting the grounding connection of described charge storage device to power supply; And one the 3rd clock, for the 4th switch, be used for connecting and disconnect the power supply of charge storage device to circuit component and be connected, and one the 5th switch, for connecting and disconnecting the grounding connection of charge storage device to circuit component.
7. distribute control system according to the electric charge before described in any claim, it is characterized in that, described clock generator comprises a synchronous electric charge distribution clock generator, an incoherent CHARGE DISTRIBUTION clock generator, a CHARGE DISTRIBUTION clock generator determined, or an asynchronous CHARGE DISTRIBUTION clock generator.
8. distribute control system according to the arbitrary described electric charge of claim 1-4, it is characterized in that, described electric charge dispensing controller comprises a delay circuit, for controlling the connection of described charge storage device.
9. an encryption system, comprising:
One charge storage distribution network, for the cryptographic block providing electric power to arrive isolation, described charge storage distribution network comprises multiple charge storage device;
A clock distribution network, provides control signal, to connect with deenergization to CHARGE DISTRIBUTION network, and connects and disconnects the cryptographic block supply lines of CHARGE DISTRIBUTION network to isolation.
10. encryption system according to claim 9, also comprises:
A comparer, for comparing the voltage of at least one in the power lead of isolation and reference power source, and exports a signal, for adjusting the control signal of clock distribution network.
11. 1 kinds of methods, for preventing at least one bypass attack, bypass attack is from following group, and group comprises Differential Power Analysis, simple power analysis, leakage current analysis, difference electromagnetic field analysis, time series analysis, heat, acoustic analysis, direct fault location and differential fault analysis, the method comprises:
Run arbitrary described system in claim 1-10.
CN201480029850.2A 2013-05-31 2014-02-20 Charge distribution control for secure systems Pending CN105431861A (en)

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US13/906,542 US8912814B2 (en) 2012-11-12 2013-05-31 Clocked charge domain logic
US14/184,088 US8912816B2 (en) 2012-11-12 2014-02-19 Charge distribution control for secure systems
US14/184,088 2014-02-19
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WO2014193496A1 (en) 2014-12-04
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