CN105426119A - Storage apparatus and data processing method - Google Patents
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- CN105426119A CN105426119A CN201510716920.8A CN201510716920A CN105426119A CN 105426119 A CN105426119 A CN 105426119A CN 201510716920 A CN201510716920 A CN 201510716920A CN 105426119 A CN105426119 A CN 105426119A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0689—Disk arrays, e.g. RAID, JBOD
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Abstract
The present invention relates to the technical field of data storage, and particularly relates to a storage apparatus and a data processing method. A comparing and matching module is added in a storage apparatus, so that tasks such as retrieval, identifying and comparing or matching and the like of data in the storage apparatus are accelerated, the work load of a central processing unit is reduced, and the performance of the storage apparatus on data processing is improved.
Description
Technical field
The present invention relates to technical field of data storage, particularly relate to a kind of memory device and data processing method.
Background technology
The data message epoch, internet has become an indispensable part in people's daily life, internet, applications is of a great variety, comprises social relation network that Facebook, MySpace, QQ are representative, video sharing application that Youtube is representative and the search engine application etc. that is representative with Google, Yahoo, Baidu.Ever-increasing Internet user brings the data (video, picture, blog etc.) of explosive growth.The technology path processing these data inherently can be divided into two aspects: the storage management technique of mass data and the treatment technology (log analysis, search engine application etc.) for mass data.
The huge data volume in internet makes us expect the thought of parallel computation to be applied on business cluster, and cloud computing thought is arisen at the historic moment.Google is the leading strength of cloud computing, and it uses process every day of Hadoop framework more than the data volume of 20PB.In order to a large amount of raw data can be processed, Google devises a new abstract model-mapping reduction (MapReduce), mapping reduction name derives from two core operations in this model: map (Map) and reduction (Reduce), realization flow figure as shown in Figure 1.First user program data to be dealt with 31 are by importing in storage networking and being divided into some fragments (split) (here for 6 fragments, be respectively fragment 321, fragment 322, fragment 323, fragment 324, fragment 325, fragment 326), then in all machines (machine), one is selected as main frame 30 (master), i.e. master control program, other as by host assignment task from machine (workers) i.e. working routine.Main frame is idle distribute a mapping tasks from machine, as mapping tasks 331, the raw data of burst is carried out mapping process, extract key (key)/value (value) right, intermediate data 341 is kept at from this locality of machine stores, and by from machine, the positional information of intermediate data is passed to main frame 30, main frame 30 again the data message of transmission is distributed to responsible reduction task from machine, then from the long-range reading intermediate data 341 of machine, intermediate data 342 and intermediate data 343, and these key/value are sorted, what be assigned with reduction task travels through the intermediate data after sequence from machine, and value corresponding for same key is passed to user-defined reduction function 351 (or reduction function 352), carry out reduction process, finally this block is appended in last output file 36.The core concept mapping reduction programming model utilizes easy software frame exactly, the application program write out based on it can operate on the large-scale cluster that is made up of thousands of business machines, and with a kind of mass data of reliably fault-tolerant mode parallel processing TB rank.
Traditional at memory device, as shown in Figure 2 be the cut-away view of solid state hard disc, host microcontroller 1 generally by cache chip 2 to accelerate the digital independent of flash chip 3 array, raising performance.When system CPU needs 4 importing data from solid state hard disc, host microcontroller 1 receives order and the data of specifying is read out from flash chip array 3, and being transferred to superior system by external interface 5, host microcontroller 1 does not do any process to data.The inner structure of such as disk as shown in Figure 3 again, its structure is similar to solid state hard disc, comprises disk 6, prime amplifier 7, read-write channel 8, disk host microcontroller 9, code area and data buffer 10, servo antrol and detuner 11, motor controller 12, motor 13 and external interface 14.Disk array, i.e. " array with redundant ability that independent disk is formed ".Disk array is by the more cheap disk of a lot of price, is combined into the disk group that a capacity is huge, and disk array has multiple port can be connected by different system or different port, and the different port of a system connection array can promote transmission speed.
Redundant Array of Independent Disks (RAID) inner structure sketch as shown in Figure 4, adopts the RAID controller 15 that the host microcontroller in Performance Ratio disk and solid state hard disc is strong, such as, adopts Intel processor; Also comprise multiple disk 16 and system interface 17 in addition.Network attached storage (NetworkAttachedStorage, NAS) is the device possessing data storage function, therefore also referred to as " network memory ".It is a kind of exclusive data storage server, and therefore network attached storage internal processor is other processor of server level that performance is higher.So, when terminal system CPU does the data processing operation of some lightweights, host microcontroller in these memory devices is not all in idle condition when doing data processing, no matter therefore for the host microcontroller in superior system CPU or memory device, it performance and power consumption is all a kind of waste.
As can be seen from simple introduction above, task handled by the above-mentioned large-scale cluster be made up of thousands of business machines is all to run process by the CPU of business machine, and these tasks be all some lightweights without the need to arithmetic logical unit (ArithmeticandLogicUnit, be called for short ALU) a large amount of work (such as mapping tasks and reduction task) participated in, first be waste in power consumption, secondly be also waste (high performance ALU does not participate in a large amount of calculating) in performance, therefore the power consumption of whole cluster and cost are all very high.
Traditional, carry out in the method for data processing in memory device, all data processing operations have all been come by the host microcontroller in memory device, and load is large, and storage device performance can be affected.If adopted, programmable logic array (FieldProgrammableGateArray, be called for short FPGA) realizes data search, identification, relatively or the operation such as coupling, efficiency is low, performance is a kind of waste; If adopt special IC (ApplicationSpecificIntegratedCircuit is called for short ASIC) to realize, cost is also relatively high.
Summary of the invention
For the problems referred to above, the present invention proposes a kind of memory device, be applied to and comprise in the computer architecture of superior system, described storage organization comprises:
Storage array, prestores pending data;
Host microcontroller, is connected with described superior system and described storage array respectively, for the data processing command that the described superior system of reception issues; And
Comparison match module, is connected with described host microcontroller and described storage array;
Wherein, described comparison match module processes the described pending data stored in described storage array according to described data processing command, and by described host microcontroller, result is fed back to described superior system.
Above-mentioned memory device, wherein, described comparison match module is hardware module.
Above-mentioned memory device, wherein, described comparison match module integration is in described host microcontroller.
Above-mentioned memory device, wherein, described comparison match module is Content Addressable Memory or Ternary Content Addressable Memory.
Above-mentioned memory device, wherein, described data processing command is data search order, data identification order, data comparison command or Data Matching order.
Above-mentioned memory device, wherein, described memory device comprises disk, solid state hard disc, network attached storage or Redundant Array of Independent Disks (RAID).
Above-mentioned memory device, wherein, described host microcontroller is connected by external interface with described superior system, so that described result is sent to described superior system.
A kind of data processing method, be applied in above-mentioned memory device, described method comprises:
S1: described superior system sends data processing command to described memory device;
S2: the described host microcontroller in described memory device receives described data processing command, and judge whether to need to carry out process operation to the data in described storage array according to described data processing command;
If the determination result is YES, S3 is performed;
Otherwise, perform S5;
S3: described data processing command is sent to described comparison match module by described host microcontroller;
S4: described comparison match module receives and according to described data processing command, processes the data in described storage array, and result is back to described superior system by described host microcontroller;
Other data processed result are back to described superior system by S5: described host microcontroller carries out other data processing tasks in this locality simultaneously.
Above-mentioned data processing method, wherein, described data processing command is data search order, data identification order, data comparison command or Data Matching order.
Above-mentioned data processing method, wherein, described result is connected with described superior system by external interface by described host microcontroller.
Above-mentioned data processing method, wherein, described comparison match module is Content Addressable Memory or Ternary Content Addressable Memory.
In sum, the present invention proposes a kind of memory device and data processing method, comparison match module is with the addition of in memory device, software simulating can be used, also hardware implementing can be used, thus expedited data carries out in memory device inside searching, identifies, relatively or the task such as coupling, alleviate the operating load of central processing unit, improve the performance that memory device carries out data processing.
Accompanying drawing explanation
Fig. 1 is that the information of prior art information processing of the present invention moves towards figure;
Fig. 2 is the inner structure schematic diagram of prior art solid state hard disc of the present invention;
Fig. 3 is the inner structure schematic diagram of prior art disk of the present invention;
Fig. 4 is prior art Redundant Array of Independent Disks (RAID) inner structure simplified schematic diagram of the present invention;
Fig. 5 is the inner structure schematic diagram of a kind of memory device of the embodiment of the present invention;
Fig. 6 is the structural representation of embodiment of the present invention comparison match module hardware;
Fig. 7 is the schematic flow sheet of a kind of data processing method of the embodiment of the present invention;
Fig. 8 is the schematic diagram of embodiment of the present invention digital independent;
Fig. 9 is the schematic diagram of embodiment of the present invention comparison match module information process.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further described.
Embodiment one
(memory device 18 can be disk, solid state hard disc, network attached storage or Redundant Array of Independent Disks (RAID) to a kind of memory device 18 as shown in Figure 5, also can be can be used in other memory devices of the present invention, at this not as restriction) in, host microcontroller 20 is connected with superior system and storage array 21 respectively, for receiving the data processing command that superior system issues, can also manage storage unit and control, such as wear leveling, model choice, bug check error correction, reading and writing data etc. simultaneously; Comparison match module 19 is connected with host microcontroller 20 and storage array 21, with according to data processing command (data processing command can be data search order, data identification order, data comparison command, Data Matching order or other data processing commands) the pending data stored in storage array 21 are processed, and by host microcontroller 20, result is fed back to superior system; Host microcontroller 20 is connected by external interface 22 with superior system, so that result is sent to superior system.Comparison match module 19 is generally hardware, can be integrated in host microcontroller 20, although may raise the cost, can save space and improve integrated level.Comparison match module 19 is Content Addressable Memory or Ternary Content Addressable Memory, also can be the addressable memory that can be applied to this.Structural representation as shown in Figure 6, comparison match module 19 comprises storage unit 23, Data Matching register 24, code translator 25, matched line 26, reads induction amplifier 27, matched data 28, it can complete the exact-match lookup of matched data 28 within a hardware clock cycle, far away faster than the speed of software simulating.The access mode of addressable memory (or triple addressable memory) is the content of Input matching data, list items all in this matched data 28 and addressable memory (or triple addressable memory) can be carried out matching ratio comparatively simultaneously, finally return to coupling list item address corresponding in addressable memory (or triple addressable memory) wherein.
Embodiment two
As shown in Figure 7, the invention provides a kind of data processing method, be applied to the memory device 18 shown in Fig. 4, the method comprises:
S1: superior system sends data processing command (this data processing command can be data search order, data identification order, data comparison command, Data Matching order or other related commands) to memory device 18 by external interface 22;
S2: the host microcontroller 20 in memory device 18 receives data processing command, and judge whether to need to carry out process operation to the data in storage array 21 according to data processing command; If the determination result is YES, S3 is performed; If judged result is no, perform S5;
S3: data processing command is sent to comparison match module 19 (comparison match module 19 can be Content Addressable Memory or Ternary Content Addressable Memory) by host microcontroller 20;
S4: comparison match module 19 receives and according to data processing command, processes the data in storage array 21, and result is back to host microcontroller 20;
S5: host microcontroller 20 continues to carry out other data processing tasks in this locality, data result is back to superior system by external interface 22 simultaneously.
Embodiment three
Google file system (googleFileSystem Google file system is called for short GFS), a kind of proprietary distributed file system, is developed by Google company, runs in Linux platform.It provides mass memory for Google cloud computing, and very tight with the combine with technique such as Chubby, MapReduce and Bigtable, is in the bottom of all core technologies.GFS comprises a master node (master server), multiple chunkserver (data server) and multiple client (running the client of various application).Fig. 8 is the architectural schematic of GFS, and each node is all common Linux server, and the work of GFS is exactly coordinate hundreds of server for various application to provide service.Chunkserver provides storage.Divide File can be fixed length block by GFS, each data block has a unique immutable ID of the overall situation (data block handle: chunk_handle), data block is stored on chunkserver with the form of common Linux file, for reliability consideration, each data block can store multiple copy, is distributed in different chunkserver.GFSmaster is exactly the master server of GFS, is responsible for the metadata of maintaining file system, comprises NameSpace, access control, file-block mapping, block address etc., and the activity of control system level, as garbage reclamation, load balancing etc.Application needs the code linking client, and then client is mutual as agency and master and chunkserver.Master can regularly exchange with chunkserver, to obtain the state of chunkserver and to send instruction.Fig. 8 also describes the flow process that data are read in application: 1. application program 37 specifies certain segment data reading certain file, because data block is fixed length, client38 can calculate this segment data and span several data block, and the data block index of filename and needs is sent to master39 by client38; 2.master39 searches NameSpace 40 and file-block mapping table 41 according to filename, obtains the address at the data block copy place needed, and the address of the ID of data block and its all copy is fed back to client38; 3.client38 selects a copy 42, and contact chunkserver43 asks for the data 44 of needs; 4.chunkserver43 return data 44 gives client38.
The method of the data processing that the present invention proposes is applied in GFS, and specific implementation step is as follows:
S1: when certain file of Client application request certain data and carry out data processing, the data block index of filename and needs is sent to master server by client;
S2:master searches NameSpace and file-block mapping table according to filename, obtains the address at the data block copy place needed, and the address of the ID of data block and its all copy is fed back to client;
S3: client computer selects a copy, contact chunkserver.The tasks such as the comparison match module in the local memory device under Chunkserver carries out searching user requested data at memory device, coupling, as shown in Figure 9, the keyword message 45 of comparison match module user desired seek or coupling is configured by the host microcontroller in local memory device, then the raw data 46 of comparison match module in local memory device carries out data search and coupling, again the data result 47 searched and mate is returned to host microcontroller, host microcontroller does further process to user requested data again in memory device;
S4: local memory device by process after sub-result data pass to host computer system, chunkserver again return data to client.
Visible, the method that this matching module based on the comparison of the present invention accelerates to carry out processing in memory device is applied in GFS file system, the carrying of data between memory device and data server internal memory can be reduced, reduce the volume of transmitted data between client and data server, greatly reduce power consumption, comparison match module in the present invention can expedited data searching and mating in memory device, and then improve the performance of carrying out data processing in memory device inside.
In sum, the present invention proposes a kind of memory device and data processing method, comparison match module is with the addition of in memory device, software simulating can be used, also hardware implementing can be used, thus expedited data carries out in memory device inside searching, identifies, relatively or the task such as coupling, alleviate the operating load of central processing unit, improve the performance that memory device carries out data processing.
By illustrating and accompanying drawing, giving embodiment and describing in detail, for a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (11)
1. a memory device, is characterized in that, is applied to and comprises in the computer architecture of superior system, and described storage organization comprises:
Storage array, prestores pending data;
Host microcontroller, is connected with described superior system and described storage array respectively, for the data processing command that the described superior system of reception issues; And
Comparison match module, is connected with described host microcontroller and described storage array;
Wherein, described comparison match module processes the described pending data stored in described storage array according to described data processing command, and by described host microcontroller, result is fed back to described superior system.
2. memory device according to claim 1, is characterized in that, described comparison match module is hardware module.
3. memory device according to claim 1, is characterized in that, described comparison match module integration is in described host microcontroller.
4. memory device according to claim 1, is characterized in that, described comparison match module is Content Addressable Memory or Ternary Content Addressable Memory.
5. memory device according to claim 1, is characterized in that, described data processing command is data search order, data identification order, data comparison command or Data Matching order.
6. memory device according to claim 1, is characterized in that, described memory device comprises disk, solid state hard disc, network attached storage or Redundant Array of Independent Disks (RAID).
7. memory device according to claim 1, is characterized in that, described host microcontroller is connected by external interface with described superior system, so that described result is sent to described superior system.
8. a data processing method, is characterized in that, be applied to as in the memory device in claim 1 ~ 7 as described in any one, described method comprises:
S1: described superior system sends data processing command to described memory device;
S2: the described host microcontroller in described memory device receives described data processing command, and judge whether to need to carry out process operation to the data in described storage array according to described data processing command;
If the determination result is YES, S3 is performed;
Otherwise, perform S5;
S3: described data processing command is sent to described comparison match module by described host microcontroller;
S4: described comparison match module receives and according to described data processing command, processes the data in described storage array, and by described host microcontroller, result is back to described superior system;
Other data processed result are back to described superior system by S5: described host microcontroller carries out other data processing tasks in this locality simultaneously.
9. data processing method according to claim 7, is characterized in that, described data processing command is data search order, data identification order, data comparison command or Data Matching order.
10. data processing method according to claim 7, is characterized in that, described result is connected with described superior system by external interface by described host microcontroller.
11. memory devices according to claim 7, is characterized in that, described comparison match module is Content Addressable Memory or Ternary Content Addressable Memory.
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