CN105425256A - Tracking circuit and method compatible with continuous and pulse navigation signals - Google Patents

Abstract

The invention discloses a tracking circuit and method compatible with continuous and pulse navigation signals. The method comprises a continuous navigation signal tracking step and a pulse navigation signal tracking step. The pulse navigation signal tracking step comprises the following sub steps: (1) despreading, (2) NkHz integration zero clearing and a first-stage accumulation, (3) time slot determination, (4) 1kHz integration zero clearing and a second-stage accumulation, and (5) phase demodulation and filtering. The problem that a traditional navigation signal tracking circuit cannot achieve pulse navigation is solved; and baseband processing adopting the circuit can be compatible with tracking of a traditional continuous navigation signal on the condition that a circuit resource is not increased, and also can track a fixed time slot or pulse time slot navigation signal, and a signal tracking function in the baseband processing is expanded.

Description

A kind of compatibility continuously and the tracking circuit of cycle matching signal and method

Technical field

The invention belongs to communication technical field, particularly relate to a kind of compatibility continuously and the tracking circuit of cycle matching signal and method.

Background technology

The tracking circuit of satellite navigation signals is the crucial baseband processing circuitry of satellite navigation receiver, and main at present navigation signal (GPS GLONASS COMPASS) all adopts continuous signal to realize.A kind of typical correlator circuit for navigation signal tracking as shown in Figure 1.Tradition connects in satellite navigation receipts machine, and tracking channel generally includes advanced correlator (realizing satellite-signal relevant to advanced code PN_E), late correlator (realize satellite-signal and delayed code PN_L be correlated with) and current correlator (realizing satellite-signal relevant with instantaneous code PN_P) three complex correlator in order to produce advanced, the delayed and satellite signal correction computing after former code is with down coversion in this locality.The frequency that correlation exports is generally 1kHz.For upgrading local carrier and code control word after correlation carries out phase demodulation and filtering after exporting, realize signal trace.At present some navigation signals strengthened for region adopt pulse signal systems, but for the cycle matching signal of 1/N millisecond, conventional navigation signal trace correlator circuit cannot export the relevant accumulation result of 1/N millisecond for signal trace.

Summary of the invention

The object of the invention is to overcome the deficiencies in the prior art, there is provided a kind of compatibility continuously and the tracking circuit of cycle matching signal and method, under the condition not increasing circuit resource, solve conventional navigation signal tracking circuit cannot the problem of compatible tracking continuous navigation signal and cycle matching signal.

The object of the invention is to be achieved through the following technical solutions: a kind of compatibility continuously and the tracking circuit of cycle matching signal, it comprises DDC, multiple despreader and the multiple totalizer groups consistent with despreader quantity, every three despreaders form a despreader group, often organize despreader by advanced despreader, delayed despreader and current despreader composition, the input of DDC is connected with external digital intermediate-freuqncy signal, the I that DDC exports, Q signal is all broken into further 3 tunnels totally 6 road signals, 3 road I signals respectively with the advanced despreader of I signal despreader group, delayed despreader is connected with current despreader, similarly, 3 road Q signals respectively with the advanced despreader of Q signal despreader group, delayed despreader is connected with current despreader, the output of despreader is connected with totalizer group, it also comprises a time slot judgement unit, described totalizer group is made up of first order totalizer and second level totalizer, the output of each despreader is connected with first order totalizer, the output of first order totalizer is connected with second level totalizer, the output of first order totalizer is also connected with the input of time slot judgement unit, the output of time slot judgement unit is connected with the integration of second level totalizer/clearing control end.

A kind of compatibility tracking circuit that is continuous and cycle matching signal also comprises yard NCO and code generator, the input of code NCO is connected with foreign key control signal, the output of code NCO is connected with code generator, advanced, the delayed and current code control signal in 3 tunnels of code generator output respectively with often organize despreader and be connected by advanced despreader, delayed despreader and current despreader.

Compatibility tracking that is continuous and cycle matching signal comprises continuous navigation signal trace step and a cycle matching signal trace step, the described following sub-step of continuous navigation signal trace step:

S11: down coversion satellite-signal is sent into despreader with advanced code PN_E, delayed code PN_L and instantaneous code PN_P respectively and carries out de-spreading operation;

S12: the signal obtained by S11 carries out NkHz integrate-dump, and export integral result by totalizer 1;

S13: the data valid signal of time slot judgement unit to first order integrate-dump leads directly to the Enable Pin exporting second level integrate-dump to, realizes the direct accumulation operations of second level integrate-dump unit, and the frequency integrator realizing 1kHz is reset computing by final related channel program;

S14: phase demodulation and filtering are carried out in the output obtained by S13, for upgrading local carrier and code control word, realizes signal trace;

The described following sub-step of cycle matching signal trace step:

S21: down coversion satellite-signal is sent into despreader with advanced code PN_E, delayed code PN_L and instantaneous code PN_P respectively and carries out de-spreading operation;

S22: the signal obtained by S21 carries out NkHz integrate-dump, and export integral result by totalizer 1;

S23: time slot judgement unit is sent into each three groups of data of two-way that the integration of the NkHz produced by totalizer 1 exports, time slot judgement unit carries out asking modulo addition, and realize N group integration data choosing differentiation in 1ms, produce CE signal and 1kHz integrate-dump signal, totalizer 2 only completes 1 time according to CE signal and 1kHz integrate-dump signal and adds up in 1ms, and the 1kHz realizing 1/N millisecond correlation exports;

First time slot judgement unit carries out detection process to NkHz plural number integral result CE, CP and CL that first order integrate-dump circuit exports:

${\mathrm{AE}}_i=\left|{\mathrm{CE}}_i\right|=\sqrt{\mathrm{CE}\_I^2+\mathrm{CE}\_Q^2}$

${\mathrm{AP}}_i=\left|{\mathrm{CP}}_i\right|=\sqrt{\mathrm{CP}\_I^2+\mathrm{CP}\_Q^2}$

${\mathrm{AL}}_i=\left|{\mathrm{CL}}_i\right|=\sqrt{\mathrm{CL}\_I^2+\mathrm{CL}\_Q^2}$

In formula, CE_I, CE_Q, CP_I, CP_Q, CL_I, CL_Q are respectively the result of the I/Q two-way that down coversion satellite-signal is exported by totalizer 1 after despreading and NkHz integrate-dump;

And to AE within the quadratic integral clearing time _i, AP _iand Al _icarry out maximal value to search, if pulse signal is random slot, when maximal value occurs at i-th time slot, then show that signal appears at i-th time slot, the NkHz integral result of Enable Pin to i-th time slot then controlling second level integrate-dump exports, thus realizes differentiation and the integration output processing of signal slot; If pulse signal is fixing time slot, then export the enable signal of second level integrate-dump at fixing time slot by external unit control slot judgement unit;

S24: the result that S23 exports being carried out phase demodulation and filtering, for upgrading local carrier and code control word, realizing signal trace.

The invention has the beneficial effects as follows: the totalizer followed the tracks of in interlock circuit is divided into two-stage by (1) the present invention, first order totalizer realizes the relevant cumulative of NkHz, and the second level realizes the relevant cumulative of 1kHz; (2) the present invention designs time slot judgement unit, achieves and differentiates the pulse slot of timeslot burst signal immediately, and the correct correlation integral data exporting pulse slot.

Accompanying drawing explanation

Fig. 1 is conventional navigation signal tracking circuit structural drawing;

Fig. 2 is circuit structure diagram of the present invention;

Fig. 3 is the inventive method process flow diagram.

Embodiment

Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail: as shown in Figure 2, a kind of compatibility continuously and the tracking circuit of cycle matching signal, it comprises DDC, multiple despreader and the multiple totalizer groups consistent with despreader quantity, every three despreaders form a despreader group, often organize despreader by advanced despreader, delayed despreader and current despreader composition, the input of DDC is connected with external digital intermediate-freuqncy signal, the I that DDC exports, Q signal is all broken into further 3 tunnels totally 6 road signals, 3 road I signals respectively with the advanced despreader of I signal despreader group, delayed despreader is connected with current despreader, similarly, 3 road Q signals respectively with the advanced despreader of Q signal despreader group, delayed despreader is connected with current despreader, the output of despreader is connected with totalizer group, it also comprises a time slot judgement unit, described totalizer group is made up of first order totalizer and second level totalizer, the output of each despreader is connected with first order totalizer, the output of first order totalizer is connected with second level totalizer, the output of first order totalizer is also connected with the input of time slot judgement unit, the output of time slot judgement unit is connected with the integration of second level totalizer/clearing control end.

A kind of compatibility tracking circuit that is continuous and cycle matching signal also comprises yard NCO and code generator, the input of code NCO is connected with foreign key control signal, the output of code NCO is connected with code generator, advanced, the delayed and current code control signal in 3 tunnels of code generator output respectively with often organize despreader and be connected by advanced despreader, delayed despreader and current despreader.

As shown in Figure 3, a kind of compatibility tracking that is continuous and cycle matching signal comprises continuous navigation signal trace step and cycle matching signal trace step, the described following sub-step of continuous navigation signal trace step:

S11: down coversion satellite-signal is sent into despreader with advanced code PN_E, delayed code PN_L and instantaneous code PN_P respectively and carries out de-spreading operation;

S12: the signal obtained by S11 carries out NkHz integrate-dump, and export integral result by totalizer 1;

S13: the data valid signal of time slot judgement unit to first order integrate-dump leads directly to the Enable Pin exporting second level integrate-dump to, realizes the direct accumulation operations of second level integrate-dump unit, and the frequency integrator realizing 1kHz is reset computing by final related channel program;

S14: phase demodulation and filtering are carried out in the output obtained by S13, for upgrading local carrier and code control word, realizes signal trace;

The described following sub-step of cycle matching signal trace step:

S21: down coversion satellite-signal is sent into despreader with advanced code PN_E, delayed code PN_L and instantaneous code PN_P respectively and carries out de-spreading operation;

S22: the signal obtained by S21 carries out NkHz integrate-dump, and export integral result by totalizer 1;

S23: time slot judgement unit is sent into each three groups of data of two-way that the integration of the NkHz produced by totalizer 1 exports, time slot judgement unit carries out asking modulo addition, and realize N group integration data choosing differentiation in 1ms, produce CE signal and 1kHz integrate-dump signal, totalizer 2 only completes 1 time according to CE signal and 1kHz integrate-dump signal and adds up in 1ms, and the 1kHz realizing 1/N millisecond correlation exports;

First time slot judgement unit carries out detection process to NkHz plural number integral result CE, CP and CL that first order integrate-dump circuit exports:

${\mathrm{AE}}_i=\left|{\mathrm{CE}}_i\right|=\sqrt{\mathrm{CE}\_I^2+\mathrm{CE}\_Q^2}$

${\mathrm{AP}}_i=\left|{\mathrm{CP}}_i\right|=\sqrt{\mathrm{CP}\_I^2+\mathrm{CP}\_Q^2}$

${\mathrm{AL}}_i=\left|{\mathrm{CL}}_i\right|=\sqrt{\mathrm{CL}\_I^2+\mathrm{CL}\_Q^2}$

In formula, CE_I, CE_Q, CP_I, CP_Q, CL_I, CL_Q are respectively the result of the I/Q two-way that down coversion satellite-signal is exported by totalizer 1 after despreading and NkHz integrate-dump;

And to AE within the quadratic integral clearing time _i, AP _iand Al _icarry out maximal value to search, if pulse signal is random slot, when maximal value occurs at i-th time slot, then show that signal appears at i-th time slot, the NkHz integral result of Enable Pin to i-th time slot then controlling second level integrate-dump exports, thus realizes differentiation and the integration output processing of signal slot; If pulse signal is fixing time slot, then export the enable signal of second level integrate-dump at fixing time slot by external unit control slot judgement unit;

S24: the result that S23 exports being carried out phase demodulation and filtering, for upgrading local carrier and code control word, realizing signal trace.

Claims (3)

1. a compatibility continuously and the tracking circuit of cycle matching signal, it comprises DDC, multiple despreader and the multiple totalizer groups consistent with despreader quantity, every three despreaders form a despreader group, often organize despreader by advanced despreader, delayed despreader and current despreader composition, the input of DDC is connected with external digital intermediate-freuqncy signal, the I that DDC exports, Q signal is all broken into further 3 tunnels totally 6 road signals, 3 road I signals respectively with the advanced despreader of I signal despreader group, delayed despreader is connected with current despreader, similarly, 3 road Q signals respectively with the advanced despreader of Q signal despreader group, delayed despreader is connected with current despreader, the output of despreader is connected with totalizer group, it is characterized in that: it also comprises a time slot judgement unit, described totalizer group is made up of first order totalizer and second level totalizer, the output of each despreader is connected with first order totalizer, the output of first order totalizer is connected with second level totalizer, the output of first order totalizer is also connected with the input of time slot judgement unit, the output of time slot judgement unit is connected with the integration of second level totalizer/clearing control end.

2. a kind of compatibility according to claim 1 continuously and the tracking circuit of cycle matching signal, it is characterized in that: it also comprises yard NCO and code generator, the input of code NCO is connected with foreign key control signal, the output of code NCO is connected with code generator, advanced, the delayed and current code control signal in 3 tunnels of code generator output respectively with often organize despreader and be connected by advanced despreader, delayed despreader and current despreader.

3. compatibility is continuously and a tracking for cycle matching signal, it is characterized in that: it comprises continuous navigation signal trace step and cycle matching signal trace step, the described following sub-step of continuous navigation signal trace step:

S11: down coversion satellite-signal is sent into despreader with advanced code PN_E, delayed code PN_L and instantaneous code PN_P respectively and carries out de-spreading operation;

S12: the signal obtained by S11 carries out NkHz integrate-dump, and export integral result by totalizer 1;

S13: the data valid signal of time slot judgement unit to first order integrate-dump leads directly to the Enable Pin exporting second level integrate-dump to, realizes the direct accumulation operations of second level integrate-dump unit, and the frequency integrator realizing 1kHz is reset computing by final related channel program;

S14: phase demodulation and filtering are carried out in the output obtained by S13, for upgrading local carrier and code control word, realizes signal trace;

The described following sub-step of cycle matching signal trace step:

S21: down coversion satellite-signal is sent into despreader with advanced code PN_E, delayed code PN_L and instantaneous code PN_P respectively and carries out de-spreading operation;

S22: the signal obtained by S21 carries out NkHz integrate-dump, and export integral result by totalizer 1;

S23: time slot judgement unit is sent into each three groups of data of two-way that the integration of the NkHz produced by totalizer 1 exports, time slot judgement unit carries out asking modulo addition, and realize N group integration data choosing differentiation in 1ms, produce CE signal and 1kHz integrate-dump signal, totalizer 2 only completes 1 time according to CE signal and 1kHz integrate-dump signal and adds up in 1ms, and the 1kHz realizing 1/N millisecond correlation exports;

First time slot judgement unit carries out detection process to NkHz plural number integral result CE, CP and CL that first order integrate-dump circuit exports:

${\mathrm{AE}}_i=\left|{\mathrm{CE}}_i\right|=\sqrt{\mathrm{CE}\_I^2+\mathrm{CE}\_Q^2}$

${\mathrm{AP}}_i=\left|{\mathrm{CP}}_i\right|=\sqrt{\mathrm{CP}\_I^2+\mathrm{CP}\_Q^2}$

${\mathrm{AL}}_i=\left|{\mathrm{CL}}_i\right|=\sqrt{\mathrm{CL}\_I^2+\mathrm{CL}\_Q^2}$

In formula, CE_I, CE_Q, CP_I, CP_Q, CL_I, CL_Q are respectively the result of the I/Q two-way that down coversion satellite-signal is exported by totalizer 1 after despreading and NkHz integrate-dump;

And to AE within the quadratic integral clearing time _i, AP _iand Al _icarry out maximal value to search, if pulse signal is random slot, when maximal value occurs at i-th time slot, then show that signal appears at i-th time slot, the NkHz integral result of Enable Pin to i-th time slot then controlling second level integrate-dump exports, thus realizes differentiation and the integration output processing of signal slot; If pulse signal is fixing time slot, then export the enable signal of second level integrate-dump at fixing time slot by external unit control slot judgement unit;

S24: the result that S23 exports being carried out phase demodulation and filtering, for upgrading local carrier and code control word, realizing signal trace.