CN105407302A - Camera device and signal processing method - Google Patents
Camera device and signal processing method Download PDFInfo
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- CN105407302A CN105407302A CN201510449864.6A CN201510449864A CN105407302A CN 105407302 A CN105407302 A CN 105407302A CN 201510449864 A CN201510449864 A CN 201510449864A CN 105407302 A CN105407302 A CN 105407302A
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Abstract
A camera device includes a semiconductor substrate, photovoltaic conversion films, a first transistor, a first capacitor, a second capacitor, an initialization circuit portion and a control portion. The photovoltaic conversion films are laminated on the semiconductor substrate. A grid of the first capacitor is electrically connected to the photovoltaic conversion films. The first capacitor is electrically connected to a drain electrode of the first transistor. The second capacitor is electrically connected to the drain electrode of the first transistor. The initialization circuit portion respectively initializes a first electric charge quantity of the first capacitor and a second electric charge quantity of the second capacitor, so that the first electric charge quantity of the first capacitor and the second charge quantity of the second capacitor are constant in total quantity. The second electric charge quantity of the second capacitor reaches a specified amount. After the control portion is initialized by the initialization circuit portion, the first electric charge quantity moves to the first capacitor from the second capacitor through the first transistor according to the second electric charge quantity. A signal processing portion generates a signal component based on the second electric charge quantity generated by the photovoltaic conversion films according to the voltage of the first capacitor.
Description
The record of association request
The application advocates the priority of No. 2014-184370th, the Japanese patent application submitted to on September 10th, 2014, and is incorporated in by the full content of this application herein.
Technical field
Embodiments of the invention relate to camera head and signal processing method.
Background technology
CMOS (CMOS (Complementary Metal Oxide Semiconductor): ComplementaryMetalOxideSemiconductor) imageing sensor is a kind of solid camera head.In recent years, there is the situation of sensitivity decrease in the microminiaturization of accompanying image transducer.In order to solve this problem, the exploitation of the stacked camera head of the photoelectric conversion film of organic film etc. is adopted to advance.In stacked camera head, photoelectric conversion film is laminated in and defines in the Semiconductor substrate of transistor.Therefore, the area of each pixel both can be reduced, again can be effectively photosensitive.So, even if by pixel minitype, also can expect that the reduction of sensitivity is inhibited.
As a kind of method realizing stacked camera head, consider method photodiode being changed into photoelectric conversion film in the structure of the traditional solid camera head adopting photodiode.According to the method, in order to be electrically connected with the impurity diffusion zone (source drain) of the reset transistor in Semiconductor substrate by the electrode of photoelectric conversion film, high concentration impurities district must be formed in the impurity diffusion zone of reset transistor.
If form high concentration impurities district in the impurity diffusion zone of reset transistor, this high concentration impurities district is just formed as potential trough.Therefore, a part for the electric charge obtained by photoelectric conversion film is just caught by high concentration impurities district, just there will be the situation being difficult to these electric charges effectively to detect.
Accompanying drawing explanation
Fig. 1 is the block diagram of the general structure example of the camera head representing the first embodiment.
Fig. 2 is the diagram of the circuit structure example of set pixel in the camera head representing the first embodiment.
Fig. 3 is the diagram of the device architecture example of set pixel in the camera head representing the first embodiment.
Fig. 4 is the flow chart of a routine workflow of the camera head representing the first embodiment.
Fig. 5 is the sequential chart of the action of the camera head represented for explanation first embodiment.
Fig. 6 A is the diagram of one of current potential of pixel internal node in each process of the camera head action representing the first embodiment example.
Fig. 6 B is the diagram of one of current potential of pixel internal node in each process of the camera head action representing the first embodiment example.
Fig. 6 C is the diagram of one of current potential of pixel internal node in each process of the camera head action representing the first embodiment example.
Fig. 6 D is the diagram of one of current potential of pixel internal node in each process of the camera head action representing the first embodiment example.
Embodiment
Embodiments of the invention provide camera head and the signal processing method that effectively can detect the electric charge obtained by photoelectric conversion film.
The camera head of the embodiment of the present invention comprises Semiconductor substrate, photoelectric conversion film, the first transistor, the first capacitor, the second capacitor, initializing circuit portion and control part.Described photoelectric conversion film is on a semiconductor substrate stacked.The grid of described the first transistor is electrically connected with described photoelectric conversion film.Described first capacitor is electrically connected with the drain electrode of described the first transistor.Described second capacitor is electrically connected with the source electrode of described the first transistor.Second quantity of electric charge of first quantity of electric charge of described first capacitor and described second capacitor is distinguished initialization by described initializing circuit portion, to make the constant total quantity of second quantity of electric charge of first quantity of electric charge of described first capacitor and described second capacitor, and second quantity of electric charge of described second capacitor is made to reach ormal weight.After carrying out initialization by described initializing circuit portion, the amount of the second electric charge that described control part makes the first electric charge produce because of exposure according to described photoelectric conversion film is moved to described first capacitor from described second capacitor by described the first transistor.Described signal processing part generates the signal component based on the amount of the second electric charge produced by described photoelectric conversion film according to the voltage of described first capacitor.
Hereinafter, with reference to the accompanying drawings of camera head and the signal processing method of embodiment.
In the following description, the electrical connection between the parts of the camera head of embodiment can be direct connection, also can be indirectly to connect.Such as, when the Electrode connection of the source electrode of MOS transistor and capacitor, the impurity diffusion zone forming MOS transistor source electrode directly can be connected with the component forming electrode for capacitors, and the source electrode of MOS transistor and the electrode of capacitor also can be connected via other arbitrary conductive members indirectly.
(the first embodiment)
Fig. 1 is the block diagram of the general structure example of the camera head 1 representing the first embodiment.
Camera head 1 is provided with pel array 2, vertical scanning portion 3, horizontal sweep portion 4 and control part 5.Pel array 2 comprises multiple pixels 20 of rectangular arrangement.At the line direction of pel array 2, be provided with many selection holding wire 3-A1 selection signal SEL exported from vertical scanning portion 3 being sent to pixel 20,3-A2 ..., 3-An (n is natural number).Below, holding wire 3-Ai (i is the natural number meeting 1≤i≤n) is selected to refer to that many are selected holding wire 3-A1,3-A2 ..., one in 3-An.
At the line direction of pel array 2, select holding wire 3-A1,3-A2 with above-mentioned many ..., 3-An is provided with many control signal wire 3-B1 for transmitting reset signal group RST and the control signal CTL exported from vertical scanning portion 3 abreast, 3-B2 ..., 3-Bn.Below, control signal wire 3-Bi refers to many control signal wire 3-B1,3-B2 ..., one in 3-Bn.
At the column direction of pel array 2, be provided with many pixel signal line 4-1 picture element signal exported from pixel 20 (sign) being sent to horizontal sweep portion 4,4-2 ..., 4-m (m is natural number).Below, pixel signal line 4-j (j is the natural number meeting 1≤j≤m) refers to many pixel signal line 4-1,4-2 ..., one in 4-m.
The multiple pixels 20 forming pel array 2 are configured in many and select holding wire 3-A1,3-A2 ..., 3-An and many pixel signal line 4-1,4-2 ..., the intersection region of 4-m.
Fig. 2 is the diagram of the circuit structure example of set pixel 20 in the camera head 1 representing the first embodiment.In Fig. 2, column amplifier 40-j is the parts in the horizontal sweep portion 4 shown in Fig. 1, be respectively with pixel signal line 4-1,4-2 ..., one in the column amplifier that 4-m connects.In Fig. 2, show the structure of the pixel 20 be connected with pixel signal line 4-j, pixel signal line 4-j is connected with the multiple pixels 20 suitable with 1 amount arranged of the pel array 2 shown in Fig. 1.
Above-mentioned vertical scanning portion 3 provides the first reset signal RSTA, the second reset signal RSTB, the 3rd reset signal RSTC, control signal CTL and selects signal SEL to pixel 20.Further, pixel 20 is supplied to the first resetting voltage V
rSTA, the second resetting voltage V
rSTB, reference voltage V
rEF, bias voltage V
bISwith earth potential (GND).In a first embodiment, in order to make explanation easy understand, if the first resetting voltage V
rSTAfor 0.8V, the second resetting voltage V
rSTBfor 2.5V, reference voltage V
rEFfor 1.0V, bias voltage V
bISfor 10V.In a first embodiment, the first resetting voltage V
rSTA, the second resetting voltage V
rSTB, reference voltage V
rEFmagnitude relationship be set to V
rSTB>V
rEF>V
rSTA.As long as meet such condition, above-mentioned first resetting voltage V
rSTA, the second resetting voltage V
rSTB, reference voltage V
rEFeach value can at random set.Further, as long as the quantity of electric charge that the inside of photoelectric conversion film described later (photoelectric conversion part) 21 can be made to produce (hole-electron to) moves to the electrode of photoelectric conversion film 21, bias voltage V
bISvalue can be optional.
Pixel 20 comprises MOS transistor 22,23,25,27,28, first capacitor 24 and second capacitor 26 of photoelectric conversion film 21, n channel-type.Assuming that photoelectric conversion film 21 is made up of organic film.Do not limit by this example, arbitrary photoelectric conversion film can be used, as long as can be layered in Semiconductor substrate.First electrode (negative electrode) of photoelectric conversion film 21 is applied in 10V voltage as bias voltage V
bIS.Second electrode (anode) of photoelectric conversion film 21 is connected with the grid of MOS transistor 25.Photoelectric conversion film 21 one is subjected to illumination when exposing and penetrates, and photoelectric conversion film 21 just produces hole-electron pair, and the negative electrical charge formed by electronics is had bias voltage V via the first electrode (negative electrode)
bISsupply power absorb.Further, the positive charge formed by hole exports from second electrode (anode) of photoelectric conversion film 21, the grid of supply MOS transistor 25.
The drain electrode of MOS transistor 22 is applied in the voltage of 0.8V as the first resetting voltage V
rSTA, the grid of MOS transistor 22 is applied in the first reset signal RSTA.The source electrode of MOS transistor 22 is connected to second electrode (anode) of photoelectric conversion film 21, is connected to again the grid of MOS transistor 25.
The drain electrode of MOS transistor 23 is applied in the voltage of 2.5V as the second resetting voltage V
rSTB, the grid of MOS transistor 23 is applied in the second reset signal RSTB.The source electrode of MOS transistor 23 is connected with the drain electrode of MOS transistor 25.In a first embodiment, as described later, the source electrode of MOS transistor 23 is formed in Semiconductor substrate with the substrate side electrode of MOS capacitor and the drain electrode of MOS transistor 25 forming the first capacitor 24, and the source electrode of MOS transistor 23 is connected with the drain electrode of MOS transistor 25 via the substrate side electrode of the MOS capacitor of formation first capacitor 24.
The drain electrode of MOS transistor 27 is connected with the source electrode of MOS transistor 25, and the grid of MOS transistor 27 is applied in the 3rd reset signal RSTC.In a first embodiment, as described later, the drain electrode of MOS transistor 27 is formed in Semiconductor substrate with the substrate side electrode of MOS capacitor and the source electrode of MOS transistor 25 forming the second capacitor 26, and the drain electrode of MOS transistor 27 is connected with the source electrode of MOS transistor 25 via the substrate side electrode of the MOS capacitor of formation second capacitor 26.The source electrode of MOS transistor 27 is applied in the voltage of 1.0V as reference voltage V
rEF.
First capacitor 24 comprises across the first opposed electrode of insulator and the second electrode.First electrode of the first capacitor 24 is electrically connected on the drain electrode of MOS transistor 25.Second electrode of the first capacitor 24 is fixed on predetermined potential (such as earth potential).Therefore, between the drain electrode that is connected electrically in MOS transistor 25 of the first capacitor 24 and predetermined potential.First capacitor 24 is MOS (metal-oxide semiconductor: the MetalOxideSemiconductor) capacitors with planar structure.First electrode of the first capacitor 24 is the substrate side electrode of MOS capacitor, and the second electrode of the first capacitor 24 is the gate electrode side electrode of MOS capacitor.But the first capacitor 24 also can for having the capacitor of such as MIM (metal-insulator-metal type: the MetalInsulatorMetal) capacitor of channel structure etc.
Second capacitor 26 comprises across the first opposed electrode of insulator and the second electrode.First Electrode connection of the second capacitor 26 is in the source electrode of MOS transistor 25.Second electrode of the second capacitor 26 is applied in control signal CTL.Second capacitor 26 is for having MOS (MetalOxideSemiconductor) capacitor of planar structure.First electrode of the second capacitor 26 is the substrate side electrode of MOS capacitor, and the second electrode of the second capacitor 26 is the gate electrode side electrode of MOS capacitor.But the second capacitor 26 also can for having the capacitor of such as MIM (MetalInsulatorMetal) capacitor of channel structure etc.
First electrode of the first capacitor 24 is electrically connected on the drain electrode of MOS transistor 28.The grid of MOS transistor 28 is applied in selects signal SEL.The source electrode of MOS transistor 28 is connected to pixel signal line 4-j.MOS transistor 28 is by the voltage V of the first capacitor 24
24pixel signal line 4-j is sent to as picture element signal VSIG.Picture element signal VSIG is with the voltage V of the first capacitor 24
24for the voltage signal of signal level, picture element signal is exactly voltage V
24.
In the parts of above-mentioned pixel 20, MOS transistor 22,23,27 are configured for the initializing circuit portion (sign) of the internal node of initialized pixel 20 together with the vertical scanning portion 3 of supply control signal CTL.Above-mentioned initializing circuit portion, by the quantity of electric charge initialization of the first capacitor 24 and the second capacitor 26, to make the total amount of electric charge of the first capacitor 24 and the second capacitor 26 constant, and makes the quantity of electric charge of the second capacitor 26 reach ormal weight.
In the initialization of the above-mentioned quantity of electric charge of the first embodiment, above-mentioned initializing circuit portion before exposure by the second electrode bias of the second capacitor 26 in voltage V
cTL1(the first voltage) and the electric charge (electronics) of the second capacitor 26 is overflowed, thus make electric charge (electronics) move to the first capacitor 24 by transistor 25 from the second capacitor 26.By this initialization, the quantity of electric charge of the second capacitor 26 is adjusted to scheduled volume by above-mentioned initializing circuit portion.Further, after above-mentioned initialization, under the control of control part 5, vertical scanning portion 3 after exposure by the second electrode bias of the second capacitor 26 in voltage V
cTL2(the second voltage) and the electric charge (electronics) of the second capacitor 26 is overflowed, thus make electric charge (electronics) move to the first capacitor 24 by transistor 25 from the second capacitor 26, thus, take out the signal component corresponding with exposure, hereinafter will describe in detail this.
Column amplifier 40-j comprises the MOS transistor 41,42 of n channel-type.The drain electrode of MOS transistor 41 is supplied to supply voltage V
dD(such as 3.3V).Pixel signal line 4-j is connected to the grid of MOS transistor 41.The source electrode of MOS transistor 41 is connected to the drain electrode of MOS transistor 42.The grid of MOS transistor 42 is applied in offset signal GDMOS.The source electrode of MOS transistor 42 is fixed in earth potential (GND).The signal level of offset signal GDMOS is set to make MOS transistor 42 as constant-current source (or load circuit) work, thus column amplifier 40-j plays the effect of source follower.The tie point of the source electrode of MOS transistor 41 and the drain electrode of MOS transistor 42 is set as the efferent of column amplifier 40-j.
Get back to Fig. 1 to be described.Vertical scanning portion 3 is for driving multiple pixels 20 of arrangement in pel array 2 with row unit.Vertical scanning portion 3 export be used for row unit select to be formed the pixel 20 of pel array 2 selection signal SEL and for the reset signal group RST of the action that controls each pixel 20 and control signal CTL.Reset signal group RST comprises the first above-mentioned reset signal RSTA, the second reset signal RSTB and the 3rd reset signal RSTC.
Horizontal sweep portion 4 is parts that picture element signal for exporting each pixel 20 from pel array 2 carries out signal transacting.Horizontal sweep portion 4 comprises the column amplifier for being amplified by the picture element signal exported from each pixel 20 and is used for carrying out the picture element signal amplified the signal processing part of signal transacting.In a first embodiment, the signal processing part that comprises of horizontal sweep portion 4 is according to the voltage V of the first capacitor 24 forming pixel 20
24perform the signal transacting producing signal voltage VS, this signal voltage VS represents the signal component based on the quantity of electric charge produced by photoelectric conversion film 21.
Control part 5 is for controlling the integrated operation of camera head 1.In a first embodiment, control part 5 mainly performs the control relevant with the driving of pixel 20.Above-mentioned by MOS transistor 22,23, after the 27 initializing circuit portions formed carry out initialization, control part 5 performs following control: according to photoelectric conversion film 21 because the quantity of electric charge that exposure produces makes electric charge be moved to the first capacitor 24 from the second capacitor 26 forming pixel 20 by MOS transistor 25.The quantity of electric charge that photoelectric conversion film 21 produces by exposure is reflected by this electric charge amount of movement.
Fig. 3 is the diagram of a routine device architecture of set pixel 20 in the camera head 1 representing the first embodiment.As shown in Figure 3, pixel 20 is formed on a semiconductor substrate 100.The interarea of Semiconductor substrate 100 is formed with p-type impurity diffusion zone 101, it forms the well region of MOS transistor.N-shaped impurity diffusion zone 22D is formed, 22S, 23D, 23S, 24B, 25D, 25S, 26B, 27D, 27S in this impurity diffusion zone 101.Wherein impurity diffusion zone 22D and impurity diffusion zone 22S forms drain electrode and the source electrode of MOS transistor 22 respectively.Impurity diffusion zone 22D is applied in the first resetting voltage V
rSTA(such as 0.8V).Second electrode (anode) 21C of photoelectric conversion film 21 is electrically connected on impurity diffusion zone 22S.
Impurity diffusion zone 23D and impurity diffusion zone 23S forms drain electrode and the source electrode of MOS transistor 23 respectively.Impurity diffusion zone 23D is applied in the second resetting voltage V
rSTB(2.5V).Impurity diffusion zone 24B forms the substrate side electrode as the MOS capacitor of the first capacitor 24.Impurity diffusion zone 25D and impurity diffusion zone 25S forms drain electrode and the source electrode of MOS transistor 25 respectively.Impurity diffusion zone 26B forms the substrate side electrode as the MOS capacitor of the second capacitor 26.Impurity diffusion zone 27D and impurity diffusion zone 27S forms drain electrode and the source electrode of MOS transistor 27 respectively.Impurity diffusion zone 27S applied reference voltage V
rEF(1.0V).
The Semiconductor substrate 100 defining above-mentioned each impurity diffusion zone is formed with not shown dielectric film, is formed as MOS transistor 22 across above-mentioned not shown dielectric film, the conductive layer 22G of the grid of 23,25,27,23G, 25G, 27G.Further, on a semiconductor substrate 100, form conductive layer 24A, 26A, described conductive layer 24A across above-mentioned not shown dielectric film, 26A forms the gate electrode side electrode of the MOS capacitor as the first capacitor 24 and the second capacitor 26.
Conductive layer 22G is applied in the first reset signal RSTA, and conductive layer 23G is applied in the second reset signal RSTB.Further, conductive layer 24A is fixed in predetermined potential (such as earth potential).Second electrode 21C (anode) of photoelectric conversion film 21 is connected to conductive layer 25G.Conductive layer 26A is applied in the voltage V of control signal CTL
cTL.Conductive layer 27G is applied in the 3rd reset signal RSTC.
In the Semiconductor substrate 100 of conductive layer defining the grid as above-mentioned each MOS transistor, be laminated with photoelectric conversion film 21 across not shown insulator layer.Photoelectric conversion film 21 is made up of stacked organic film 21A, the first electrode 21B (negative electrode) and the second electrode 21C (anode).First electrode 21B is configured to across organic film 21A relative with the second electrode 21C.First electrode 21B is applied in 10V voltage as bias voltage V
bIS.Second electrode 21C is connected with the conductive layer 25G of the grid as MOS transistor 25, is connected again with the impurity diffusion zone 22S of the source electrode as MOS transistor 22.
In order to reduce area, MOS transistor 22,23,25,27 and the p-type impurity diffusion zone of capacitor 24,26 can be integrally formed, but also can implement element and be separated by forming respective diffusion region dividually.
Then, the operation of the camera head 1 of the first embodiment is also described with reference to Fig. 5 and Fig. 6 A ~ Fig. 6 D by the flow chart shown in Fig. 4.Fig. 4 is the flow chart of a routine operating process of the camera head 1 representing the first embodiment, Fig. 5 is used to the sequential chart of the operation of the camera head 1 of explanation first embodiment, and Fig. 6 A ~ Fig. 6 D is the diagram of one of current potential of pixel internal node in each process of the operation of the camera head 1 representing the first embodiment example.
Here, be described centered by the action of the pixel 20 shown in Fig. 2.Further, for the purpose of simplifying the description, suppose that the threshold voltage of the grid VT of the MOS transistor 22,23,25,27,28 shown in Fig. 2 is 0V, threshold voltage of the grid VT can set arbitrarily.
At first, under the control of control part 5, vertical scanning portion 3 is by the internal node initialization (step S1) of pixel 20.Specifically, the internal node of the 3 pairs of pixels 20 in vertical scanning portion carries out precharge (step S11).More particularly, in initial condition, vertical scanning portion 3, selection signal SEL is located at high level, selects signal SEL to make one's options to the pixel 20 in a line in pel array 2.
During moment t1 to moment t2 after the above-mentioned initial condition shown in Fig. 5, the first reset signal RSTA, the second reset signal RSTB and the 3rd reset signal RSTC are all located at high level by vertical scanning portion 3.Thus, MOS transistor 22,23,27 become conducting state, and the internal node of pixel 20 is precharged.That is, the grid of MOS transistor 25 is pre-charged to the first resetting voltage V by MOS transistor 22
rSTA(0.8V), the first capacitor 24 is pre-charged to the second resetting voltage V by MOS transistor 23
rSTB(2.5V), the second capacitor 26 is pre-charged to reference voltage V by MOS transistor 27
rEF(1.0V).
Here MOS transistor 25, its grid is applied in 0.8V voltage as the first resetting voltage V
rSTA, its source electrode is applied in 1.0V voltage as reference voltage V
rEF, its drain electrode is applied in 2.5V voltage as the second resetting voltage V
rSTB.Under this biasing condition, the grid voltage of MOS transistor 25 becomes the voltage of 0.2V lower than its source voltage.In this case, the grid voltage due to MOS transistor 25 does not exceed threshold voltage of the grid VT (=0V), and MOS transistor 25 becomes cut-off state.
The current potential of pixel 20 inside during Fig. 6 A represents between above-mentioned moment t1 and moment t2.As according to Fig. 6 A understand, the current potential corresponding to a part for the Semiconductor substrate 100 in the region forming MOS transistor 25 grid becomes the current potential of the substrate side electrode (impurity diffusion zone 24B) higher than the first electrode as the first capacitor 24, and the current potential of substrate side electrode (impurity diffusion zone 26B) higher than the second capacitor 26.Therefore, the first capacitor 24 and the second capacitor 26 are by MOS transistor 25 electric isolution.In this case, the first capacitor 24 is by the second resetting voltage V
rSTBcharging, the second capacitor 26 is by reference voltage V
rEFcharging.
Further, as shown in Figure 6A, grid is applied in the current potential of the channel region 23C of the MOS transistor 23 of the second reset signal RSTB of high level lower than the second resetting voltage V
rSTB, the source electrode (impurity diffusion zone 23S) of MOS transistor 23 and the current potential of the drain electrode current potential of (impurity diffusion zone 23D) and the substrate side electrode (impurity diffusion zone 24B) of the first capacitor 24 become by the second resetting voltage V
rSTBthe constant potential determined.And, the current potential that grid is applied in the channel region 27C of the MOS transistor 27 of the 3rd reset signal RSTC of high level is also low, and the current potential of the source electrode of MOS transistor 27 (impurity diffusion zone 27S) and the drain electrode current potential of (impurity diffusion zone 27D) and the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26 becomes by reference voltage V
rEFthe constant potential determined.
Then, under the control of control part 5, the first reset signal RSTA, the second reset signal RSTB and the 3rd reset signal RSTC are located at low level at moment t2 by vertical scanning portion 3.Thus, MOS transistor 22,23,27 become cut-off state.In this case, as shown in following Fig. 6 B, MOS transistor 23, the current potential of 27 respective channel region 23C, 27C rises.Thus, in the first capacitor 24 accumulation electric charge (electronics) and the second capacitor 26 in accumulate electric charge (electronics) be limited in by the region between the channel region 23C of MOS transistor 23 and the current potential of the channel region 27C of MOS transistor 27.
Here, MOS transistor 22,23,27 have noise RNZ (such as, kTC noise) to occur when moment t2 becomes cut-off state, be subject to the impact of this noise RNZ, the grid voltage V of MOS transistor 25
iNwith signal level (the i.e. voltage V of the first capacitor 24 of picture element signal VSIG
24) reduce.But, as long as MOS transistor 23 after this, 27 do not become conducting state, be limited in MOS transistor 23,27 respective channel region 23C, the electric charge (electronics) in the region between the current potential of 27C, the total amount of the electric charge (electronics) namely held in the first capacitor 24 and the second capacitor 26 keeps constant.
Then, under the control of control part 5, vertical scanning portion 3 adjusts the electric charge (step S12) of the second capacitor 26.Specifically, the voltage V of control signal CTL is made in moment t3 vertical scanning portion 3
cTLreduce voltage V
cTL1.Thus, as shown in Figure 6B, the current potential raised voltage V of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26
cTL1.At this moment, the current potential of the source area (impurity diffusion zone 25S) of the MOS transistor 25 be connected with the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26 exceedes the current potential of the channel region 25C of MOS transistor 25, and MOS transistor 25 becomes conducting state.Thus, the part exceeding the electric charge (electronics) accumulated in the second suitable capacitor 26 of the part of the current potential of the channel region 25C of MOS transistor 25 with the current potential of the source area (impurity diffusion zone 25S) of MOS transistor 25 is overflowed from the potential trough of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26, moves to the first capacitor 24 by MOS transistor 25 from the second capacitor 26.
Thus, in the second capacitor 26, the quantity of electric charge of accumulation is adjusted to by the fixed amount of the current potential height regulation of the channel region 25C of MOS transistor 25.Here, due to the grid voltage V of MOS transistor 25
iNbecome by the first resetting voltage V
rSTAthe predetermined value (0.8V) determined, in the second capacitor 26, the quantity of electric charge of accumulation becomes by the first resetting voltage V
rSTAthe scheduled volume of regulation.
Then, under the control of control part 5, vertical scanning portion 3 makes the voltage V of control signal CTL at moment t4
cTLboosted voltage V
cTL1and turn back to original value.Thus, as shown in following Fig. 6 C, the current potential of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26, is applied in the voltage V provided by the first resetting voltage VRSTA than grid
iN(0.8V) the potential drop low-voltage V of the channel region 25C of MOS transistor 25
cTL1.In this case, even if improve the voltage V of control signal CTL
cTL, electric charge (electronics) also can not occur to the inflow of the second capacitor 26 and electric charge (electronics) from the outflow of the second capacitor 26, in the second capacitor 26, the quantity of electric charge of accumulation is maintained at scheduled volume.In other words, even if change the voltage V of control signal CTL
cTL, also can not make the affected noise of the quantity of electric charge of the second capacitor 26.
Then, under the control of control part 5, vertical scanning portion 3 will move to the first capacitor 24 electric charge (residual charge) from the second capacitor 26 and eliminate (step S13).Specifically, in moment t5 vertical scanning portion 3, second reset signal RSTB is located at high level.Thus, the current potential of the channel region 23C of MOS transistor 23 reduces, MOS transistor 23 conducting.And MOS transistor 23 1 conducting, the residual charge (electronics) moving to the first capacitor 24 from the second capacitor 26 is just provided the second resetting voltage V by MOS transistor 23
rSTBpower supply (not shown) absorb.Therefore, the current potential of the substrate side electrode (impurity diffusion zone 24B) of the first capacitor 24 is reset to the second resetting voltage V
rSTBcurrent potential.
Then, at moment t6, under the control of control part 5, the second reset signal RSTB is located at low level by vertical scanning portion 3.Thus, as shown in following Fig. 6 C, the current potential of the channel region 23C of MOS transistor 23 rises, and MOS transistor 23 is ended.MOS transistor 23 1 is ended, and electric charge (electronics) is just limited in the potential trough of substrate side electrode (impurity diffusion zone 24B) of the first capacitor 24.
Then, under the control of control part 5, horizontal sweep portion 4 detects the voltage V of expression first capacitor 24
24picture element signal VSIG (step S2).Specifically, the voltage V of the first capacitor 24
24exported from pixel 20 by MOS transistor 28 as picture element signal VSIG.The picture element signal VSIG exported from pixel 20 to be supplied to the column amplifier 40-j in horizontal sweep portion 4 via pixel signal line 4-j.Output voltage V after picture element signal VSIG amplifies by column amplifier 40-j
out.The signal processing part (not shown) in horizontal sweep portion 4 is sampled and keeps voltage V
out.
Then, during moment t7 to moment t8, the exposure (step S3) to photoelectric conversion film 21 is carried out by the control of the system (not shown) of carrying camera head 1.Between this exposure period, under the control of control part 5, selection signal SEL is located at low level by vertical scanning portion 3.Photoelectric conversion film 21 is pressed sensitive volume and is produced electric charge (hole-electron to), and from second electrode (anode) of photoelectric conversion film 21 to grid supply positive charge (hole) of MOS transistor 25.Thus, the grid voltage V of MOS transistor 25
iNrise, become than the first resetting voltage V
rSTAexceed Δ V
iN.Therefore, as shown in Figure 6 C, the potential drop low-voltage Δ V of the channel region 25C of the first reset transistor 25
iN.
Then, at moment t8, under the control of control part 5, selection signal SEL is located at high level by vertical scanning portion 3.Thus, the voltage V of the first capacitor 24 of pixel 20
24be supplied to column amplifier 40-j as picture element signal VSIG, column amplifier 40-j becomes the state can amplifying picture element signal VSIG.
Then, under the control of control part 5, vertical scanning portion 3 makes electric charge move to the first capacitor 24 (step S4) according to exposure from the second capacitor 26.Specifically, during moment t9 to moment t10, vertical scanning portion 3 is by the voltage V of control signal CTL
cTLbe set in and fall voltage V
cTL2low-voltage on.Here, voltage V
cTL2absolute value be equal to or greater than above-mentioned voltage V
cTL1absolute value, and be equal to or less than the second resetting voltage V
rSTBwith reference voltage V
rEFthe absolute value of difference.But, not by the restriction of this example, voltage V
cTL2absolute value can be set in and be equal to or greater than voltage V
cTL1absolute value arbitrary value on.In a first embodiment, for the purpose of simplifying the description by voltage V
cTL2be set to and voltage V
cTL1equal.
Here, at the voltage V of moment t9 control signal CTL
cTLvoltage V is reduced once being set in
cTL2(=V
cTL1) voltage on, as shown in Figure 6 D, the current potential of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26 is with regard to boosted voltage V
cTL2(=V
cTL1).As mentioned above, the current potential of the channel region 25C of MOS transistor 25 is in and reduces voltage Δ V because of exposure
iNstate.Therefore, the current potential of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26 is once boosted voltage V
cTL2(=V
cTL1), a part for electric charge (electronics) is just overflowed from the potential trough of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26, moves to the first capacitor 24 by MOS transistor 25 from the second capacitor 26.
Now, the quantity of electric charge moving to the first capacitor 24 from the second capacitor 26 with because exposing the grid voltage V of the MOS transistor 25 caused
iNknots modification and voltage Δ V
iNcorresponding.Here suppose, if the grid voltage V of MOS transistor 25
iNdo not rise, voltage Δ V
iNfor 0V, then the current potential of the channel region 25C of MOS transistor 25 is maintained at and exceedes reference voltage V
rEFinitial potential on.Therefore, even if by the voltage V of control signal CTL
cTLboosted voltage V
cTL2(=V
cTL1), the current potential of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26 does not exceed the current potential of the channel region 25C of MOS transistor 25 yet, and rests on the state (with reference to Fig. 6 B) equal with the current potential of the channel region 25C of MOS transistor 25.Therefore, electric charge (electronics) does not move from the second capacitor 26 to the first capacitor 24.
In contrast, if the grid voltage V of MOS transistor 25
iNrise because of exposure i.e. voltage Δ V
iNbe greater than 0V, then the current potential of the substrate side electrode (impurity diffusion zone 26B) of the second capacitor 26 exceeds voltage Δ V than the current potential of the channel region 25C of MOS transistor 25
iN.Therefore, electric charge (electronics) moves from the second capacitor 26 to the first capacitor 24.This dislocation charge amount is according to voltage Δ V
iNdetermine.Therefore, by making control signal CTL boosted voltage V at moment t9
cTL2(=V
cTL1), the electric charge (electronics) corresponding with exposure moves to the first capacitor from the second capacitor 26.The voltage V of the first capacitor 24
24reduce due to the movement of this electric charge (electronics), this reducing amount becomes the signal voltage VS corresponding with signal component.
Then, under the control of control part 5, horizontal sweep portion 4 detects the voltage V of the first capacitor 24 representing corresponding to exposure
24picture element signal VSIG (step S5).
Specifically, the voltage V of the first corresponding to exposure capacitor 24
24exported from pixel 20 by MOS transistor 28 as picture element signal VSIG.The picture element signal VSIG exported from pixel 20 to be supplied to the column amplifier 40-j in horizontal sweep portion 4 via pixel signal line 4-j.Picture element signal VSIG amplifies and output voltage V by column amplifier 40-j
out.The signal processing part (not shown) in horizontal sweep portion 4 is sampled and keeps voltage V
out.
Then, under the control of control part 5, the voltage V that the signal processing part in horizontal sweep portion 4 obtains according to above-mentioned sampling
outcalculate signal voltage VS (step S6).Specifically, the signal processing part in horizontal sweep portion 4 calculates the voltage V based on the first capacitor 24 when aforementioned instant t6 second reset signal RSTB is located at low level
24voltage V
outsampled value and based on the voltage V at moment t9 control signal CTL
cTLbe located at voltage V
cTL2time the voltage V of the first capacitor 24
24voltage V
outsampled value between difference, and this result of calculation to be exported as signal voltage VS.This signal voltage VS represents the signal component that the quantity of electric charge that produces because of exposure with photoelectric conversion film 21 is suitable.
Then, be conceived to the threshold voltage of the grid VT of MOS transistor 25 and the voltage of each internal node remark additionally with regard to the operation of above-mentioned camera head 1.
In the structure of Fig. 2, the first reset signal RSTA, the second reset signal RSTB, the 3rd reset signal RSTC are once being located at high level, and MOS transistor 22,23,27 with regard to conducting.Thus, the grid voltage of MOS transistor 25 is set in the first resetting voltage V
rSTA(0.8V), its drain voltage is set in the second resetting voltage V
rSTB(2.5V), its source voltage is set in reference voltage V
rEF(1.0V).In this condition, owing to being that the grid voltage of benchmark MOS transistor 25 does not exceed threshold voltage of the grid VT with source voltage, MOS transistor 25 is ended.
Then, MOS transistor 22,23,27 cut-offs.Thus, as previously mentioned, the forbidden state of input and output that the drain electrode of MOS transistor 25 and the first capacitor 24 of source electrode and the second capacitor 26 become electric charge is connected to.
Then, control signal CTL is made to reduce voltage V
cTL1.Thus, the source voltage of MOS transistor 25 reduces.Consequently, take source voltage as benchmark, the grid voltage of MOS transistor 25 exceeds threshold voltage of the grid VT, and MOS transistor 25 becomes conducting state.Therefore, electric current flow to the first capacitor 24 (that is, electric charge (electronics) moves to the first capacitor 24 from the second capacitor 26) by MOS transistor 25 from the second capacitor 26.Based on this electric current, the voltage V of the second capacitor 26
26rise, and the source voltage of MOS transistor 25 rises.Then, take source voltage as benchmark, when the grid voltage of MOS transistor 25 reaches threshold voltage of the grid VT, (in other words, when source voltage reaches the voltage of threshold voltage of the grid VT lower than grid voltage) MOS transistor 25 is ended.Thus, the quantity of electric charge of the second capacitor 26 is adjusted to scheduled volume.
Then, at the voltage V of control signal CTL
cTLboosted voltage V
cTL1and after turning back to initial voltage, MOS transistor 23 becomes conducting state, thus the voltage of the first capacitor 24 is set in the second resetting voltage V again
rSTB.Then expose, the grid voltage V of MOS transistor 25
iNthe boosted voltage Δ V because of exposure
iN.
Then, at the voltage V of moment t9, control signal CTL
cTLbe lowered voltage V
cTL2.Thus the source voltage of MOS transistor 25 reduces, and therefore grid voltage becomes higher than source voltage, MOS transistor 25 conducting.In this case, due to grid voltage and the exposure correspondingly boosted voltage Δ V of MOS transistor 25
iN, with voltage V
cTL1source voltage boosted voltage Δ V is compared when being applied in as control signal CTL
iNstate under, MOS transistor 25 is ended.Thus, the magnitude of current corresponding to exposure flows to the second capacitor 26 from the first capacitor 24, and the quantity of electric charge corresponding to exposure moves to the first capacitor 24 by MOS transistor 25 from the second capacitor 26.As mentioned above, the amount of movement of this magnitude of current or electric charge is by the voltage V of the first capacitor 24
24reflection, from the voltage V of the first capacitor 24
24obtain signal voltage VS.
According to the first embodiment, the quantity of electric charge stored in the potential trough of the substrate side electrode (impurity diffusion zone 26B) of the first electrode as the second capacitor 26 is adjusted to scheduled volume, and by changing the voltage as the gate electrode side electrode (conductive layer 26A) of the second electrode of the second capacitor 26, with above-mentioned scheduled volume for the quantity of electric charge of spilling is moved to the first capacitor from the second capacitor 26 by benchmark, the electric charge of photoelectric conversion film 21 therefore can be detected while the impact of stress release treatment RNZ.
And, according to the first embodiment, the quantity of electric charge produced by photoelectric conversion film 21 can not be supplied MOS transistor 25 via the high concentration impurities diffusion region of Semiconductor substrate 100, therefore electric charge is not caught by the potential trough formed by high concentration impurities diffusion region, effectively can detect the quantity of electric charge that photoelectric conversion film 21 produces.
Therefore, according to the first embodiment, in the structure using photoelectric conversion film 21, can not detect by the impact of noise RNZ the quantity of electric charge that photoelectric conversion film 21 produces, and improve detection sensitivity.
And, according to the first embodiment, due to by a semiconductor substrate 100 stacked for photoelectric conversion film 21, can, by pixel minitype, photoelectric conversion film 21 can be used effectively photosensitive.
(the second embodiment)
Then, the second embodiment is described.
In second embodiment, to eliminate in above-mentioned first embodiment at moment t5 the second reset signal RSTB to the initialization of the voltage of the first capacitor 24, other aspects are identical with the first embodiment.Detection sensitivity can not be improved with affecting by noise RNZ by the second embodiment.
(the 3rd embodiment)
Then, the 3rd embodiment is described.
In 3rd embodiment, organic film is not used to adopt the device with the current generating properties being similar to photodiode etc. as photoelectric conversion film 21.Further, replace MOS transistor 22, be provided with the constant-current circuit of the load of serving as photoelectric conversion film 21.Thus, the voltage corresponding to the quantity of electric charge produced by photoelectric conversion film 21 is supplied in real time the grid of MOS transistor 25.Other structure is identical with the first embodiment.The same with the first embodiment, detection sensitivity can not be improved with affecting by noise RNZ by the 3rd embodiment.
The operation of the camera head 1 of the above embodiments, can state as the signal processing method performed in camera head 1.That is, this signal processing method is the signal processing method performed in camera head 1, and camera head 1 is made up of such as lower part: the MOS transistor 25 that stacked photoelectric conversion film 21 on a semiconductor substrate 100, its grid are supplied to the quantity of electric charge produced by photoelectric conversion film 21, be electrically connected with the drain electrode of MOS transistor 25 the first capacitor 25 (? 24) signal processing part in the second capacitor 26, be electrically connected with the source electrode of MOS2 transistor 25, control part 5 and horizontal sweep portion 4.The signal processing method of formation like this comprises first stage and second stage, in the first stage, after the initialization in described initializing circuit portion, the quantity of electric charge that electric charge is produced because of exposure according to photoelectric conversion film 21 is moved to the first capacitor 24 from the second capacitor 26 by MOS transistor 25; In second stage, the signal component of the quantity of electric charge that above-mentioned signal processing part produces from the voltage subtraction of the first capacitor 24 based on photoelectric conversion film 21.
According to camera head and the signal processing method of at least one embodiment above-described, the electric charge that photoelectric conversion film obtains effectively can be detected.
Be described with regard to several embodiments of the present invention above, but these embodiments just presentation by way of example, unintentionally scope of the present invention is limited.These embodiments can be implemented by other various forms, and can make various omission, displacement and change in the scope not departing from invention main points.These embodiments and distortion thereof are included in scope of the present invention and main points, are included in equally in the scope of the present invention and the equivalent thereof of setting forth in claims of the present invention.
Claims (10)
1. a camera head, comprising:
Semiconductor substrate;
Photoelectric conversion film, it is on the semiconductor substrate stacked;
The first transistor, it has the grid be electrically connected with described photoelectric conversion film;
First capacitor, it is electrically connected with the drain electrode of described the first transistor;
Second capacitor, it is electrically connected with the source electrode of described the first transistor;
Initializing circuit portion, second quantity of electric charge of first quantity of electric charge of described first capacitor and described second capacitor is distinguished initialization by it, to make the constant total quantity of second quantity of electric charge of first quantity of electric charge of described first capacitor and described second capacitor, and second quantity of electric charge of described second capacitor is made to reach ormal weight;
Control part, it is after described initializing circuit portion carries out initialization, and the amount of the second electric charge that the first electric charge is produced because of exposure according to described photoelectric conversion film is moved to described first capacitor from described second capacitor by described the first transistor; And
Signal processing part, its voltage according to described first capacitor generates the signal component based on the amount of the second electric charge produced by described photoelectric conversion film.
2. camera head as claimed in claim 1, is characterized in that,
Described second capacitor comprises the first electrode of being electrically connected with the source electrode of described the first transistor and the second electrode across insulator and described first electrode contraposition,
Described initializing circuit portion before exposure by described second electrode bias of described second capacitor in the first voltage, thus make tricharged move to described first capacitor by described the first transistor from described second capacitor,
Described control part after exposure by described second electrode bias of described second capacitor in the second voltage, thus make described first electric charge move to described first capacitor by described the first transistor from described second capacitor.
3. camera head as claimed in claim 1 or 2, is characterized in that,
Described first capacitor and described second capacitor are the capacitors with the channel structure formed on the semiconductor substrate.
4. camera head as claimed in claim 3, is characterized in that,
Described initializing circuit portion comprises:
Transistor seconds, its drain electrode is applied in the first resetting voltage, and grid is supplied to the first reset signal, the Electrode connection of source electrode and described photoelectric conversion film;
Third transistor, its drain electrode is applied in the second resetting voltage, and grid is supplied to the second reset signal, and source electrode is connected with the drain electrode of described the first transistor;
4th transistor, its drain electrode is connected with the source electrode of described the first transistor, and grid is supplied to the 3rd reset signal, source electrode applied reference voltage;
5th transistor, it is for sending the voltage of described first capacitor to pixel signal line,
Described first resetting voltage is higher than described reference voltage, and described second resetting voltage is lower than described reference voltage.
5. the signal processing method performed in camera head,
Described camera head comprises:
Semiconductor substrate;
Photoelectric conversion film, it is on the semiconductor substrate stacked;
The first transistor, its grid is electrically connected with described photoelectric conversion film;
First capacitor, it is electrically connected with the drain electrode of described the first transistor;
Second capacitor, it is electrically connected with the source electrode of described the first transistor;
Initializing circuit portion;
Control part; And
Signal processing part,
Described signal processing method comprises:
After carrying out initialization by described initializing circuit portion, the amount of the second electric charge that described control part produces because of exposure according to described photoelectric conversion film makes the first electric charge be moved to described first capacitor from described second capacitor by described the first transistor;
Described signal processing part generates the signal component based on the amount of the second electric charge produced by described photoelectric conversion film according to the voltage of described first capacitor.
6. signal processing method as claimed in claim 5, is characterized in that,
Second quantity of electric charge of first quantity of electric charge of described first capacitor and described second capacitor is distinguished initialization by the initialization performed by described initializing circuit portion, to make the constant total quantity of second quantity of electric charge of first quantity of electric charge of described first capacitor and described second capacitor, and second quantity of electric charge of described second capacitor is made to reach ormal weight.
7. signal processing method as claimed in claim 6, is characterized in that,
Described second capacitor comprises the first electrode of being electrically connected with the source electrode of described the first transistor and the second electrode across insulator and described first electrode contraposition,
By described first quantity of electric charge and described second quantity of electric charge respectively initialization comprise: before exposure by described second electrode bias of described second capacitor in the first voltage, thus make tricharged move to described first capacitor by described the first transistor from described second capacitor.
8. signal processing method as claimed in claim 6, is characterized in that,
Described first electric charge is moved comprise: after exposure by described second electrode bias of described second capacitor in the second voltage, thus make described first electric charge move to described first capacitor by described the first transistor from described second capacitor.
9. the signal processing method according to any one of claim 5 to 8, is characterized in that,
Described first capacitor and described second capacitor are the capacitors with the channel structure formed on the semiconductor substrate.
10. signal processing method as claimed in claim 9, is characterized in that,
Described initializing circuit portion comprises:
Transistor seconds, its drain electrode is applied in the first resetting voltage, and grid is supplied to the first reset signal, the Electrode connection of source electrode and described photoelectric conversion film;
Third transistor, its drain electrode is applied in the second resetting voltage, and grid is supplied to the second reset signal, and source electrode is connected with the drain electrode of described the first transistor;
4th transistor, its drain electrode is connected with the source electrode of described the first transistor, and grid is supplied to the 3rd reset signal, source electrode applied reference voltage; And
5th transistor, it is for sending the voltage of described first capacitor to pixel signal line,
Described first resetting voltage is higher than described reference voltage, and described second resetting voltage is lower than described reference voltage.
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| JP2014184370A JP2016058918A (en) | 2014-09-10 | 2014-09-10 | Lamination type imaging apparatus and signal processing method |
| JP2014-184370 | 2014-09-10 |
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|---|---|---|---|---|
| US20060164531A1 (en) * | 2005-01-27 | 2006-07-27 | Dun-Nian Yaung | Structure for CMOS image sensor |
| US7570292B2 (en) * | 2004-03-19 | 2009-08-04 | Fujifilm Corporation | Photoelectric conversion film, photoelectric conversion element, imaging element, method of applying electric field thereto and electric field-applied element |
| CN102196195A (en) * | 2010-03-05 | 2011-09-21 | 索尼公司 | Solid-state imaging device, method of fabricating solid-state imaging device, method of driving solid-state imaging device, and electronic apparatus |
| CN103369266A (en) * | 2012-03-29 | 2013-10-23 | 全视科技有限公司 | Imaging sensor pixel with floating diffusion switch, and system and operation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7570292B2 (en) * | 2004-03-19 | 2009-08-04 | Fujifilm Corporation | Photoelectric conversion film, photoelectric conversion element, imaging element, method of applying electric field thereto and electric field-applied element |
| US20060164531A1 (en) * | 2005-01-27 | 2006-07-27 | Dun-Nian Yaung | Structure for CMOS image sensor |
| CN102196195A (en) * | 2010-03-05 | 2011-09-21 | 索尼公司 | Solid-state imaging device, method of fabricating solid-state imaging device, method of driving solid-state imaging device, and electronic apparatus |
| CN103369266A (en) * | 2012-03-29 | 2013-10-23 | 全视科技有限公司 | Imaging sensor pixel with floating diffusion switch, and system and operation method thereof |
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