CN105406466A - Online fast local topology analysis method suitable for large power grid - Google Patents
Online fast local topology analysis method suitable for large power grid Download PDFInfo
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Abstract
The invention provides an online fast local topology analysis method suitable for a large power grid. The online fast local topology analysis method comprises the following steps: establishing a local topology analysis data model, and defining a data structure; determining a basic bus analysis range and a local bus analysis range; carrying out topology analysis for the basic bus analysis range; carrying out topology analysis for the local bus analysis range; and analyzing local system topology based on local bus topology analysis algorithm and result. The method is high in practicability, and can be used for solving the problem of quickly analyzing and calculating the topology of the large power grid under a remote signaling deflection condition of the power grid, tracking and updating the topology result in real time, flexibly defining the local topology analysis range, realizing fast topology analysis of the power grid within a self-defined range, providing a calculation and analysis foundation for scheduling various high level applications in an automatic system and further improving the practicability of an online analysis application.
Description
Technical Field
The invention relates to analysis, in particular to an online local topology analysis method suitable for a large power grid.
Background
Network topology analysis converts a physical model of a power system into a calculation model through topology analysis, and most of the current research on topology analysis is two major topology analysis methods, namely a search method and a matrix method.
(1) And (4) searching. Among the current network topology analysis algorithms, the search method and its various variants are the most conceivable and widely used ones. The method is mainly used for analyzing by searching the connection relation between a certain node and the adjacent node. According to different search principles, the method is divided into a depth-first search method and a breadth-first search method, which are carried out layer by layer according to layer search, and the number of times of searching adjacent vertexes of each vertex in a network is only once, so that repeated access to nodes does not exist in the search process, and the search efficiency is higher than that of the depth-first search method. However, in either method, an association table needs to be established to reflect the association relationship between node branches. The breadth search method only accesses each node once, and effectively improves the search speed. Searching using the stack technique is slow because some nodes need to be traced back. The searching range of the nodes can be narrowed to the plant station according to the principle that one switch cannot belong to different voltage levels, and the efficiency of the topology can be improved to a certain extent. In the literature, a method for optimizing the bus sequence in the later period is provided for solving the problem of discontinuous bus numbering caused by local topology correction.
(2) Matrix method. As can be seen from the theory of correlation of graph theory, the graph is uniquely determined by both the correlation matrix and the adjacency matrix, and therefore, the matrix method includes a correlation matrix method and an adjacency matrix method. The incidence matrix is a matrix representing the incidence relation between nodes and edges, and is 1 when the nodes are correlated and 0 when the nodes are not correlated. Generating a node-branch incidence matrix according to a network structure, solving a transposed matrix-branch-node incidence matrix of the node-branch incidence matrix, carrying out matrix multiplication on the transposed matrix and the branch-node incidence matrix to obtain an adjacency matrix, then carrying out operation on the adjacency matrix to obtain a full-connection matrix which reflects the connection relation between any two nodes in the network, and finally analyzing the full-connection matrix by a certain method to obtain a topological result. This is the correlation matrix method. The adjacency matrix is a matrix representing an adjacency relationship between nodes, and is 1 when nodes are connected with edges, and is 0 when nodes are not connected with edges. Therefore, it can intuitively reflect the network structure. And (4) operating the adjacent matrix to obtain a full-access matrix, and analyzing the full-access matrix to obtain a topological result. This is the contiguous matrix method. From the above description, it can be seen that the starting point of the two methods is slightly different, but the following analysis processes are substantially the same, and all the matrices are obtained by performing matrix multiplication on the adjacent matrices. The matrix method obtains the matrix representing the incidence relation between the nodes by defining matrix multiplication operation and then utilizing the transmission property and the symmetry property of connectivity, and the method is visual, clear in analysis process, simple in data organization and capable of saving CPU time, so that the method is suitable for topology analysis of any wiring mode of a power grid.
With the rapid development of power grids in China, the network scale is larger and larger, the scale of a computing node of a typical network reaches ten thousand orders of magnitude, and the requirement of large power grid scheduling on the computing speed of online analysis software is higher and higher. As a basic module in online analysis application, network topology analysis is responsible for providing a calculation model for other online analysis modules in an intelligent power grid scheduling technology support system, and the performance of the online analysis module is directly restricted by the calculation performance. Therefore, the calculation speed of the network topology analysis module must be further increased, and a fast analysis method for local topology of the large power grid needs to be developed according to the characteristics of the large power grid, a fast topology state correction technology for local remote signaling deflection of the large power grid is researched, the operation speed of the large power grid topology analysis software is increased, and therefore the practical level of the large power grid online analysis software is further increased.
Disclosure of Invention
In order to achieve the purpose, the invention provides an online local topology analysis method suitable for a large power grid, which can realize rapid analysis and calculation of the large power grid topology under the condition of remote signaling and deflection of the power grid, thereby greatly improving the calculation performance of the online analysis and calculation function application.
In order to achieve the purpose of the invention, the invention adopts the following technical scheme:
a quick local topology analysis method suitable for large power grid online comprises the following steps:
(1) constructing a local topology analysis data model and defining a data structure;
(2) determining a basic analysis range and a local analysis range of the bus;
(3) carrying out topology analysis aiming at the basic analysis range of the bus;
(4) carrying out topology analysis aiming at the bus local analysis range;
(5) and analyzing the local topology of the system based on a bus local topology analysis algorithm and a bus local topology analysis result.
Preferably, the local topology analysis data model in the step (1) is suitable for self-defined local topology analysis and event-triggered local topology analysis, and comprises a plant station data model, a voltage level data model and a bus local topology analysis data model; wherein,
the plant station data model comprises a plant station name, a voltage level inlet and a voltage level outlet;
the voltage grade data model comprises a logic number of a station, a bus inlet and a bus outlet;
the bus local topology analysis data model comprises a bus, a switch, a node, single-ended equipment and a branch.
Further, the defining data structure in step (1) includes: defining data structures of a bus, a switch end, a node, a branch end and single-ended equipment; splitting the switch end and the branch end, and defining data structures of the split switch end and the branch end; wherein,
the bus data structure comprises a forward pointer, a backward pointer, a scanning flag bit, an equipment linked list inlet and an electrical island number to which the equipment linked list inlet belongs;
a switch data structure including a switch name, a head end node number and a tail end node number;
the split switch end data structure comprises a switch end name, an associated node number and a logic number of a switch to which the switch belongs;
the node data structure comprises a bus logic number, an associated unit logic number, an associated load logic number, an associated reactance logic number, an associated switch end logic number, an associated branch end logic number and a scanning zone bit;
a branch data structure comprising a branch name, a head end node number, a tail end node number, a head end branch end logic number and a tail end branch end logic number;
the split branch end data structure comprises a correlation node logic number and a branch logic number to which the correlation node logic number belongs;
a single-ended device data structure comprising a device type and a device logic number.
Preferably, the step (2) of determining the bus basic analysis range and the bus local analysis range includes:
the switch, the nodes associated with the switch and the single-ended equipment are used as a basic analysis range of the bus without considering the opening and closing state of the switch; the boundary of the bus basic analysis range is a branch circuit;
collecting a full-network topology analysis result of a historical record, and taking a switch, a node and single-ended equipment related to a bus to which a node at the head end and the tail end of a position-changing switch belongs as a bus local analysis range; the bus basic analysis range comprises a bus local analysis range.
Preferably, in the step (3), the topology analysis of the bus basic analysis range is suitable for the initial or full-network topology analysis, and in the case that the switching action is more in the basic analysis range.
Further, the performing topology analysis on the basic bus analysis range specifically includes: initializing a nd array; optionally selecting one node as an initial node in the bus basic topology analysis range; closing the switch to enable the nodes associated with the switch to form a linked list until all the nodes are added into the linked list; the same BS is assigned to the nodes stored in the same linked list.
Preferably, in the step (4), the topology analysis of the bus local analysis range is suitable for the case that the switching action is less in the bus basic analysis range;
the topology analysis for the bus local analysis range comprises the following steps: only correction analysis is needed to be carried out on the relevant bus in the basic analysis range of the bus; the method specifically comprises the following steps:
aiming at single switch action, when the switch is switched on and off, the bs numbers of nodes at two ends of the switch are equal, and whether an opposite end node can be searched by closing any node at one end of the switch is judged; if yes, keeping the BS number of the topology analysis unchanged, and if not, splitting the current BS into two parts;
when the switch is closed, judging whether the BS belonged to the nodes at the two ends of the switch is equal, if so, keeping the BS unchanged,
if not, combining the two BSs into 1 BS;
aiming at a plurality of switch actions, circularly executing the analysis method of a single switch action until all action switches are analyzed; if the situation is complex, the topological analysis of the basic range of the bus is adopted.
Preferably, in the step (5), analyzing the local topology of the system includes, by using a result of analyzing the local topology of the bus, repartitioning the electrical island by a small amount of correction analysis;
analyzing the system local topology for a single switch closure comprises:
if the switch is closed and the BS combination is not caused, the topological analysis result of the system is kept unchanged;
if the switch is closed to cause different BSs to be combined, judging whether the island numbers of the different BSs are equal or not; if so, the system topology analysis result is kept unchanged; if not, combining the two electric islands into one, keeping the electric island corresponding to the smaller island number unchanged, and assigning the smaller island number to all BS [ ]. island of the electric island with the larger island number;
analyzing the system local topology for a single switch open includes:
if the switch is switched off to cause BS splitting, searching whether two split BSs have a connected path or not by adopting a wide area priority search algorithm according to the incidence relation of the bus and the branch, namely, whether one BS can find the other split BS or not by closing the branch; if yes, the system topology analysis is kept unchanged; if not, splitting one electric island into two electric islands, and judging whether the two electric islands after splitting both comprise the unit and the load.
Further, the specific method for judging comprises: if yes, keeping the island number of one electric island unchanged, and assigning a new island number to all BS [ ]. island of the other electric island; if any one of the electric islands does not contain the unit and the load, the island is a dead island, and the island number of the island is assigned to be-1;
when a plurality of switches are closed or opened, analysis of single switch action is executed in a circulating mode until all action switches are analyzed.
Compared with the prior art, the invention has the following beneficial effects:
(1) and (3) providing a bus local topology analysis technology. The method has the advantages that the local topology analysis data model is established, the basic topology analysis range and the real topology analysis range of the bus are defined, and the fast local topology analysis in the bus range can be realized to be matched with the local topology analysis of the system.
(2) And (3) providing a system local topology analysis technology. Based on a bus local topology analysis algorithm and a bus local topology analysis result, merging and splitting of the electric island are quickly judged by adopting a breadth-first path quick search technology according to telemetering displacement, and quick correction of system topology analysis is realized.
(3) The event-triggered local topology analysis scheme well combines the technologies of full-network topology analysis, bus local topology analysis and system local topology analysis, thereby not only ensuring the safety and stability of the algorithm, but also meeting the real-time property of topology analysis.
(4) The local topology analysis of the user-defined range can flexibly define the local topology analysis range of the power grid, and the software applicability is greatly improved.
Drawings
FIG. 1 is a diagram illustrating the results of a known topology analysis;
FIG. 2 is a schematic diagram of a local topology analysis range;
FIG. 3 is a flow chart of a local topology analysis process;
FIG. 4 is a diagram of a local topology data model structure.
Detailed Description
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
The invention relates to a rapid local topology analysis method suitable for a large power grid on line;
the network topology analysis is the basis of the on-line analysis and calculation of the power system, is suitable for the on-line rapid local topology analysis technology of the real-time operation of the large power grid, can realize the rapid analysis and calculation of the large power grid topology under the condition of remote signaling and deflection of the power grid, and can greatly improve the calculation performance of the on-line analysis and calculation function application.
The research result of the technology has wide application prospect, and the research result is applied to demonstration of various levels of scheduling mechanisms, so that the calculation speed of the intelligent power grid scheduling control system for analyzing various high-level applications on line can be further increased, and the capability of refining, lean and integrated operation of various levels of intelligent power grid scheduling is comprehensively supported. Meanwhile, the real-time performance of online analysis and calculation of the super-large-scale power grid can be effectively improved, powerful technical support is provided for safe, high-quality and economic operation of the extra-high voltage large power grid, the capacity of the power grid for dispatching and driving the large power grid is further improved, the safe, stable, high-quality and economic operation of the large power grid is guaranteed, and the method has important practical significance for improving the power service quality and ensuring stable development of the society.
The method comprises the following steps: (1) constructing a local topology analysis data model and defining a data structure; the local topology analysis is performed on the basis of the existing topology analysis results, which are shown in fig. 1.
The local topology analysis data model in the step (1) is suitable for user-defined local topology analysis and event-triggered local topology analysis, and comprises a plant station data model, a voltage level data model and a local topology analysis data model; the user-defined range local topology analysis means that a user can flexibly define a local power grid which is interested or concerned by the user, and the rapid topology analysis and calculation of the local power grid are realized. The event-triggered local topology analysis means that when a remote signaling deflection event is received, a local topology analysis algorithm is automatically triggered, and bus local topology analysis and system local topology analysis are respectively carried out to realize rapid correction of power grid topology analysis. The whole network topology analysis is periodically analyzed and calculated according to actual requirements, the event-triggered local topology monitoring remote signaling deflection is timely analyzed and calculated, and the user-defined range local topology is manually started to analyze and calculate according to user requirements.
The plant Station (ST) data model comprises a plant station name, a voltage level inlet and a voltage level outlet;
a voltage class (kV) data model, which comprises a logic number of a station, a bus inlet and a bus outlet;
the local topology analysis data model comprises buses, switches, nodes, single-ended equipment and branches.
Defining the data structure includes: defining data structures of a bus, a switch end, a node, a branch end and single-ended equipment; splitting the switch end and the branch end, and defining data structures of the split switch end and the branch end; wherein,
the Bus (BS) data structure comprises a forward pointer, a backward pointer, a scanning flag bit, an equipment linked list inlet and an electrical island number to which the equipment linked list inlet belongs;
a switch (CB) data structure including a switch name, a head end node number and a tail end node number;
a split switch side (CB2) data structure comprising a switch side name, an associated node number and a logical number of the switch to which it belongs;
the Node (ND) data structure comprises a bus logic number, an associated unit logic number, an associated load logic number, an associated reactance logic number, an associated switch end logic number, an associated branch end logic number and a scanning flag bit;
a tributary (BR) data structure comprising a tributary name, a head end node number, a tail end node number, a head end tributary end logic number and a tail end tributary end logic number;
a split tributary side (BR2) data structure including an association node logic number and an affiliated tributary logic number;
a single-ended Device (DEV) data structure including a device type and a device logic number. As shown in the following table:
TABLE 1 Bus (BS) data Structure
| Name of Chinese | English name | Data type |
| Forward pointer | fptr | int |
| Backward pointer | bptr | int |
| Scanning flag bit | q | int |
| Device chain table entry | idev | int |
| Belonging electric island number | island | int |
TABLE 2 switch (CB) data Structure
| Name of Chinese | English name | Data type |
| Switch name | name | char* |
| Head end nd number | ind | int |
| End nd number | jnd | int |
TABLE 3 switch side (CB2) data Structure
| Name of Chinese | English name | Data type |
| Switch terminal name | name | char* |
| Associated nd number | ind | int |
| Logic number of the switch | icb | int |
TABLE 4 Node (ND) data Structure
TABLE 5 Branch (BR) data Structure
| Name of Chinese | English name | Data type |
| Branch name | name | char* |
| Head end nd number | ind | int |
| End nd number | jnd | int |
| Head end tributary end logic number | ibr2 | int |
| End branch end logic number | jbr2 | int |
TABLE 6 Branch-end (BR2) data Structure
| Name of Chinese | English name | Data type |
| Associated nd logic number | ind | int |
| Logic number of the branch | ibr | int |
TABLE 7 Single-ended Device (DEV) Linked List data Structure
| Name of Chinese | English name | Data type |
| Type of device | typ | int |
| Logical number of equipment | pos | int |
| Associated nd logic number | ind | int |
For the data structures of BS, CB2, ND, BR2 and DEV, array variables are represented by BS, CB2, ND, BR2 and DEV, and subscripts of the array variables are represented by ibs, icb2, ind, ibr2 and idev. The data structure can be used for conveniently describing the interrelation among the single-ended equipment, the nodes, the switches and the buses.
In order to meet the flexible self-definition of local topology, a plant station local topology data model and a voltage level local topology data model are added on the basis of an original local topology analysis data model, and the three models are buckled with each other in a ring-to-ring mode, so that the flexible self-definition of the local topology is realized.
TABLE 8 Station (ST) data Structure
| Name of Chinese | English name | Data type |
| Name of factory station | name | char* |
| Voltage class entry | ikv | int |
| Voltage class outlet | jkv | int |
TABLE 9 Voltage class (KV) data Structure
The plant station data structure, the voltage level data structure and the local topology analysis data model jointly form a data model which is suitable for both full-network topology analysis and event-triggered local topology analysis and self-defined range local topology analysis, the data model comprises a plant station local topology model, a voltage level local topology model and a local topology model, the loops of the three-layer models are buckled one by one, and the logical structure of the three-layer models is shown in figure 4. Through the model, topological analysis of topological ranges such as a certain plant or a plurality of plants, a certain voltage grade of the certain plant, certain voltages of a plurality of plants, a plurality of voltage grades of the plurality of plants and the like can be flexibly specified, and the flexibility of a power grid topological analysis function is greatly developed.
(2) Determining a basic analysis range and a local analysis range of the bus;
the switch, the nodes associated with the switch and the single-ended equipment are used as a basic analysis range of the bus without considering the opening and closing state of the switch; the boundary of the bus basic analysis range is a branch circuit;
collecting a full-network topology analysis result of a historical record, and taking a switch, a node and single-ended equipment related to a bus to which a node at the head end and the tail end of a position-changing switch belongs as a bus local analysis range; the bus basic analysis range comprises a bus local analysis range.
(3) Carrying out topology analysis aiming at the basic analysis range of the bus; in the step (3), the topology analysis of the bus basic analysis range is suitable for the initial or full-network topology analysis and the situation that switching actions are more in the basic analysis range.
The topology analysis for the bus basic analysis range specifically includes: initializing a nd array; optionally selecting one node as an initial node in the bus basic topology analysis range; closing the switch to enable the nodes associated with the switch to form a linked list until all the nodes are added into the linked list; the same BS is assigned to the nodes stored in the same linked list. Taking the topological result shown in fig. 2 as an example, the analysis process specifically includes:
initializing scanning zone bits nd [ i ] q of all nodes to be 0, meaning not scanning, and nd [ i ] q to be 1, meaning scanned;
and nd [1] is included in the linked list 1, and is assigned with nd [1]. fptr as-1, and the scanned flag bit nd [1]. q as 1 is collocated, wherein fptr as-1 represents the end of the linked list.
Scanning all the associated closed switches of a current node nd [1] of the linked list 1, judging that a node nd [7] at the opposite end of the closed switch cb [1] is not scanned, therefore, the linked list 1 is included, assigning nd [1]. fptr to be 7, nd [7]. fptr to be-1, and setting a scanned flag position nd [7]. q to be 1.
And scanning nodes recorded with the value nd [1]. fptr being 7 in the linked list 1, namely all the associated closed switches nd [7], judging that a node nd [1] at the opposite end of the closed switch cb [1] is scanned, judging that a node nd [4] at the opposite end of the closed switch cb [2] is not scanned yet, including nd [4] in the linked list 1, assigning the value nd [7]. fptr being 4, and setting the value nd [4]. fptr being-1 and setting the scanned flag bit nd [4]. q being 1.
Nodes recorded with nd [7]. fptr ═ 4 in the scan chain table 1, that is, all the associated closed switches nd [4], are not scanned through the opposite end nd [3] associated with cb [3], so that the scan chain table 1 is included, and the scanned flag bits are assigned with nd [4]. fptr ═ 3, nd [3]. fptr ═ 1, and nd [3]. q ═ 1. At this time, cb [4] is in an open state, the end node nd [5] is not yet scanned, nd [5] is included in the linked list 2, the value nd [5]. fptr is-1, and the scanned flag nd [5]. q is set to 1.
And (3) scanning nodes recorded in the chain table 1, namely nd [4]. fptr being 3, namely nd [3] all associated closed switches, scanning nd [4] of the cb [3] opposite end, no other closed switches exist, and scanning nd [3]. fptr being-1, so that the chain table 1 is ended, and all nodes nd [3], nd [4], nd [7] and nd [1] in the chain table 1 belong to the same bus, and the bus bs [1] is distributed to the nodes.
And (2) scanning the linked list 2, wherein the current node nd [5] is all associated closed switches, and the opposite end node nd [6] of cb [5] is not scanned yet, so that the linked list 2 is included, and the values nd [5] fptr are 6, nd [6] fptr are-1, and the scanned flag bit nd [6] q is 1.
And scanning nodes recorded with the value nd [5]. fptr being 6 in the linked list 2, namely all the associated closure switches nd [6], judging that the node nd [5] at the opposite end of the closure switch cb [5] is scanned, judging that the node nd [2] at the opposite end of the closure switch cb [6] is not scanned yet, incorporating nd [2] into the linked list 2, assigning the value nd [6]. fptr to be 2, and setting the scanned flag bit nd [2]. q to be 1.
And scanning nodes recorded in the chain table 2 in the form of nd [6]. fptr being 2, namely nd [2] all associated closed switches, scanning nd [6] of the cb [6] opposite end, no other associated closed switches exist, and scanning nd [2]. fptr being-1, so that the chain table 2 is ended, and all the nodes nd [2], nd [6] and nd [5] in the chain table 2 belong to the same bus, and the bus bs [2] is allocated to the nodes.
(4) Carrying out topology analysis aiming at the bus local analysis range; in the step (4), the topological analysis of the bus local analysis range is suitable for the condition that the switching action is less in the bus basic analysis range;
the topology analysis for the bus local analysis range comprises the following steps: only correction analysis is needed to be carried out on the relevant bus in the basic analysis range of the bus; the method specifically comprises the following steps:
aiming at single switch action, when the switch is switched on and off, the bs numbers of nodes at two ends of the switch are equal, and whether an opposite end node can be searched by closing any node at one end of the switch is judged; if yes, keeping the BS number of the topology analysis unchanged, and if not, splitting the current BS into two parts;
when the switch is closed, judging whether the BS to which the nodes at the two ends of the switch belong are equal, if so, keeping the BS unchanged, and if not, combining the two BSs into 1;
aiming at a plurality of switch actions, circularly executing the analysis method of a single switch action until all action switches are analyzed; if the situation is complex, the topological analysis of the basic range of the bus is adopted.
(5) And analyzing the local topology of the system based on a bus local topology analysis algorithm and a bus local topology analysis result. The bus local topology analysis means that after remote signaling deflection, topology analysis is only carried out on the affected bus; the local topology analysis of the system refers to a rapid local topology analysis technology in a system range aiming at the influenced bus, branch and electric island after remote signaling deflection.
The electric island is divided again by a small amount of corrected analysis modes according to the result of the bus local topology analysis;
analyzing the system local topology for a single switch closure comprises:
if the switch is closed and the BS combination is not caused, the topological analysis result of the system is kept unchanged;
if the switch is closed to cause different BSs to be combined, judging whether the island numbers of the different BSs are equal or not; if so, the system topology analysis result is kept unchanged; if not, combining the two electric islands into one, keeping the electric island corresponding to the smaller island number unchanged, and assigning the smaller island number to all BS [ ]. island of the electric island with the larger island number;
analyzing the system local topology for a single switch open includes:
if the switch is switched off to cause BS splitting, searching whether two split BSs have a connected path or not by adopting a wide area priority search algorithm according to the incidence relation of the bus and the branch, namely, whether one BS can find the other split BS or not by closing the branch; if yes, the system topology analysis is kept unchanged; if not, splitting one electric island into two electric islands, and judging whether the two split electric islands comprise a unit and a load or not;
the specific method for judging comprises the following steps: if yes, keeping the island number of one electric island unchanged, and assigning a new island number to all BS [ ]. island of the other electric island; if any one of the electric islands does not contain the unit and the load, the island is a dead island, and the island number of the island is assigned to be-1;
when a plurality of switches are closed or opened, analysis of single switch action is executed in a circulating mode until all action switches are analyzed.
Finally, it should be noted that: the above embodiments are only intended to illustrate the technical solution of the present invention and not to limit the same, and a person of ordinary skill in the art can make modifications or equivalents to the specific embodiments of the present invention with reference to the above embodiments, and such modifications or equivalents without departing from the spirit and scope of the present invention are within the scope of the claims of the present invention as set forth in the claims.
Claims (9)
1. A quick local topology analysis method suitable for large power grid online is characterized by comprising the following steps:
(1) constructing a local topology analysis data model and defining a data structure;
(2) determining a basic analysis range and a local analysis range of the bus;
(3) carrying out topology analysis aiming at the basic analysis range of the bus;
(4) carrying out topology analysis aiming at the bus local analysis range;
(5) and analyzing the local topology of the system based on a bus local topology analysis algorithm and a bus local topology analysis result.
2. The method of claim 1, wherein the local topology analysis data model in step (1) is adapted for custom local topology analysis and event-triggered local topology analysis, including a plant station data model, a voltage level data model, and a bus bar local topology analysis data model; wherein,
the plant station data model comprises a plant station name, a voltage level inlet and a voltage level outlet;
the voltage grade data model comprises a logic number of a station, a bus inlet and a bus outlet;
the bus local topology analysis data model comprises a bus, a switch, a node, single-ended equipment and a branch.
3. The method of claim 2, wherein the defining the data structure in step (1) comprises: defining data structures of a bus, a switch end, a node, a branch end and single-ended equipment; splitting the switch end and the branch end, and defining data structures of the split switch end and the branch end; wherein,
the bus data structure comprises a forward pointer, a backward pointer, a scanning flag bit, an equipment linked list inlet and an electrical island number to which the equipment linked list inlet belongs;
a switch data structure including a switch name, a head end node number and a tail end node number;
the split switch end data structure comprises a switch end name, an associated node number and a logic number of a switch to which the switch belongs;
the node data structure comprises a bus logic number, an associated unit logic number, an associated load logic number, an associated reactance logic number, an associated switch end logic number, an associated branch end logic number and a scanning zone bit;
a branch data structure comprising a branch name, a head end node number, a tail end node number, a head end branch end logic number and a tail end branch end logic number;
the split branch end data structure comprises a correlation node logic number and a branch logic number to which the correlation node logic number belongs;
a single-ended device data structure comprising a device type and a device logic number.
4. The method of claim 1, wherein the step (2) of determining the bus bar fundamental analysis range and the bus bar local analysis range comprises:
the switch, the nodes associated with the switch and the single-ended equipment are used as a basic analysis range of the bus without considering the opening and closing state of the switch; the boundary of the bus basic analysis range is a branch circuit;
collecting a full-network topology analysis result of a historical record, and taking a switch, a node and single-ended equipment related to a bus to which a node at the head end and the tail end of a position-changing switch belongs as a bus local analysis range; the bus basic analysis range comprises a bus local analysis range.
5. The method according to claim 1, wherein in the step (3), the topology analysis of the bus basic analysis range is suitable for the initial or full-network topology analysis, and the case of more switching actions in the basic analysis range.
6. The method of claim 5, wherein the performing topology analysis on the bus bar fundamental analysis range specifically comprises: initializing a nd array; optionally selecting one node as an initial node in the bus basic topology analysis range; closing the switch to enable the nodes associated with the switch to form a linked list until all the nodes are added into the linked list; the same BS is assigned to the nodes stored in the same linked list.
7. The method according to claim 1, wherein in the step (4), the topological analysis of the bus local analysis range is suitable for the case of less switching actions within the bus basic analysis range;
the topology analysis for the bus local analysis range comprises the following steps: only correction analysis is needed to be carried out on the relevant bus in the basic analysis range of the bus; the method specifically comprises the following steps:
aiming at single switch action, when the switch is switched on and off, the bs numbers of nodes at two ends of the switch are equal, and whether an opposite end node can be searched by closing any node at one end of the switch is judged; if yes, keeping the BS number of the topology analysis unchanged, and if not, splitting the current BS into two parts;
when the switch is closed, judging whether the BS belonged to the nodes at the two ends of the switch is equal, if so, keeping the BS unchanged,
if not, combining the two BSs into 1 BS;
aiming at a plurality of switch actions, circularly executing the analysis method of a single switch action until all action switches are analyzed; if the situation is complex, the topological analysis of the basic range of the bus is adopted.
8. The method of claim 1, wherein in step (5), analyzing the local topology of the system comprises, using the results of the analysis of the local topology of the bus, repartitioning the electrical island by a small number of modified analysis modes;
analyzing the system local topology for a single switch closure comprises:
if the switch is closed and the BS combination is not caused, the topological analysis result of the system is kept unchanged;
if the switch is closed to cause different BSs to be combined, judging whether the island numbers of the different BSs are equal or not; if so, the system topology analysis result is kept unchanged; if not, combining the two electric islands into one, keeping the electric island corresponding to the smaller island number unchanged, and assigning the smaller island number to all BS [ ]. island of the electric island with the larger island number;
analyzing the system local topology for a single switch open includes:
if the switch is switched off to cause BS splitting, searching whether two split BSs have a connected path or not by adopting a wide area priority search algorithm according to the incidence relation of the bus and the branch, namely, whether one BS can find the other split BS or not by closing the branch; if yes, the system topology analysis is kept unchanged; if not, splitting one electric island into two electric islands, and judging whether the two electric islands after splitting both comprise the unit and the load.
9. The method according to claim 8, wherein the specific method of the judgment comprises: if yes, keeping the island number of one electric island unchanged, and assigning a new island number to all BS [ ]. island of the other electric island; if any one of the electric islands does not contain the unit and the load, the island is a dead island, and the island number of the island is assigned to be-1;
when a plurality of switches are closed or opened, analysis of single switch action is executed in a circulating mode until all action switches are analyzed.
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