CN105405846A - Dynamic random access memory unit structure - Google Patents

Dynamic random access memory unit structure Download PDF

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Publication number
CN105405846A
CN105405846A CN201511026453.2A CN201511026453A CN105405846A CN 105405846 A CN105405846 A CN 105405846A CN 201511026453 A CN201511026453 A CN 201511026453A CN 105405846 A CN105405846 A CN 105405846A
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voltage
junction
bit line
dram cell
cell structure
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CN105405846B (en
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杨光华
孔蔚然
杨光军
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

The invention relates to a dynamic random access memory unit structure. The dynamic random access memory unit structure comprises a floating NMOS transistor, a parasitic PN junction capacitor and a first P+ region formed in a top layer semiconductor layer of an SOI substrate; the source region, the channel region and the drain region of the floating NMOS transistor are all formed in the top layer semiconductor layer of the SOI substrate; a gate structure is formed at the top of the channel region; the gate structure is connected with a word line; the drain region is connected with a bit line; the first side of the first P+ region transversely contacts with the source region, so that the parasitic PN junction capacitor can be formed; the first P+ region is connected with a capacitor plate electrode; and by means of the characteristic that the electric leakage of the SOI substrate is low, the parasitic PN junction capacitor is adopted as a storage unit. The area of the dynamic random access memory unit structure of the invention can be reduced, and the operating voltage of the dynamic random access memory unit structure can be decreased.

Description

DRAM cell structure
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of DRAM cell structure.
Background technology
As shown in Figure 1A, be the schematic diagram of the first DRAM cell structure 101 existing; DRAM cell structure 101 is formed in silicon substrate 102, silicon substrate 102 is body silicon structure, shallow trench isolating oxide layer (STI) 103 is formed in silicon substrate 102, the drain region of NMOS tube is made up of N+ district 104a, source region is made up of N+ district 104b, the silicon substrate 102 of the P type doping between source region and drain region forms channel region, is formed with gate oxide and polysilicon gate 105 at top, channel region.Storage capacitance is made up of the N+ district 107 of polysilicon layer 106 and bottom and the dielectric layer be positioned at therebetween.Drain region 104a meets bit line BL, and polysilicon gate 105 meets wordline WL, and polysilicon layer 106 is connected with source region 104b, N+ district 107 ground connection GND.
Shown in Figure 1A, the first structure existing is the structure that 1T1CNMOS adds polysilicon capacity plate antenna, and storage capacitance is slab construction, has larger area overhead.
As shown in Figure 1B, be the schematic diagram of existing the second DRAM cell structure 201; DRAM cell structure 201 is formed in the P trap (P-well) 202 of silicon substrate, silicon substrate is body silicon structure, the drain region of NMOS tube is made up of N+ district 203a, source region is made up of N+ district 203b, P trap 202 between source region and drain region forms channel region, is formed with gate oxide and polysilicon gate 204 at top, channel region.Storage capacitance is made up of the N+ layer 205 be formed in groove, dielectric layer 206 and polysilicon layer (Poply-Si) 207.Drain region 203a meets bit line BL, and polysilicon gate 204 meets wordline WL, and N+ layer 205 is connected with source region 203b, polysilicon layer 207 ground connection GND.
Shown in Figure 1B, existing the second structure is the structure that 1T1CNMOS adds polysilicon channel capacitor, and storage capacitance is groove structure, can reduce the area of storage capacitance, but owing to adding the technique of groove, processing procedure is complicated by forming groove.
As shown in Figure 1 C, be the schematic diagram of the third DRAM cell structure 301 existing; DRAM cell structure 301 is formed in the top layer silicon 302 of SOI substrate, for burying oxide layer (BOX) 303 bottom described top layer silicon 302, described in bury bottom oxide layer 303 at the bottom of backing as back silicon substrate.Shallow trench isolating oxide layer 304 is formed in described top layer silicon 302; The drain region of NMOS tube is made up of N+ district 305a, source region is made up of N+ district 305b, and the p type island region 306 between source region and drain region forms channel region, is formed with gate oxide and polysilicon gate 307 at top, channel region.Storage capacitance is made up of the N+ district 308 of polysilicon layer 309 and bottom and the dielectric layer be positioned at therebetween.Drain region 305a meets bit line BL, and polysilicon gate 307 meets wordline WL, and polysilicon layer 309 is connected with source region 305b, N+ district 308 ground connection GND.
Although the third structure existing is formed in SOI substrate shown in Fig. 1 C, when the third structure existing is still for 1T1CNMOS adds the structure of polysilicon capacity plate antenna, storage capacitance is slab construction, has larger area overhead.
As shown in figure ip, be the schematic diagram of existing 4th kind of DRAM cell structure 401; DRAM cell structure 401 is formed in the top layer silicon 402 of SOI substrate, for burying oxide layer 403 bottom described top layer silicon 402, described in bury bottom oxide layer 403 at the bottom of backing as back silicon substrate (Si) 404.Shallow trench isolating oxide layer 405 is formed in described top layer silicon 402; The source region of NMOS tube is made up of N+ district 406a, drain region is made up of N+ district 406b, and the p type island region 407 between source region and drain region forms channel region, is formed with gate oxide and polysilicon gate 408 at top, channel region.Existing 4th kind of structure is 1TNMOS structure, does not need additionally to make storage capacitance, realizes the change of the threshold voltage of threshold value NMOS tube, thus realize the storage of information by stored charge in channel region 407.Although existing 4th kind no longer needs to adopt extra storage capacitance, operating voltage is higher.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of DRAM cell structure, can reduce area and reduce operating voltage.
For solving the problems of the technologies described above, DRAM cell structure provided by the invention comprises a buoyancy aid NMOS tube and a parasitic capacitance of PN junction.
The source region of described buoyancy aid NMOS tube, channel region and drain region are all formed in the top-layer semiconductor of SOI substrate, described source region and Dou You N+ district, described drain region composition, described channel region is made up of P type doped region, first side of described channel region and described drain region lateral contact, second side of described channel region and described source region lateral contact, be formed with grid structure at the top of described channel region; Described grid structure is connected with wordline, and described drain region is connected with bit line.
Be formed at the P+ district in the top-layer semiconductor of described SOI substrate, the first side and the described source region lateral contact in a described P+ district form described parasitic capacitance of PN junction, and a described P+ district connects capacitor plate electrode; Utilize the feature that the electric leakage of described SOI substrate is little, using described parasitic capacitance of PN junction as memory cell, the voltage in described source region is as storage node voltage.
Further improvement is, forms shallow trench isolating oxide layer in the top-layer semiconductor of described SOI substrate, utilizes the isolation that described shallow trench isolating oxide layer realizes between adjacent DRAM cell structure.
Further improvement is, is formed with the 3rd N+ district in the top-layer semiconductor of described SOI substrate, and the second side and the described 3rd N+ district in a described P+ district contact.
Further improvement is, described grid structure is made up of the gate dielectric layer on surface and polysilicon gate being formed at described channel region successively.
Further improvement is, described gate dielectric layer is gate oxide.
Further improvement is, DRAM cell structure comprise standby, write, read and refresh four kinds of operating states.
Further improvement is, when the operating state of described DRAM cell structure is standby:
Described wordline connects low level and makes the not conducting of described buoyancy aid NMOS tube.
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage.
Described bit line is connected to pre-charge voltage, and described pre-charge voltage is greater than described plate voltage and is less than described supply voltage.
When being " 1 " by the data of described cell stores, described storage node voltage is supply voltage; When being " 0 " by the data of described cell stores, described storage node voltage is greater than earth potential and is less than described plate voltage.
Further improvement is, when the operating state of described DRAM cell structure is for writing:
Described wordline connects high level and makes the conducting of described buoyancy aid NMOS tube.
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage.
Described bit line earthing potential when writing " 0 ", discharges to described parasitic capacitance of PN junction, makes described storage node voltage be earth potential.
During one writing, described bit line connects supply voltage, charges to described parasitic capacitance of PN junction, makes described storage node voltage be supply voltage.
Further improvement is, when the operating state of described DRAM cell structure is for reading:
Described wordline connects high level and makes the conducting of described buoyancy aid NMOS tube.
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage.
Described bit line and pre-charge voltage disconnect and are in floating state, and described bit line and described parasitic PN junction carry out charge-exchange, and when the signal that described parasitic PN junction stores is " 0 ", the current potential of described bit line reduces on the basis of pre-charge voltage; When the signal that described parasitic PN junction stores is " 1 ", the current potential of described bit line raises on the basis of pre-charge voltage.
The potential change of described bit line after sensitive amplifier circuit amplifies by data reading that described parasitic PN junction stores.
While data reading, carry out write operation to described parasitic capacitance of PN junction, when sense data is " 0 ", while reading, described bit line earthing potential, discharges to described parasitic capacitance of PN junction, makes described storage node voltage be earth potential; When sense data is " 1 ", while reading, described bit line connects supply voltage, charges to described parasitic capacitance of PN junction, makes described storage node voltage be supply voltage.
Further improvement is, when the operating state of described DRAM cell structure is for refreshing:
Described wordline connects high level and makes the conducting of described buoyancy aid NMOS tube.
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage.
Described bit line and pre-charge voltage disconnect and are in floating state, and described bit line and described parasitic PN junction carry out charge-exchange, and when the signal that described parasitic PN junction stores is " 0 ", the current potential of described bit line reduces on the basis of pre-charge voltage; When the signal that described parasitic PN junction stores is " 1 ", the current potential of described bit line raises on the basis of pre-charge voltage.
The data feedback that described parasitic PN junction stores by the potential change of described bit line after sensitive amplifier circuit amplifies is to described bit line; When the Data Data that described parasitic PN junction stores is " 0 ", described bit line earthing potential, discharges to described parasitic capacitance of PN junction, makes described storage node voltage be earth potential; When the Data Data that described parasitic PN junction stores is " 1 ", described bit line connects supply voltage, charges to described parasitic capacitance of PN junction, makes described storage node voltage be supply voltage.
Further improvement is, the value that when size of described plate voltage and described pre-charge voltage is configured such that and reads " 0 ", the current potential of described bit line reduces on the basis of pre-charge voltage and when reading " 1 " difference of the value that the current potential of described bit line raises on the basis of pre-charge voltage reduce, this difference is the smaller the better.
Further improvement is, described pre-charge voltage be described plate voltage and described supply voltage and half.
Further improvement is, described plate voltage is 1V.
Further improvement is, described DRAM cell structure writing, to read or refresh operation completes and all reverts to stand-by operation state.
Further improvement is, the top-layer semiconductor of described SOI substrate is top layer silicon, for burying oxide layer bottom described top layer silicon, described in bury bottom oxide layer as at the bottom of backing.
DRAM cell structure of the present invention is formed in the top-layer semiconductor of SOI substrate, utilize the feature that the electric leakage of described SOI substrate is little, directly using parasitic capacitance of PN junction as memory cell, the N-type region of parasitic capacitance of PN junction is directly made up of the source region of buoyancy aid NMOS tube, p type island region is made up of the P+ district be connected with source region.Relative to existing polysilicon slab electric capacity or polysilicon trench capacitance structure, parasitic capacitance of PN junction of the present invention has the little feature of area.But adopt parasitic capacitance of PN junction as the unit of storage capacitance, must in conjunction with the structure of SOI substrate of the present invention, if adopt body silicon, parasitic capacitance of PN junction has larger electric leakage, thus cannot realize the function of storage information.Therefore the present invention is by conjunction with SOI substrate and parasitic capacitance of PN junction, can reduce the area of device cell, thus the integrated level of memory can be improved.
In addition, the present invention adopts parasitic capacitance of PN junction as memory cell, parasitic capacitance of PN junction has less operating voltage, to the read-write of parasitic PN junction and refresh operation simply and do not need to provide extra high-tension circuit, therefore the 1TNMOS structure relative to existing 4th kind, mode of operation of the present invention is simple and can reduce operating voltage, without the need to extra high-tension circuit support.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Figure 1A to Fig. 1 D is the schematic diagram of existing four kinds of DRAM cell structures;
Fig. 2 is the schematic diagram of embodiment of the present invention DRAM cell structure;
Fig. 3 is the equivalent circuit diagram of Fig. 2;
Fig. 4 is the operation waveform schematic diagram of embodiment of the present invention circuit.
Embodiment
As shown in Figure 2, be the schematic diagram of embodiment of the present invention DRAM cell structure; As shown in Figure 3, be the equivalent circuit diagram of Fig. 2; Embodiment of the present invention DRAM cell structure comprises buoyancy aid NMOS tube 1 and a parasitic capacitance of PN junction 2.
The source region 7 of described buoyancy aid NMOS tube 1, channel region 8 and drain region 6 are all formed in the top-layer semiconductor 3 of SOI substrate, described source region 7 and Dou You N+ district, described drain region 6 composition, described channel region 8 is made up of P type doped region, first side of described channel region 8 and described drain region 6 lateral contact, second side of described channel region 8 and described source region 7 lateral contact, be formed with grid structure at the top of described channel region 8; Described grid structure is connected with wordline WL, and described drain region 6 is connected with bit line BL.
Be formed at the P+ district 10 in the top-layer semiconductor 3 of described SOI substrate, the first side and described source region 7 lateral contact in a described P+ district 10 form described parasitic capacitance of PN junction 2, and a described P+ district 10 connects capacitor plate electrode VCC_plate; Utilize the feature that the electric leakage of described SOI substrate is little, using described parasitic capacitance of PN junction 2 as memory cell, the voltage in described source region 7 is as storage node voltage Vnode.
In the embodiment of the present invention, in the top-layer semiconductor 3 of described SOI substrate, form shallow trench isolating oxide layer 5, utilize the isolation that described shallow trench isolating oxide layer 5 realizes between adjacent DRAM cell structure.
In the top-layer semiconductor 3 of described SOI substrate, be formed with the 3rd N+ district 11, the second side and the described 3rd N+ district 11 in a described P+ district 10 contact.
Described grid structure is made up of the gate dielectric layer on surface and polysilicon gate 9 being formed at described channel region 8 successively.Described gate dielectric layer is gate oxide.
Be preferably, the top-layer semiconductor 3 of described SOI substrate is top layer silicon, for burying oxide layer 4 bottom described top layer silicon 3, described in bury at the bottom of backing or be called support substrates bottom oxide layer 4, support substrates can adopt silicon support substrates.
As shown in Figure 4, be the operation waveform schematic diagram of embodiment of the present invention circuit; Include the operation waveform of three signals, be respectively the waveform of word-line signal and signal WL, the waveform of bit line signal and signal BL and the waveform of storage node voltage Vnode; And signal BL comprises two with BL (0,1) expression according to the different curve of storage data, correspond respectively to the situation of data " 0 " and data " 1 "; And storage node voltage Vnode comprises two with Vnode (0,1) expression according to the different curve of storage data, correspond respectively to the situation of data " 0 " and data " 1 ".Embodiment of the present invention DRAM cell structure comprises standby (Standby), writes (Write), reads (Read) and refresh (Refresh) four kinds of operating states.
Shown in the holding state in figure 4, when the operating state of described DRAM cell structure is standby:
Described wordline WL connects low level i.e. GND current potential and makes the not conducting of described buoyancy aid NMOS tube 1.
Described capacitor plate electrode VCC_plate connects plate voltage Vccplate, and described plate voltage Vccplate is greater than the cut-in voltage of described parasitic capacitance of PN junction 2 and is less than supply voltage VCC.
Described bit line BL is connected to pre-charge voltage VPRE, and described pre-charge voltage VPRE is greater than described plate voltage Vccplate and is less than described supply voltage VCC.
When being " 1 " by the data of described cell stores, described storage node voltage Vnode is supply voltage VCC; When being " 0 " by the data of described cell stores, described storage node voltage Vnode is greater than ground GND current potential and is less than described plate voltage Vccplate.
Shown in the write cycle time state in figure 4, when the operating state of described DRAM cell structure is for writing:
Described wordline WL connects high level and makes the conducting of described buoyancy aid NMOS tube 1.
Described capacitor plate electrode VCC_plate connects plate voltage Vccplate, and described plate voltage Vccplate is greater than the cut-in voltage of described parasitic capacitance of PN junction 2 and is less than supply voltage VCC.
Described bit line BL ground connection GND current potential when writing " 0 ", discharges to described parasitic capacitance of PN junction 2, makes described storage node voltage Vnode for ground GND current potential.
During one writing, described bit line BL meets supply voltage VCC, charges to described parasitic capacitance of PN junction 2, makes described storage node voltage Vnode be supply voltage VCC.
After write cycle time terminates, operating state returns to holding state.
Shown in the read cycle state in figure 4, when the operating state of described DRAM cell structure is for reading:
Described wordline WL connects high level and makes the conducting of described buoyancy aid NMOS tube 1.
Described capacitor plate electrode VCC_plate connects plate voltage Vccplate, and described plate voltage Vccplate is greater than the cut-in voltage of described parasitic capacitance of PN junction 2 and is less than supply voltage VCC.
Described bit line BL and pre-charge voltage VPRE disconnects and is in floating state, described bit line BL and described parasitic PN junction carry out charge-exchange, when the signal that described parasitic PN junction stores is " 0 ", the current potential of described bit line BL reduces on the basis of pre-charge voltage VPRE; When the signal that described parasitic PN junction stores is " 1 ", the current potential of described bit line BL raises on the basis of pre-charge voltage VPRE.
The potential change of described bit line BL after sensitive amplifier circuit amplifies by data reading that described parasitic PN junction stores.
After data reading, described storage node voltage Vnode can increase accordingly or reduce, therefore need to occur writing it, also namely while data reading, write operation is carried out to described parasitic capacitance of PN junction 2, when sense data is " 0 ", while reading, described bit line BL ground connection GND current potential, described parasitic capacitance of PN junction 2 is discharged, makes described storage node voltage Vnode for ground GND current potential; When sense data is " 1 ", while reading, described bit line BL meets supply voltage VCC, charges to described parasitic capacitance of PN junction 2, makes described storage node voltage Vnode be supply voltage VCC.
After read cycle terminates, operating state returns to holding state.
Shown in the refresh cycle state in figure 4, when the operating state of described DRAM cell structure is for refreshing:
Described wordline WL connects high level and makes the conducting of described buoyancy aid NMOS tube 1.
Described capacitor plate electrode VCC_plate connects plate voltage Vccplate, and described plate voltage Vccplate is greater than the cut-in voltage of described parasitic capacitance of PN junction 2 and is less than supply voltage VCC.
Described bit line BL and pre-charge voltage VPRE disconnects and is in floating state, described bit line BL and described parasitic PN junction carry out charge-exchange, when the signal that described parasitic PN junction stores is " 0 ", the current potential of described bit line BL reduces on the basis of pre-charge voltage VPRE; When the signal that described parasitic PN junction stores is " 1 ", the current potential of described bit line BL raises on the basis of pre-charge voltage VPRE.
The data feedback that described parasitic PN junction stores by the potential change of described bit line BL after sensitive amplifier circuit amplifies is to described bit line BL; When the Data Data that described parasitic PN junction stores is " 0 ", described bit line BL ground connection GND current potential, discharges to described parasitic capacitance of PN junction 2, makes described storage node voltage Vnode for ground GND current potential; When the Data Data that described parasitic PN junction stores is " 1 ", described bit line BL meets supply voltage VCC, charges to described parasitic capacitance of PN junction 2, makes described storage node voltage Vnode be supply voltage VCC.
In the embodiment of the present invention, the value that when size of described plate voltage Vccplate and described pre-charge voltage VPRE is configured such that and reads " 0 ", the current potential of described bit line BL reduces on the basis of pre-charge voltage VPRE and when reading " 1 " difference of the value that the current potential of described bit line BL raises on the basis of pre-charge voltage VPRE reduce, this difference is the smaller the better, the value that the current potential reading described bit line BL time " 0 " reduces on the basis of pre-charge voltage VPRE and when reading " 1 " current potential of described bit line BL raise on the basis of pre-charge voltage VPRE value equal and opposite in direction time best.Actually to arrange, described pre-charge voltage VPRE is that described plate voltage Vccplate can set according to the characteristic of described buoyancy aid NMOS tube 1 and described parasitic capacitance of PN junction 2, plate voltage Vccplate is 1V as will be described, described pre-charge voltage VPRE is set to described plate voltage Vccplate and described supply voltage VCC's and half.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.

Claims (15)

1. a DRAM cell structure, is characterized in that, comprises a buoyancy aid NMOS tube and a parasitic capacitance of PN junction;
The source region of described buoyancy aid NMOS tube, channel region and drain region are all formed in the top-layer semiconductor of SOI substrate, described source region and Dou You N+ district, described drain region composition, described channel region is made up of P type doped region, first side of described channel region and described drain region lateral contact, second side of described channel region and described source region lateral contact, be formed with grid structure at the top of described channel region; Described grid structure is connected with wordline, and described drain region is connected with bit line;
Be formed at the P+ district in the top-layer semiconductor of described SOI substrate, the first side and the described source region lateral contact in a described P+ district form described parasitic capacitance of PN junction, and a described P+ district connects capacitor plate electrode; Utilize the feature that the electric leakage of described SOI substrate is little, using described parasitic capacitance of PN junction as memory cell, the voltage in described source region is as storage node voltage.
2. DRAM cell structure as claimed in claim 1, it is characterized in that: in the top-layer semiconductor of described SOI substrate, form shallow trench isolating oxide layer, utilize the isolation that described shallow trench isolating oxide layer realizes between adjacent DRAM cell structure.
3. DRAM cell structure as claimed in claim 1, it is characterized in that: in the top-layer semiconductor of described SOI substrate, be formed with the 3rd N+ district, the second side and the described 3rd N+ district in a described P+ district contact.
4. DRAM cell structure as claimed in claim 1, is characterized in that: described grid structure is made up of the gate dielectric layer on surface and polysilicon gate being formed at described channel region successively.
5. DRAM cell structure as claimed in claim 4, is characterized in that: described gate dielectric layer is gate oxide.
6. DRAM cell structure as claimed in claim 1, is characterized in that: DRAM cell structure comprise standby, write, read and refresh four kinds of operating states.
7. DRAM cell structure as claimed in claim 6, is characterized in that: when the operating state of described DRAM cell structure is standby:
Described wordline connects low level and makes the not conducting of described buoyancy aid NMOS tube;
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage;
Described bit line is connected to pre-charge voltage, and described pre-charge voltage is greater than described plate voltage and is less than described supply voltage;
When being " 1 " by the data of described cell stores, described storage node voltage is supply voltage; When being " 0 " by the data of described cell stores, described storage node voltage is greater than earth potential and is less than described plate voltage.
8. DRAM cell structure as claimed in claim 6, is characterized in that: when the operating state of described DRAM cell structure is for writing:
Described wordline connects high level and makes the conducting of described buoyancy aid NMOS tube;
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage;
Described bit line earthing potential when writing " 0 ", discharges to described parasitic capacitance of PN junction, makes described storage node voltage be earth potential;
During one writing, described bit line connects supply voltage, charges to described parasitic capacitance of PN junction, makes described storage node voltage be supply voltage.
9. DRAM cell structure as claimed in claim 6, is characterized in that: when the operating state of described DRAM cell structure is for reading:
Described wordline connects high level and makes the conducting of described buoyancy aid NMOS tube;
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage;
Described bit line and pre-charge voltage disconnect and are in floating state, and described bit line and described parasitic PN junction carry out charge-exchange, and when the signal that described parasitic PN junction stores is " 0 ", the current potential of described bit line reduces on the basis of pre-charge voltage; When the signal that described parasitic PN junction stores is " 1 ", the current potential of described bit line raises on the basis of pre-charge voltage;
The potential change of described bit line after sensitive amplifier circuit amplifies by data reading that described parasitic PN junction stores;
While data reading, carry out write operation to described parasitic capacitance of PN junction, when sense data is " 0 ", while reading, described bit line earthing potential, discharges to described parasitic capacitance of PN junction, makes described storage node voltage be earth potential; When sense data is " 1 ", while reading, described bit line connects supply voltage, charges to described parasitic capacitance of PN junction, makes described storage node voltage be supply voltage.
10. DRAM cell structure as claimed in claim 6, is characterized in that: when the operating state of described DRAM cell structure is for refreshing:
Described wordline connects high level and makes the conducting of described buoyancy aid NMOS tube;
Described capacitor plate electrode connects plate voltage, and described plate voltage is greater than the cut-in voltage of described parasitic capacitance of PN junction and is less than supply voltage;
Described bit line and pre-charge voltage disconnect and are in floating state, and described bit line and described parasitic PN junction carry out charge-exchange, and when the signal that described parasitic PN junction stores is " 0 ", the current potential of described bit line reduces on the basis of pre-charge voltage; When the signal that described parasitic PN junction stores is " 1 ", the current potential of described bit line raises on the basis of pre-charge voltage;
The data feedback that described parasitic PN junction stores by the potential change of described bit line after sensitive amplifier circuit amplifies is to described bit line; When the Data Data that described parasitic PN junction stores is " 0 ", described bit line earthing potential, discharges to described parasitic capacitance of PN junction, makes described storage node voltage be earth potential; When the Data Data that described parasitic PN junction stores is " 1 ", described bit line connects supply voltage, charges to described parasitic capacitance of PN junction, makes described storage node voltage be supply voltage.
11. DRAM cell structures as claimed in claim 9, it is characterized in that: the value that when size of described plate voltage and described pre-charge voltage is configured such that and reads " 0 ", the current potential of described bit line reduces on the basis of pre-charge voltage and read " 1 " time described bit line the difference of value that raises on the basis of pre-charge voltage of current potential reduce, this difference is the smaller the better.
12. DRAM cell structures as claimed in claim 11, is characterized in that: described pre-charge voltage be described plate voltage and described supply voltage and half.
13. DRAM cell structures as described in claim 11 or 12, is characterized in that: described plate voltage is 1V.
14. DRAM cell structures as claimed in claim 6, is characterized in that: described DRAM cell structure writing, to read or refresh operation completes and all reverts to stand-by operation state.
15. DRAM cell structures as claimed in claim 1, is characterized in that: the top-layer semiconductor of described SOI substrate is top layer silicon, for burying oxide layer bottom described top layer silicon, described in bury bottom oxide layer as at the bottom of backing.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112542518A (en) * 2019-09-20 2021-03-23 长鑫存储技术有限公司 Semiconductor structure and capacitance detection method thereof
WO2023245759A1 (en) * 2022-06-24 2023-12-28 长鑫存储技术有限公司 Semiconductor structure and method for forming same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070230234A1 (en) * 2000-08-17 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers
CN101533860A (en) * 2008-03-13 2009-09-16 海力士半导体有限公司 Semiconductor device and method for manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070230234A1 (en) * 2000-08-17 2007-10-04 Kabushiki Kaisha Toshiba Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers
CN101533860A (en) * 2008-03-13 2009-09-16 海力士半导体有限公司 Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112542518A (en) * 2019-09-20 2021-03-23 长鑫存储技术有限公司 Semiconductor structure and capacitance detection method thereof
WO2023245759A1 (en) * 2022-06-24 2023-12-28 长鑫存储技术有限公司 Semiconductor structure and method for forming same

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