CN105405766A - Method of forming source drain area epitaxial Ge Si uniform profile - Google Patents
Method of forming source drain area epitaxial Ge Si uniform profile Download PDFInfo
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- CN105405766A CN105405766A CN201510716917.6A CN201510716917A CN105405766A CN 105405766 A CN105405766 A CN 105405766A CN 201510716917 A CN201510716917 A CN 201510716917A CN 105405766 A CN105405766 A CN 105405766A
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 25
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 63
- 239000002210 silicon-based material Substances 0.000 claims description 57
- 239000013078 crystal Substances 0.000 claims description 30
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 230000001413 cellular effect Effects 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 6
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000000347 anisotropic wet etching Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000008859 change Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000006835 compression Effects 0.000 description 3
- 238000007906 compression Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910021334 nickel silicide Inorganic materials 0.000 description 3
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 210000000481 breast Anatomy 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 210000005056 cell body Anatomy 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention mainly relates to a method of forming a source drain area epitaxial Ge Si uniform profile. The method comprises the following steps: a gate structure is prepared on a substrate; the top part of the substrate is etched to form a first groove and a second groove to enable the gate structure to be arranged above the area between the first groove and the second groove of the substrate; side walls of the first groove and the second groove are etched until inward sunken grooves are formed on the side walls of the grooves; the side walls with the grooves of the first groove and the second groove are etched to increase the rough degree of the side walls; and the first groove and the second groove are filled with Ge Si materials to form a source area and a drain area respectively.
Description
Technical field
The present invention relates generally to semiconductor device, or rather, relate to a kind of with the preparation method of germanium silicon material as the source area of FET device and the semiconductor device of drain region and correspondence thereof, the grid carrying out enhanced field field effect transistor devices by this controls and current driving ability.
Background technology
Semiconductor integrated circuit industry experiencings and increases fast, allow the quantity of total device on every chip unit area constantly increase during high speed development and become possibility, but the physical dimension of device cell itself constantly reduces, being reduced to raising productivity effect and reducing costs of this size provides benefit, but synchronously also allows the processing of chip and manufacture be tending towards complicated.Such as, along with mos field effect transistor reduces size by technology node, occur that the source area that strains and drain region are increasing the mobility of charge carrier, realize the performance improvement of device.The measure of stress makes lattice deformability or the strain of semiconductor, affects band arrangement and the charge transmission of semiconductor.There is utilizing germanium silicon material although current as the drain region of strain and source area to be applicable to the improvement of device performance, the effect improved does not make us being satisfied with completely.In the detailed description follow-up by the present invention and appended claim, in conjunction with the present invention along with graphic and prior art basis on, the characteristic sum scheme that the present invention discloses will become clear.
Summary of the invention
In certain embodiments, the present invention relates to a kind of method forming source-drain area epitaxial Germanium silicon uniform profile, comprise the following steps: step S1: pre-prepared grid structure on one substrate; Step S2: form first, second groove at the top etch of substrate, makes grid structure be arranged in above the region of substrate between first, second groove; Step S3: etch first, second groove straight wall separately to forming the groove caved inward on their sidewall; Step S4: etch first, second groove and respectively carry the sidewall of groove to increase the degree of roughness of sidewall; Step S5: fill germanium silicon material to form drain region and source area respectively in first, second groove.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, in step s 2, forms first, second groove with the sidewall profile that be rendered as vertical plane mutually orthogonal with substrate place plane.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, in step s3, by anisotropic wet etching, is etched into the sidewall profile of the Σ type with upper angled face and lower beveled by first, second groove sidewall separately.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, in step s 4 which, by first, second groove of dry etching sidewall separately, the sidewall surfaces respectively carrying groove at first, second groove forms cellular suede structure.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, in step s3, first, second groove separately with upper angled face and lower beveled be <111> crystal face.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, in step s3, the etching gas containing hydrogen chloride is adopted to etch first, second groove inner wall surface separately, and the condition of carrying out dry etching meets: temperature controlled within the scope of 550 ~ 750 DEG C, pressure within the scope of 10 ~ 700torr, gas flow within the scope of 70 ~ 300sccm and etch period within the scope of 3 ~ 120s.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, in step s 5, comprises following point/sub-step: sub-step S5.1: the bottom of first, second groove and sidewall epitaxial growth resilient coating (Bufferlayer); And step S5.2: at first, second trench interiors epitaxial growth Ge silicon materials (Bulklayer); Step S5.3: germanium silicon material upper surface epitaxial growth silicon materials (Silicon-Caplayer) in first, second groove;
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, the resilient coating prepared in step S5.1 is an inculating crystal layer of low doping concentration germanium silicon, and its doping content is lower than the concentration of the germanium silicon material prepared in step S5.2, and the thickness of inculating crystal layer exists
scope in.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, in step S5.3 before epitaxial growth silicon materials, first etch the upper surface of germanium silicon material to form cellular suede structure at the upper surface of germanium silicon material, and then at suede structure Epitaxial growth silicon materials; The etching gas containing hydrogen chloride is wherein adopted to etch the upper surface of germanium silicon material, and the condition of carrying out etch process meets: temperature controlled within the scope of 550 ~ 750 DEG C, pressure controls within the scope of 10 ~ 700torr, and gas flow controls within the scope of 70 ~ 300sccm and etch period controls within the scope of 3 ~ 120s.
The method of above-mentioned formation source-drain area epitaxial Germanium silicon uniform profile, wherein exists at the thickness of this germanium silicon material upper surface epitaxially grown one deck silicon materials (Silicon-Caplayer) layer again
scope in.
Accompanying drawing explanation
Read following detailed description also with reference to after the following drawings, Characteristics and advantages of the present invention will be apparent:
Fig. 1 is presented in base substrate and has prepared fleet plough groove isolation structure STI and grid structure.
Fig. 2 is presented at substrate top and forms the U-shaped groove being positioned at grid mechanism both sides.
The sidewall of U-shaped groove is etched thus U-shaped groove is changing into Σ type groove by Fig. 3 display.
Suede structure is made on the surface that Fig. 4 shows the appropriate etching gas in-situ etch Σ type groove of use.
Fig. 5 is presented at superficial growth one deck resilient coating of Σ type groove.
Fig. 6 is presented in groove and continues to fill germanium silicon material.
The upper surface of the germanium silicon material that Fig. 7 shows in use etching gas in-situ etch Σ type groove makes suede structure.
Embodiment
Below in conjunction with each embodiment; clear complete elaboration is carried out to technical scheme of the present invention; but described embodiment is only that the present invention is with being described herein the embodiment that embodiment used and not all are described; based on these embodiments, those skilled in the art belongs to protection scope of the present invention not making the scheme obtained under the prerequisite of creative work.
See Fig. 1, a substrate 100 of such as silicon substrate or SOI substrate or any equivalents is provided, conveniently technological process, be formed with fleet plough groove isolation structure 103 (STI) to be used in substrate 100, define the active area of one or more region as field-effect transistor at the top of substrate 100, and preparation has grid structure on the end face or upper surface of substrate 100, this grid structure comprises the gate insulator 101 of isolation of can insulating and the gate electrode 102 of conduction.And gate insulator 101 can be independent one deck also can be the composite bed that different materials superposition is formed, same gate electrode 102 can be independent one deck also can be the composite bed that different materials superposition is formed.
See Fig. 2, etch at the top of substrate 100, preparation forms the groove being positioned at grid structure both sides, the first groove 104a such as shown in figure and the second groove 104b, it should be noted that, now the pattern of grid structure side grooves is U-shaped groove, and this also means that the pattern of the first groove 104a and the second groove 104b sidewall is separately plane, and their sidewall is substantially vertical with the plane at substrate 100 place.Wherein grid structure is above the region of substrate 100 between the first groove 104a and the second groove 104b, limit the position relationship of grid structure and the first groove 104a and the second groove 104b, because extended meeting is as source area or drain region after the packing material in the first groove 104a and the second groove 104b, and the region of substrate 100 between source area and drain region then can form inversion layer as channel region and set up the passage of carrier mobility, whether grid structure is then used for controlling the formation of channel region.
See Fig. 3, implement etching to the vertical sidewall that the first groove 104a and the second groove 104b comes out, destroy the vertical profile of its sidewall, etching mode here emphasizes it is anisotropic etch.Such as via wet etching, make the first groove 104a and the second groove 104b finally define the Σ type groove be rendered as with upper angled face 104-1 and lower beveled 104-2, and be no longer the U-shaped groove with vertical sidewall pattern mentioned above.Now the inside lateral recesses of comparatively mid portion of the first groove 104a and the second groove 104b sidewall in the vertical direction separately obtains the darkest, and upper angled face 104-1 progressively reduces from the lateral recesses degree to top bottom it or shoals, and lower beveled 104-2 progressively reduces from the lateral recesses degree of its top-to-bottom or shoals.In other words, substrate 100 is positioned at the region (being also namely clamped in the region between the first groove 104a and the second groove 104b) immediately below grid structure, the width being now rendered as top and bottom is greater than the hourglass shaped structure of pars intermedia width, intermediate portion is continuous progressively to increase the mode of width and top area and bottom section respectively up and down, because the sidewall of these hourglass shaped structure both sides defines the groove of transverse recess to the inside, exactly because the existence of groove, the sidewall of hourglass shaped structure just has opposed vertical direction and presents the upper angled face 104-1 for sloped sidewall and the lower beveled 104-2 for sloped sidewall.In an optional embodiment, for example substrate 100 has <100> crystal face, its end face is presented as the crystal face in <100> crystal orientation, then upper angled face 104-1 and lower beveled 104-2 <111> crystal face often.One of problem is, relative to other crystal face (such as the first groove 104a and the second groove 104b bottom surface separately), the speed that germanium and silicon epitaxial inculating crystal layer (seed/crystal layer) on <111> crystal face grows is slower, cause inculating crystal layer less at <111> crystal face place growth thickness, and the inculating crystal layer growth rate of other crystal face is relatively very fast and one-tenth-value thickness 1/10 is also larger.In order to avoid because the inconsistent doubt brought of term, notice that so-called inculating crystal layer has multiple address, such as resilient coating (Bufferlayer), available germanium silicon material or silicon materials etc. here.Inculating crystal layer variable thickness causes/unevenly easily bring out a negative phenomena: and its is used for cushioning the change in concentration of this Ge element material originally, and effect is very limited faster, cause further occurring some such as Stackingfault dislocation defects in germanium silicon body layer (the germanium silicon material Bulklayer also namely hereinafter recorded), thus formation stress relaxation, this can worsen the performance of transistor device.
See Fig. 4, the present invention advocates that etching first groove 104a and the second groove 104b respectively carries the script sidewall comparatively glossily of transverse concave groove, with the degree of roughness of the upper angled face 104-1 and lower beveled 104-2 that increase sidewall.Concrete optional measure such as, the first groove 104a and the respective sidewall of the second groove 104 is etched by dry etching DRYETCH method, the sidewall surfaces respectively carrying groove at the first groove 104a and the second groove 104 forms cellular suede structure, the present invention advocates to adopt and etches the first groove 104a and the respective inner wall surface of the second groove 104 containing the etching gas of hydrogen chloride HCI, and the temperature of carrying out etching controls within the scope of about 550 ~ 750 DEG C, pressure controls within the scope of about 10 ~ 700torr, gas flow controls within the scope of about 70 ~ 300sccm and etch period controls within the scope of about 3 ~ 120s.Although also namely the first groove 104a and the respective sidewall of the second groove 104 with upper angled face 104-1 and lower beveled 104-2 be originally <111> crystal face, but once be formed after cellular suede structure makes their roughening on the surface of upper angled face 104-1 and lower beveled 104-2, again as shown in Figure 5, when the stage at the first groove 104a and the respective bottom of the second groove 104 and a sidewall epitaxial growth resilient coating (or inculating crystal layer) 105, the thickness of resilient coating 105 is just comparatively even, that is, the one-tenth-value thickness 1/10 covering the resilient coating 105 on upper angled face 104-1 and lower beveled 104-2 is basically identical with the one-tenth-value thickness 1/10 covering channel bottom.The doping content of resilient coating 105 is very low, the change in concentration of main buffering germanium, and be such as the plurality of optional mode such as the germanium silicon material of low concentration doping or intrinsic silicon, its final thickness is greatly in the scope of 10 ~ 200 dusts.Resilient coating 105 ensure that the protection of the epitaxially grown interface of the follow-up germanium silicon material 106 as strained layer, and for the germanium silicon material 106 ensureing device quality, the interface of free of contamination perfect crystallization is necessary.
See Fig. 6, after the first groove 104a and the respective sidewall of the second groove 104 and bottom cover thinner resilient coating 105 according to the mode introduced above, the centre of the first groove 104a and the second groove 104 remains cavity or the cell body of hollow, so continue in figure 6 to fill among germanium silicon material 106 to the first groove 104a and the second groove 104 to form drain region and source area respectively, notice that so-called germanium silicon material 106 also has multiple address here, such as germanium silicon body layer Bulklayer etc.Thus by this way, we increase the device performance of MOSFET by the mobility that germanium silicon material SiGe improves raceway groove carriers, such as, mainly have employed the HKMG technology of source-drain area strained silicon technology and high-dielectric constant metal grid pole from the mainstream technology of 40nm node and following critical size.In strained silicon technology, source-drain area all adopts epitaxial growth, by lattice parameter difference introduce stress to raceway groove place thus raising carrier mobility.Under the prerequisite that stress relaxation does not occur, germanium concentration is higher, and the compression of introducing is larger.Along with device performance improves, require to introduce larger compression to raceway groove place.The present invention is except the method adopting Ge element concentration to increase, in source-drain area groove shape, also make some change, advocate to change from U-shaped groove to Σ type groove, because the drift angle (being also the bosom of the depression lateral recesses on trenched side-wall) of Σ type groove can shorten channel distance, and Σ type groove has larger volume, the mobility that more epitaxial Germanium silicon materials improve charge carrier further can be filled.In outgrowth process, change gradually if control Ge element component in germanium silicon material 106, its energy gap is also stepping.
See Fig. 7, also to need on the first groove 104a and the second groove 104 separately inner germanium silicon material 106 of filling epitaxial growth one deck silicon materials 107 again.In order to avoid because the inconsistent doubt brought of term, notice that so-called silicon materials 107 can also be referred to as cap (Caplayer) here.Also namely silicon materials 107 growth rate on the <111> crystal face of germanium silicon material 106 is slower equally for silicon cap layer, if when the nickel silicide forming alloy again on silicon materials 107 forms ohmic contact to reduce contact resistance, if silicon materials 107 variable thickness causes and causes nickel silicide growth thickness uneven, the <111> crystal face of the germanium silicon material 106 of high concentration may be caused also cannot to be that silicon materials 10 cover by silicon cap layer, contact resistance significantly increases, even STI edge contacting metal cannot be connected with source-drain area and affect yield.In order to overcome this doubt, before epitaxial growth silicon materials 107, first etch the upper surface of germanium silicon material 106, so that we can form cellular suede structure at the upper surface of germanium silicon material 106, and then epitaxial growth silicon materials 107 are carried out on this suede structure, the problem of silicon materials 107 uneven thickness before mentioned can be solved.The etching gas containing hydrogen chloride is wherein adopted to etch the exposed upper surface of germanium silicon material 106, and the technique carrying out etching meets: temperature controls within the scope of about 550 ~ 750 DEG C, pressure controls within the scope of about 10 ~ 700torr, the flow control of whole etching gas is within the scope of about 70 ~ 300sccm, and the time controling of etching is in the scope of 3 ~ 120s.The thickness of the epitaxially grown silicon materials 107 of germanium silicon material 106 upper surface finally controls in the scope of 75 ~ 300 dusts.
In sum, the invention provides a kind of method forming source-drain area epitaxial Germanium silicon non-uniform topographical, before <111> crystal face carries out epitaxial growth, use appropriate etching gas HCI original position etching <111> crystal face, its surface is made to become roughening, for the forming core of the germanium silicon material of epitaxial growth on <111> crystal face provides condition, promote the epitaxial growth of <111> crystal face, and reduce the difference of growth rate on <111> crystal face and other crystal face simultaneously, thus formation non-uniform topographical.The Seed Layer of non-uniform topographical can realize epitaxial Germanium silicon volume maximization, strengthens raceway groove compression.The silicon cap layer of non-uniform topographical can improve the uniformity of nickel silicide, reduces contact resistance, can increase the contact probability of STI edge metal in addition, improves yield.
Above, by illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. form a method for source-drain area epitaxial Germanium silicon uniform profile, it is characterized in that, comprise the following steps:
S1: pre-prepared grid structure on one substrate;
S2: form first, second groove at the top etch of substrate, makes grid structure be arranged in above the region of substrate between first, second groove;
S3: etch first, second groove straight wall separately to forming the groove caved inward on their sidewall;
S4: etch first, second groove and respectively carry the sidewall of groove to increase the degree of roughness of sidewall;
S5: fill germanium silicon material to form drain region and source area respectively in first, second groove.
2. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 1, is characterized in that, in step s 2, forms first, second groove and is rendered as perpendicular plane sidewall profile with substrate place plane.
3. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 1, it is characterized in that, in step s3, by anisotropic wet etching, first, second groove sidewall is separately etched into the sidewall profile of the Σ type with upper angled face and lower beveled.
4. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 1, it is characterized in that, in step s 4 which, by first, second groove of dry etching sidewall separately, the sidewall surfaces respectively carrying groove at first, second groove forms cellular suede structure.
5. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 3, it is characterized in that, in step s3, first, second groove separately sidewall with upper angled face and lower beveled be <111> crystal face.
6. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 4, it is characterized in that, the etching gas containing hydrogen chloride is adopted to etch first, second groove inner wall surface separately in step s3, and the temperature of carrying out etching is within the scope of 550 ~ 750 DEG C, pressure within the scope of 10 ~ 700torr, gas flow within the scope of 70 ~ 300sccm and etch period within the scope of 3 ~ 120s.
7. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 1, is characterized in that, in step s 5, comprise the following steps:
S5.1: at the bottom of first, second groove and sidewall epitaxial growth resilient coating;
S5.2: at first, second trench interiors epitaxial growth Ge silicon materials;
S5.3: the germanium silicon material upper surface epitaxial growth silicon materials in first, second groove.
8. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 7, it is characterized in that, the resilient coating prepared in step S5.1 is an inculating crystal layer of low doping concentration germanium silicon, its doping content is lower than the concentration of the germanium silicon material prepared in step S5.2, and the thickness of inculating crystal layer exists
scope in.
9. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 7, it is characterized in that, in step S5.3 before epitaxial growth silicon materials, first etch the upper surface of germanium silicon material to form cellular suede structure at the upper surface of germanium silicon material, and then at suede structure Epitaxial growth silicon materials;
The etching gas containing hydrogen chloride is wherein adopted to etch the upper surface of germanium silicon material, and carry out the temperature of etch process within the scope of 550 ~ 750 DEG C, pressure within the scope of 10 ~ 700torr, gas flow within the scope of 70 ~ 300sccm and etch period within the scope of 3 ~ 120s.
10. the method for formation source-drain area epitaxial Germanium silicon uniform profile according to claim 7, it is characterized in that, the thickness of the epitaxially grown silicon materials of germanium silicon material upper surface exists
scope in.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108511463A (en) * | 2018-03-30 | 2018-09-07 | 武汉华星光电半导体显示技术有限公司 | Array substrate and its manufacturing method |
| CN109065624A (en) * | 2018-07-13 | 2018-12-21 | 上海华力集成电路制造有限公司 | The manufacturing method of MOS transistor with the leakage of germanium silicon source |
| CN111403274A (en) * | 2020-04-10 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Method for increasing surface area of silicon groove |
| CN111489971A (en) * | 2019-01-28 | 2020-08-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112349738A (en) * | 2020-10-27 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device, forming method thereof and image sensor |
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| CN108511463A (en) * | 2018-03-30 | 2018-09-07 | 武汉华星光电半导体显示技术有限公司 | Array substrate and its manufacturing method |
| CN109065624A (en) * | 2018-07-13 | 2018-12-21 | 上海华力集成电路制造有限公司 | The manufacturing method of MOS transistor with the leakage of germanium silicon source |
| CN111489971A (en) * | 2019-01-28 | 2020-08-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111403274A (en) * | 2020-04-10 | 2020-07-10 | 上海华虹宏力半导体制造有限公司 | Method for increasing surface area of silicon groove |
| CN112349738A (en) * | 2020-10-27 | 2021-02-09 | 武汉新芯集成电路制造有限公司 | Semiconductor device, forming method thereof and image sensor |
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| CN105405766B (en) | 2018-09-04 |
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