CN105390082B

CN105390082B - Display device and method of driving display panel

Info

Publication number: CN105390082B
Application number: CN201510526126.7A
Authority: CN
Inventors: 李京远; 朴修亨; 朴文山; 高俊哲; 裴玗美
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2014-08-27
Filing date: 2015-08-25
Publication date: 2021-02-02
Anticipated expiration: 2035-08-25
Also published as: KR102413158B1; US20180040289A1; US20160063914A1; CN105390082A; KR102339039B1; US10438556B2; KR20160025675A; US9818364B2; KR20210154782A

Abstract

A display apparatus and a method of driving a display panel are provided, the display apparatus including a timing controller, a data driver, and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of the input image. The timing controller generates a data signal having a first frequency based on input image data having the first frequency. The data driver converts the data signal into a data voltage. The display panel displays an image based on the data voltage.

Description

Display device and method of driving display panel

Technical Field

Exemplary embodiments of the present invention relate to a display device and a method of driving a display panel using the same. More particularly, exemplary embodiments of the present invention relate to a display device having reduced power consumption and a method of driving a display panel using the same.

Background

Methods of minimizing power consumption of information technology ("IT") products, such as desktop personal computers ("PCs") and laptop PCs, have been studied.

In order to minimize power consumption of an IT product including a display panel, power consumption of the display panel may be minimized. When the display panel displays a static or still image, the display panel may be driven at a relatively low frequency, thereby reducing power consumption of the display panel.

Alternatively, when the display panel displays a video or moving image, the display panel is driven at a relatively high frequency. When the display panel is driven at a high frequency, power consumption increases relative to the case of being driven at a low frequency.

Disclosure of Invention

Exemplary embodiments of the present invention provide a display device capable of reducing power consumption of the display device.

Exemplary embodiments of the present invention also provide a method of driving a display panel using the display device.

In an exemplary embodiment of a display apparatus according to the present invention, the display apparatus includes a timing controller, a data driver, and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of the input image. The timing controller generates a data signal having a first frequency based on input image data having the first frequency. The data driver converts the data signal into a data voltage. The display panel displays an image based on the data voltage.

In an exemplary embodiment, the display apparatus may further include a decoder, a memory, and a graphic processing unit. The decoder decodes the input image. The memory stores the decoded input image. The graphic processing unit converts the decoded input image into input image data having a first frequency and outputs the input image data to the timing controller.

In an exemplary embodiment, the input image data may include active periods and blank periods alternating with each other.

In an exemplary embodiment, the intervals between the active periods may be substantially uniform.

In an exemplary embodiment, the length of the active period may be 1/60 seconds. The length of the blank period may be determined as an interval of adjacent active periods.

In an exemplary embodiment, when the first frequency is 30Hz (hertz), the length of the active period may be substantially equal to the length of the blank period.

In an exemplary embodiment, when the first frequency is less than 30Hz (hertz), the length of the active period may be less than the length of the blank period.

In an exemplary embodiment, the timing controller may include a blank power supply control part to turn off the data driver during the blank period.

In an exemplary embodiment, the timing controller may further include a register. The register stores a frame rate of the input image. The blank power source control section may output a blank control signal that changes according to a frame rate of the input image.

In an exemplary embodiment, the data driver may include a power control part, a digital-to-analog conversion part, a buffer part, a first switching part, and a second switching part. The power supply control unit controls the power supply based on a blank control signal determined in accordance with the input image. The digital-to-analog conversion section converts the data signal from a digital type data voltage to an analog type data voltage. The buffer portion buffers a data voltage. The first switching part is turned on during the active period and applies the data voltage to the data line. The second switching part is turned on during the blank period and applies a blank voltage to the data line.

In an exemplary embodiment, the data driver may further include a power switch part. The power switch section turns off the digital-to-analog conversion section and the buffer section during the blank period.

In an exemplary embodiment, the data driver may further include a blank voltage supply part. The blank voltage supply section supplies a blank voltage to the second switching section.

In an exemplary embodiment, the second switching section may include switches in the first and second rows. The switches in the first row are alternately turned on and apply a first blank voltage to the data lines. The switches in the second row are alternately turned on and apply a second blank voltage to the data lines.

In an exemplary embodiment of a method of driving a display panel according to the present invention, the method includes: receiving an input image at a first frequency, the first frequency being substantially equal to a frame rate of the input image; generating a data signal having a first frequency based on input image data having the first frequency; and displaying an image based on the data signal.

In an exemplary embodiment, the method may further include: decoding an input image; storing the decoded input image in a memory; converting the decoded input image into input image data having a first frequency; and outputting the input image data to the timing controller.

In an exemplary embodiment, the timing controller may control the data driver to be turned off during the blank period.

In an exemplary embodiment, the timing controller further includes a register. The register stores a frame rate of the input image.

According to the display device and the method of driving the display panel using the display device, when the display panel displays a video image, the display panel is driven at a frequency equal to a frame rate of an input image, so that power consumption of the display panel can be reduced.

Drawings

The above and other aspects and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

fig. 1 is a block diagram illustrating an exemplary embodiment of a display apparatus according to an exemplary embodiment of the present invention;

FIG. 2 is a block diagram illustrating an exemplary embodiment of the application processor of FIG. 1;

fig. 3 is a block diagram illustrating an exemplary embodiment of the timing controller of fig. 1;

fig. 4 is a conceptual diagram illustrating an exemplary embodiment of signals of the timing controller and the data driver of fig. 1;

FIG. 5 is a block diagram illustrating an exemplary embodiment of the data driver of FIG. 1;

FIG. 6A is a block diagram illustrating an exemplary embodiment of the data driver of FIG. 1 in an active period;

FIG. 6B is a block diagram illustrating an exemplary embodiment of the data driver of FIG. 1 in a blank period;

fig. 7 is a conceptual diagram illustrating an exemplary embodiment of signals of a timing controller and a data driver according to the present invention; and

fig. 8 is a block diagram illustrating an exemplary embodiment of a timing controller according to the present invention.

Detailed Description

While the invention is amenable to various modifications and alternative embodiments, specifics thereof have been shown in the drawings and will be described primarily in the specification. However, the scope of exemplary embodiments of the present invention is not limited to the specific embodiments and should be construed to include all variations, equivalents, and alternatives included in the spirit and scope of the present invention.

Throughout the specification, when an element is referred to as being "connected" to another element, the element is "directly connected" to the other element or is "electrically connected" to the other element with one or more intervening elements interposed therebetween. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a "first element" discussed below could be termed a "second element" or a "third element," and similarly termed a "second element" and a "third element," without departing from the teachings herein.

Spatially relative terms, such as "below … …," "below … …," "below," "above … …," and "above," may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, in an exemplary embodiment, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation above … … and below … …. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, "about" or "approximately" includes the stated value and is meant to be within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account measurement issues and errors associated with measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" may mean within one or more standard deviations or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Unless explicitly defined as such herein, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. In addition, the sharp corners shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

Hereinafter, the present invention according to exemplary embodiments will be explained in further detail with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating an exemplary embodiment of a display apparatus according to the present invention.

Referring to fig. 1, the display device includes a display panel 100, a panel driver (200, 300, 400, 500), and an application processor 600. The panel driver includes a timing controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

The display panel 100 includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels connected to the gate lines GL and the data lines DL. The gate line GL extends in a first direction D1, and the data line DL extends in a second direction D2 crossing the first direction D1.

Each pixel includes a switching element (not shown), a liquid crystal capacitor (not shown), and a storage capacitor (not shown). The liquid crystal capacitor and the storage capacitor are electrically connected to the switching element. The pixels may be arranged in a matrix form.

The timing controller 200 receives input image data RGB and input control signals CONT from the application processor 600. In an exemplary embodiment, the input image data may include red image data ("R"), green image data ("G"), and blue image data ("B"). In an exemplary embodiment, the input control signals CONT may include a master clock signal and a data enable signal. In an exemplary embodiment, the input control signals CONT may further include a vertical synchronization signal and a horizontal synchronization signal.

The timing controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a DATA signal DATA based on the input image DATA RGB and the input control signals CONT.

The timing controller 200 generates a first control signal CONT1 controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the first control signal CONT1 to the gate driver 300. In an exemplary embodiment, the first control signals CONT1 may further include a vertical start signal and a gate clock signal.

The timing controller 200 generates a second control signal CONT2 controlling the operation of the data driver 500 based on the input control signal CONT and outputs the second control signal CONT2 to the data driver 500. In an exemplary embodiment, the second control signals CONT2 may include a horizontal start signal and a load signal.

The timing controller 200 generates DATA signals DATA based on input image DATA RGB. The timing controller 200 outputs the DATA signal DATA to the DATA driver 500.

In an exemplary embodiment, the timing controller 200 may control the operation of the gate driver 300 and the operation of the data driver 500 according to an active period of the input image data RGB and a blank period of the input image data RGB.

During the active period, the timing controller 200 controls the gate driver 300 and the data driver 500 to normally operate.

During the blank period, the timing controller 200 may not output the first control signal CONT1 to the gate driver 300. For example, the timing controller 200 may not output the vertical start signal to the gate driver 300 during the blank period.

In addition, the timing controller 200 may not output the second control signal CONT2 and the DATA signal DATA to the DATA driver 500 during the blank period. For example, the timing controller 200 may not output the horizontal start signal and the load signal to the data driver 500 during the blank period.

In an exemplary embodiment, the timing controller 200 may control power (power) to the data driver 500. For example, the timing controller 200 may turn off the operation of the data driver 500 during a blank period of the input image data RGB. The timing controller 200 may output a blank control signal for controlling power to the data driver 500.

The timing controller 200 generates a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

An exemplary embodiment of the structure and operation of the timing controller 200 is explained in further detail below with reference to fig. 3.

The gate driver 300 generates a gate signal driving the gate line GL in response to the first control signal CONT1 received from the timing controller 200. The gate driver 300 sequentially outputs gate signals to the gate lines GL.

In an exemplary embodiment, the gate driver 300 may be directly mounted on the display panel 100, or may be connected to the display panel 100 as a tape carrier package ("TCP") type. Alternatively, in another exemplary embodiment, the gate driver 300 may be integrated on the display panel 100.

The gamma reference voltage generator 400 generates the gamma reference voltage VGREF in response to the third control signal CONT3 received from the timing controller 200. The gamma reference voltage generator 400 supplies the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the DATA signal DATA.

In an exemplary embodiment, the gamma reference voltage generator 400 may be provided in the data driver 500. Alternatively, in another exemplary embodiment, the gamma reference voltage generator 400 may be provided in the timing controller 200.

The DATA driver 500 receives the second control signal CONT2 and the DATA signal DATA from the timing controller 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generator 400. The DATA driver 500 converts the DATA signal DATA into an analog DATA voltage using the gamma reference voltage VGREF. The data driver 500 outputs a data voltage to the data line DL.

The data driver 500 outputs a data voltage to the data lines DL during an active period of the input image data RGB. The data driver 500 outputs a blank voltage to the data lines DL during a blank period of the input image data RGB.

In an exemplary embodiment, the data driver 500 may be directly mounted on the display panel 100, or alternatively, may be connected to the display panel 100 in a TCP type. Alternatively, in another exemplary embodiment, the data driver 500 may be integrated on the display panel 100.

An exemplary embodiment of the structure and operation of the data driver 500 is explained in further detail below with reference to fig. 5, 6A, and 6B.

The application processor 600 decodes an input image and converts the decoded input image into input image data RGB. The application processor 600 outputs the input image data RGB to the timing controller 200.

The application processor 600 outputs the input control signal CONT to the timing controller 200.

An exemplary embodiment of the structure and operation of the application processor 600 is explained in further detail below with reference to fig. 2.

Fig. 2 is a block diagram illustrating an exemplary embodiment of the application processor 600 of fig. 1. Fig. 3 is a block diagram illustrating an exemplary embodiment of the timing controller 200 of fig. 1. Fig. 4 is a conceptual diagram illustrating an exemplary embodiment of signals of the timing controller 200 and the data driver 500 of fig. 1.

Referring to fig. 1, 2 and 4, the application processor 600 includes a decoder 620 and a graphic processing unit 640 and a memory 660.

The decoder 620 decodes the input image. The input image has a frame rate. The frame rate represents the refresh rate of the video image. That is, the frame rate (also known as the frame rate and frames per second ("fps")) is the frequency (rate) at which the imaging device produces unique sequential images called frames. The frame rate is defined as the number of frames during a preset period of time. For example, the frame rate of the input images may be 30fps (frames per second). For example, the frame rate of the input image may be 24 fps.

The decoder 620 sends the decoded input image DI to the memory 660. The decoded input image DI is stored in the memory 660.

The graphic processing unit 640 converts the decoded input image DI stored in the memory 660 into input image data RGB having a first frequency.

The graphic processing unit 640 controls writing of the decoded input image DI to the memory 660 and reading of the decoded input image DI from the memory 660 at the first frequency.

Referring to fig. 4, the input image data RGB includes active periods a1, a2, A3, and a4 and blank periods B1, B2, B3, and B4 alternating with each other. In an exemplary embodiment, the intervals between the active periods a1, a2, A3, and a4 may be substantially uniform (homogeneous). The length of the blank period may be defined as an interval between adjacent active periods.

The length of the active period may be determined based on a normal driving frequency of the display panel 100. For example, in an exemplary embodiment, when the normal driving frequency of the display panel 100 is 60Hz (hertz), the length of the active period may be determined to be 1/60 seconds of 1/(normal driving frequency). Alternatively, in an exemplary embodiment, the length of the active period may be slightly shorter than 1/(the normal driving frequency).

Referring to fig. 3, the timing controller 200 includes a data control part 220 and a blank power control part 240.

The DATA control part 220 receives the input image DATA RGB at the first frequency and generates the DATA signal DATA having the first frequency. The data control part 220 outputs a data signal having a first frequency to the data driver 500.

The DATA control part 220 compensates the gray DATA of the input image DATA RGB and rearranges the input image DATA RGB to generate the DATA signal DATA to correspond to the DATA type of the DATA driver 500. In an exemplary embodiment, the DATA signal DATA may be a digital type signal.

For example, in an alternative exemplary embodiment, the data control part 220 may include an adaptive color correction part (not shown) and a dynamic capacitance compensation part (not shown).

The adaptive color correction section receives gradation data of input image data RGB and runs adaptive color correction ("ACC"). The adaptive color correcting part may compensate the gray data using the gamma curve.

The dynamic capacitance compensation part performs dynamic capacitance compensation ("DCC") for compensating gray data of the current frame data using the previous frame data and the current frame data.

The blank power control part 240 controls the data driver 500 to be turned off corresponding to a blank period of the input image data RGB. The blank power control part 240 outputs a blank control signal BS to control when the data driver 500 is turned on and off.

Although not shown in the drawings, in another exemplary embodiment, the timing controller 200 may further include a low frequency driving part.

The low frequency driving part (not shown) receives input image data RGB. The low frequency driving section determines a driving frequency of the display panel 100 based on the input image data RGB. For example, when the input image data RGB is a still or still image, the low frequency driving part drives the display panel 100 at a relatively low frequency. For example, in an exemplary embodiment, the relatively low frequency may be about 1 Hz. For example, when the input image data RGB is a video or moving image, the low frequency driving section drives the display panel 100 at a relatively high frequency. For example, in an exemplary embodiment, the relatively high frequency may be the first frequency.

In fig. 4, for example, the frame rate of the input image is 30 fps. When the frame rate of the input images is 30fps, the input images include thirty-frame-per-second images.

The input image DI decoded by the decoder 620 is stored in the memory 660.

The input image data RGB has a first frequency substantially equal to the frame rate (30fps) of the input image. When the frame rate of the input image is 30fps, the first frequency of the input image data RGB may be 30 Hz.

The input image data RGB includes thirty frames per second of images and thirty active periods per second. In addition, the input image data RGB includes thirty blank periods per second.

The length of the active period of the input image data RGB may be determined based on a normal driving frequency of the display panel 100. For example, in an exemplary embodiment, when the normal driving frequency of the display panel 100 is 60Hz, the length of the active period may be determined to be 1/60 seconds. Alternatively, in another exemplary embodiment, when the normal driving frequency of the display panel 100 is 60Hz, the length of the active period may be slightly shorter than 1/60 seconds.

For example, when the first frequency is 30Hz, the length of the active period may be substantially the same as the length of the blank period.

In fig. 4, the input image data RGB includes a first active period a1 during which the first input image I1 is displayed and a first blank period B1 following the first active period a 1. The length of the first activity period a1 is about 16.67 ms. The length of the first blank period B1 is about 16.67 ms.

The input image data RGB includes a second active period a2 following the first blank period B1 and a second blank period B2 following the second active period a 2. During the second active period a2, a second input image I2 is displayed. The length of the second activity period a2 is about 16.67 ms. The length of the second blank period B2 is about 16.67 ms.

The input image data RGB includes a third active period A3 succeeding the second blank period B2 and a third blank period B3 succeeding the third active period A3. During the third active period a3, a third input image I3 is displayed. The length of the third activity period a3 is about 16.67 ms. The length of the third blank period B3 is about 16.67 ms.

The blank power control part 240 controls the data driver 500 to be turned off during the blank period. For example, in an exemplary embodiment, the second analog power supply voltage AVDD2 transmitted to the data driver 500 may have an ON level during an active period and an OFF level during a blank period.

Fig. 5 is a block diagram illustrating an exemplary embodiment of the data driver 500 of fig. 1. Fig. 6A is a block diagram illustrating an exemplary embodiment of the data driver 500 of fig. 1 in an active period. Fig. 6B is a block diagram illustrating an exemplary embodiment of the data driver 500 of fig. 1 in a blank period.

Referring to fig. 1 to 6B, the data driver 500 includes a latch unit 510, a first multiplexing unit 520, a digital-to-analog conversion unit 530, a buffer unit 540, a second multiplexing unit 550, a first switching unit 560, a second switching unit 570, a power control unit 580, a power switch unit 590, and a blank voltage supply unit 595.

The latch unit 510 receives the DATA signal DATA and the second control signal CONT 2. The latch section 510 temporarily stores the DATA signal DATA and outputs the DATA signal DATA to the digital-to-analog conversion section 530 through the first multiplexing section 520. In an exemplary embodiment, the digital power supply voltage DVDD may be applied to the latch part 510 and the first multiplexing part 520.

The digital-to-analog conversion part 530 generates an analog DATA voltage based on the digital DATA signal DATA and the gamma reference voltage VGREF. The digital-to-analog conversion part 530 outputs the data voltage to the buffer part 540.

The digital-to-analog conversion part 530 may include a plurality of digital-to-analog converters DAC1 to DAC 6. Although six analog digital-to-analog converters are shown in fig. 5, 6A, and 6B for ease of explanation, the present invention is not limited to any number of digital-to-analog converters. For example, the digital-to-analog converting part 530 may include as many digital-to-analog converters as necessary in order to correspond to the number of the data lines DL.

The buffer 540 buffers the data voltage. The buffer 540 compensates the data voltage to have a uniform level. The buffer 540 outputs the compensated data voltage to the data line DL through the second multiplexing unit 550, the first switching unit 560, and the second switching unit 570.

The buffer 540 in an exemplary embodiment may include a plurality of buffers B1 through B6. For example, the first, third, and fifth buffers B1, B3, and B5 may buffer the data voltage having the first polarity. The second, fourth, and sixth buffers B2, B4, and B6 may buffer data voltages having a second polarity opposite to the first polarity.

The first multiplexer 520 and the second multiplexer 550 operate as path selectors. For example, when the data voltages having the first polarity are output to the odd data lines and the data voltages having the second polarity are output to the even data lines during the first frame, the first multiplexer MUX11 of the first multiplexing section 520 and the second multiplexer MUX12 of the second multiplexing section 550 transmit the first data voltages of the first polarity to the first data lines through the first digital-to-analog converter DAC1 and the first buffer B1, and transmit the second data voltages of the second polarity to the second data lines through the second digital-to-analog converter DAC2 and the second buffer B2, respectively.

In contrast, when the data voltages having the second polarity are output to the odd data lines and the data voltages having the first polarity are output to the even data lines during the second frame, the first multiplexer MUX11 of the first multiplexing section 520 and the second multiplexer MUX12 of the second multiplexing section 550 transmit the second data voltages of the first polarity to the second data lines through the first digital-to-analog converter DAC1 and the first buffer B1, and transmit the first data voltages of the second polarity to the first data lines through the second digital-to-analog converter DAC2 and the second buffer B2, respectively.

During the active period of the input image data RGB, the first switching part 560 is turned on to apply the data voltage to the data line DL. In contrast, during the blank period of the input image data RGB, the first switching part 560 is turned off to disconnect the buffer part 540 from the data line DL.

The first switching section 560 includes a plurality of switches S11 to S16. When the switches S11 to S16 of the first switching section 560 are turned on, the buffer section 540 is connected to the data line DL. When the switches S11 to S16 of the first switching section 560 are turned off, the buffer section 540 is disconnected from the data line DL.

Although not shown in the drawings, in an exemplary embodiment, the second multiplexing part 550 may be integrally formed with the first switching part 560 such that the multiplexing operation of the second multiplexing part 550 and the switching operation of the first switching part 560 may be simultaneously operated.

During the blank period of the input image data RGB, the second switching part 570 is turned on to apply a blank voltage to the data lines DL. In contrast, during the active period of the input image data RGB, the second switching part 570 is turned off not to apply the blank voltage to the data lines DL.

The second switching part 570 includes a plurality of switches S21 to S26 in a first row and a plurality of switches S31 to S36 in a second row. In an exemplary embodiment, the switches S21 through S26 in the first row may be alternately turned on while the other switches in the first row are alternately turned off during a blank period of the input image data RGB. In an exemplary embodiment, the switches S31 to S36 (i.e., S32, S34, S36) in the second row may be alternately turned on during a blank period of the input image data RGB. In addition, the switch S21 and the switch S31 connected to the first data line may be alternately turned on (i.e., S21, S23, S25) during a blank period of the input image data RGB. For example, during a blank period of the input image data RGB, the switch S21 may be turned on and the switch S31 may be turned off.

During the first blank period B1 of the input image data RGB, the switches S21 to S26 in the first row may apply the first blank voltage VB1 to the odd-numbered data lines, and the switches S31 to S36 in the second row may apply the second blank voltage VB2 to the even-numbered data lines. For example, in an exemplary embodiment, during the first blank period B1 of the input image data RGB, the first switch S21, the third switch S23, and the fifth switch S25 in the first row may be turned on to apply the first blank voltage VB1 to the odd-numbered data lines, and the second switch S32, the fourth switch S34, and the sixth switch S36 in the second row may be turned on to apply the second blank voltage VB2 to the even-numbered data lines.

In an exemplary embodiment, the first blank voltage VB1 may have a polarity opposite to that of the second blank voltage VB 2. For example, the first blank voltage VB1 may have a positive polarity, and the second blank voltage VB2 may have a negative polarity.

During the second blank period B2 in which the image data RGB is input, when the polarity of the data voltage is inverted with respect to the polarity of the data voltage in the first blank period B1, the switches S21 to S26 in the first row may apply the first blank voltage VB1 to the even-numbered data lines, and the switches S31 to S36 in the second row may apply the second blank voltage VB2 to the odd-numbered data lines. For example, in an exemplary embodiment, during the second blank period B2 of the input image data RGB, the second switch S22, the fourth switch S24, and the sixth switch S26 in the first row may be turned on to apply the first blank voltage VB1 to the even-numbered data lines, and the first switch S31, the third switch S33, and the fifth switch S35 in the second row may be turned on to apply the second blank voltage VB2 to the odd-numbered data lines.

In an exemplary embodiment, the power supply control section 580 controls power (or power supply) of the data driver 500 according to the blank control signal BS. During the active period of the input image data RGB, the power control part 580 may turn on the first switching part 560 and may turn off the second switching part 570. The power control part 580 may turn off the first switching part 560 and may turn on the second switching part 570 during a blank period of the input image data RGB.

In an exemplary embodiment, the power supply control section 580 may control the operation of the power supply switching section according to the blank control signal BS. In addition, the power supply control section 580 may control the operation of the gamma reference voltage generator 400 according to the blank control signal BS.

The power switch section 590 turns on or off elements in the data driver 500 according to the control of the power control section 580.

In an alternative exemplary embodiment, the power switch section 590 may turn off the digital-to-analog conversion section 530 and the buffer section 540 during a blank period of the input image data RGB. The power switch section 590 may turn off the gamma reference voltage generator 400, the first multiplexing section 520, and the second multiplexing section 550 during a blank period of the input image data RGB.

The power switch section 590 may turn off the blank voltage supply section 595 during the active period of the input image data RGB.

In the present exemplary embodiment, the first analog power supply voltage AVDD1 and the second analog power supply voltage AVDD2 are applied to the power switch section 590. The first analog supply voltage AVDD1 may be a constant voltage. In contrast, the second analog supply voltage AVDD2 may be a variable. For example, in an exemplary embodiment, the second analog power supply voltage AVDD2 may have a high level (ON level) during an active period of the input image data RGB. In contrast, the second analog power supply voltage AVDD2 may have a low level (OFF level) during the blank period of the input image data RGB. In the present exemplary embodiment, the blank power control operation is performed by the data driver 500, and thus the variable second analog power voltage AVDD2 may be externally supplied to the data driver 500. Therefore, the element that needs to be always turned on is driven by the first analog power supply voltage AVDD 1.

Alternatively, in an exemplary embodiment, only one power supply voltage having a constant voltage is applied to the power switch section 590, and a blank power supply control operation may be performed in the data driver 500.

The blank voltage supply section 595 supplies blank voltages VB1 and VB2 to the second switching section 570. During the blank period of the input image data RGB, blank voltages VB1 and VB2 are applied to the data lines DL through the second switching section 570.

In the present exemplary embodiment, the blank voltages VB1 and VB2 may be determined by one of external blank voltages EVB1 and EVB2 applied from the outside of the data driver 500 and one of internal blank voltages IVB1 and IVB2 generated in the power supply control part 580.

The blank voltages VB1 and VB2 may be determined using an average pixel voltage of pixels of the display panel 100 corresponding to an input image. For example, in an exemplary embodiment, the external blank voltages EVB1 and EVB2 may not vary in real time. The external blank voltages EVB1 and EVB2 may be determined by an average pixel voltage of pixels of the display panel 100 corresponding to a normal image. For example, in an exemplary embodiment, the internal blank voltages IVB1 and IVB2 may vary in real time. The internal blank voltages IVB1 and IVB2 may be determined by an average pixel voltage of pixels of the display panel 100 corresponding to an input image in each frame.

For example, the first blank voltage VB1 may have a first polarity. The second blank voltage VB2 may have a second polarity opposite the first polarity. Accordingly, the first external blank voltage EVB1 may have a first polarity and the second external blank voltage EVB2 may have a second polarity. Accordingly, the first internal blank voltage IVB1 may have a first polarity and the second internal blank voltage IVB2 may have a second polarity.

The blank voltage supply section 595 includes blank digital-to-analog conversion sections BDAC1 and BDAC2, blank buffer sections BB1 and BB2, and blank multiplexing sections BMUX1 and BMUX 2.

The blanking digital to analog converters BDAC1 and BDAC2 include a first blanking digital to analog converter BDAC1 and a second blanking digital to analog converter BDAC 2. The first blank digital-to-analog converter BDAC1 converts the first internal blank voltage IVB1 having a digital type signal received from the power control part 580 into an analog type signal. The second blank digital-to-analog converter BDAC2 converts the second internal blank voltage IVB2 received from the power supply control section 580 from a digital voltage to an analog voltage.

The blank buffers BB1 and BB2 include a first blank buffer BB1 and a second blank buffer BB 2. The first blank buffer BB1 is connected to the first blank digital-to-analog converter BDAC1 to buffer the first internal blank voltage IVB1 converted to an analog voltage. The second blank buffer BB2 is connected to the second blank digital-to-analog converter BDAC2 to buffer the second internal blank voltage IVB2 converted to an analog voltage.

The blank multiplexing sections BMUX1 and BMUX2 include a first blank multiplexer BMUX1 and a second blank multiplexer BMUX2, respectively. The first blank multiplexer BMUX1 is connected to a first external line applying a first external blank voltage EVB1 and a first blank buffer BB1 to selectively output one of the first external blank voltage EVB1 and a first internal blank voltage IVB 1. The second blank multiplexer BMUX2 is connected to a second external line applying a second external blank voltage EVB2 and a second blank buffer BB2 to selectively output one of the second external blank voltage EVB2 and a second internal blank voltage IVB 2.

Unlike the above explanation, in an alternative exemplary embodiment, the blank voltages VB1 and VB2 may be determined only by the internal blank voltages IVB1 and IVB2 generated in the power supply control part 580. The blank voltages VB1 and VB2 may vary in real time based on the input image data RGB. In the present exemplary embodiment, the blank voltage supply section 595 may not include the blank multiplexing sections BMUX1 and BMUX 2.

Unlike the above explanation, in an alternative exemplary embodiment, the blank voltages VB1 and VB2 may be determined only by the external blank voltages EVB1 and EVB2 provided from the outside of the data driver 500. The blank voltages VB1 and VB2 may not change in real time. In the present exemplary embodiment, the data driver 500 may not include the blank voltage provider 595.

Fig. 6A represents an exemplary embodiment of an operation of the data driver 500 during an active period of the input image data RGB. Referring again to fig. 6A, during the active period of the input image data RGB, the latch part 510, the digital-to-analog conversion part 530, and the buffer part 540 are turned on, so that the normal data voltage applied to the data lines DL is generated. In addition, during the active period of the input image data RGB, the first switching part 560 is turned on to supply the normal data voltage to the data line DL.

In contrast, during the active period of the input image data RGB, the blank voltage supply section 595 is turned off, so that the blank voltages VB1 and VB2 are not generated. In addition, during the active period of the input image data RGB, all the switches S21 to S26 and S31 to S36 of the second switching section 570 are turned off, so that the data line DL is not connected to the blank voltage application line.

Fig. 6B represents an exemplary embodiment of an operation of the data driver 500 during a blank period of the input image data RGB. Referring again to fig. 6B, during the blank period of the input image data RGB, the latch part 510, the digital-to-analog conversion part 530, and the buffer part 540 are turned off so that the normal data voltage applied to the data line DL is not generated. In addition, during a blank period of the input image data RGB, the first switching part 560 is turned off so that the data line DL is not connected to the buffer part 540.

In contrast, during the blank period of the input image data RGB, the blank voltage supply section 595 is turned on, so that the blank voltages VB1 and VB2 are supplied to the second switching section 570. In addition, during a blank period of the input image data RGB, the second switching part 570 is turned on to apply blank voltages VB1 and VB2 to the data lines DL.

According to the present exemplary embodiment, when the display apparatus displays a video image, the input image data RGB has a frequency (e.g., 30Hz) equal to a frame rate (e.g., 30fps) of the input image. Accordingly, power consumption for converting an input image having a frame rate (e.g., 30fps) into input image data RGB having frequencies (e.g., 60Hz and 120Hz) higher than the frame rate (e.g., 30fps) can be reduced. In addition, power consumption for displaying images at frequencies (e.g., 60Hz and 120Hz) greater than the frame rate (30fps) of input images can be reduced. In particular, during the blank period of the input image data RGB, the power consumption of the data driver 500 may be significantly reduced by the blank power control method. Accordingly, when the display device displays a video image, power consumption of the display device can be significantly reduced.

Fig. 7 is a conceptual diagram illustrating an exemplary embodiment of signals of the timing controller 200 and the data driver 500 according to the present invention.

The display apparatus according to the present exemplary embodiment is substantially the same as the display apparatus of the previous exemplary embodiment explained with reference to fig. 1 to 6B except that the frame rate of the input image is 24fps instead of 30 fps. Therefore, the same reference numerals will be used to refer to the same or similar components as those described in the previous exemplary embodiment of fig. 1 to 6B, and any repetitive explanation regarding the above elements will be omitted.

Referring to fig. 1 to 3, 5, 6A, 6B, and 7, the display device includes a display panel 100, a panel driver, and an application processor 600. The panel driver includes a timing controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

The application processor 600 includes a decoder 620 and a graphics processing unit 640 and a memory 660.

The decoder 620 decodes the input image. The input image has a frame rate. The decoder 620 sends the decoded input image DI to the memory 660. The input image DI is stored in the memory 660.

The input image data RGB includes active periods a1, a2, A3, and a4 and blank periods B1, B2, B3, and B4 (i.e., a1, B1, a2, B2, A3, B3, a4, B4) alternating with one another. The intervals between the active periods a1, a2, A3, and a4 may be substantially uniform. The length of the blank period may be defined as an interval of adjacent active periods a1, a2, A3, and a 4.

In fig. 7, for example, the frame rate of the input image is 24 fps. When the frame rate of the input images is 24fps, the input images include twenty-four frame images per second.

The input image DI decoded by the decoder 620 is stored in the memory 660.

The input image data RGB has a first frequency substantially equal to the frame rate (24fps) of the input image. When the frame rate of the input image is 24fps, the first frequency of the input image data RGB may be 24 Hz.

The input image data RGB includes twenty-four frames per second of images and twenty-four active periods per second. In addition, the input image data RGB includes twenty-four blank periods per second.

The length of the active period may be determined based on a normal driving frequency of the display panel 100. For example, in an exemplary embodiment, when the normal driving frequency of the display panel 100 is 60Hz, the length of the active period may be determined to be 1/60 seconds. Alternatively, when the normal driving frequency of the display panel 100 is 60Hz, the length of the active period may be slightly shorter than 1/60 seconds.

For example, when the first frequency is less than 30Hz, the length of the active period may be shorter than the length of the blank period. For example, when the first frequency is 24Hz, the length of the active period may be shorter than the length of the blank period.

In fig. 7, the input image data RGB includes a first active period a1 during which the first input image I1 is displayed and a first blank period B1 following the first active period a 1. The length of the first activity period a1 is about 16.67 ms. The length of the first blank period B1 is about 25 ms.

The input image data RGB includes a second active period a2 following the first blank period B1 and a second blank period B2 following the second active period a 2. During the second active period a2, a second input image I2 is displayed. The length of the second activity period a2 is about 16.67 ms. The length of the second blank period B2 is about 25 ms.

The input image data RGB includes a third active period A3 succeeding the second blank period B2 and a third blank period B3 succeeding the third active period A3. During the third active period a3, a third input image I3 is displayed. The length of the third activity period a3 is about 16.67 ms. The length of the third blank period B3 is about 25 ms.

The blank power control part 240 of the timing controller 200 controls the data driver 500 to be turned off during the blank period of the input image data RGB. For example, the second analog power supply voltage AVDD2 transmitted to the data driver 500 may have an ON level during an active period of the input image data RGB and an OFF level during a blank period of the input image data RGB.

According to the present exemplary embodiment, when the display apparatus displays a video image, the input image data RGB has a frequency (for example, 24Hz) equal to a frame rate (for example, 24fps) of the input image. Accordingly, power consumption for converting an input image having a frame rate (e.g., 24fps) into input image data RGB having frequencies (e.g., 60Hz and 120Hz) higher than the frame rate (e.g., 24fps) can be reduced. In addition, power consumption for displaying images at frequencies (e.g., 60Hz and 120Hz) greater than the frame rate of the input images (24fps) can be reduced. In particular, during the blank period, the power consumption of the data driver 500 may be significantly reduced by the blank power control method. Accordingly, when the display device displays a video image, power consumption of the display device can be significantly reduced.

Fig. 8 is a block diagram illustrating an exemplary embodiment of a timing controller 200A according to the present invention.

The display apparatus according to the present exemplary embodiment is substantially the same as the display apparatus of the previous exemplary embodiment explained with reference to fig. 1 to 6B, except for the structure of the timing controller 200. Therefore, the same reference numerals will be used to refer to the same or similar components as those described in the previous exemplary embodiment of fig. 1 to 6B, and any repetitive explanation regarding the above elements will be omitted.

Referring to fig. 1, 2, 4 to 6B, and 8, the display device includes a display panel 100, a panel driver, and an application processor 600. The panel driver includes a timing controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

The application processor 600 includes a decoder 620, a graphics processing unit 640, and a memory 660.

The decoder 620 decodes the input image DI. The input image DI has a frame rate. The decoder 620 sends the decoded input image DI to the memory 660. The input image DI is stored in the memory 660.

The timing controller 200A includes a data control part 220 and a blank power control part 240. In an exemplary embodiment, the timing controller 200A may further include a frame rate register 260.

For example, the data control part 220 may include an adaptive color correction part (not shown) and a dynamic capacitance compensation part (not shown).

The frame rate register 260 stores a frame rate FPS of the input image. The graphic processing unit 640 may output a frame rate FPS of an input image to the frame rate register 260.

The blank power source control part 240 may output a blank control signal BS that varies according to a frame rate FPS of an input image. For example, in an exemplary embodiment, when the frame rate FPS of the input image is 24FPS, the second analog power supply voltage AVDD2 may maintain the OFF level for the blank period (about 25ms) of the input image data RGB. For example, when the frame rate FPS of the input image is 30FPS, the second analog power supply voltage AVDD2 may maintain the OFF level for the blank period (about 16.67ms) of the input image data RGB.

According to the present exemplary embodiment, when the display apparatus displays a video image, the input image data RGB has a frequency (e.g., 30Hz, 24Hz) equal to a frame rate (e.g., 30fps, 24fps) of the input image. Accordingly, power consumption for converting the input image DI having the frame rate (e.g., 30fps, 24fps) into the input image data RGB having frequencies (e.g., 60Hz and 120Hz) higher than the frame rate (e.g., 30fps, 24fps) can be reduced. In addition, power consumption for displaying images at frequencies (e.g., 60Hz and 120Hz) greater than the frame rate (30fps, 24fps) of the input images DI can be reduced. In particular, during the blank period of the input image data RGB, the power consumption of the data driver 500 may be significantly reduced by the blank power control method. Accordingly, when the display device displays a video image, power consumption of the display device can be significantly reduced.

According to the present exemplary embodiment, power consumption of the display device can be significantly reduced when the display device displays a video image.

The foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. In the claims, a functional limitation is intended to cover the structure described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific exemplary embodiments disclosed, and that modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims

1. A display device, characterized in that the display device comprises:

a timing controller, a data driver and a display panel;

wherein the timing controller receives input image data at a first frequency, the first frequency being equal to a frame rate of an input image, the timing controller generating a data signal having the first frequency based on the input image data having the first frequency;

the data driver converts the data signal into a data voltage; and is

The display panel displays an image based on the data voltages,

the display apparatus further includes a decoder decoding the input image, a memory storing the decoded input image in the memory, and a graphic processing unit converting the decoded input image into the input image data having the first frequency and outputting the input image data to the timing controller,

wherein the input image data includes active periods and blank periods alternating with each other, a length of the active periods being less than or equal to a length of the blank periods,

wherein the data driver includes a second switching part which is turned on during the blank period and applies a blank voltage to the data line,

wherein the second switching section includes switches in a first row and switches in a second row,

wherein the switches in the first row are alternately turned on and apply a first blank voltage to the data lines; the switches in the second row are alternately turned on and apply a second blank voltage to the data lines.

2. The display device of claim 1, wherein each interval between the active periods is uniform.

3. A display device as claimed in claim 2, characterized in that the length of the active period is 1/60 seconds, and

the length of the blank period is determined as the each interval of adjacent active periods.

4. The display device of claim 1, wherein a length of the active period is equal to a length of the blank period when the first frequency is 30 Hz.

5. The display device of claim 1, wherein the length of the active period is less than the length of the blanking period when the first frequency is less than 30 Hz.

6. The display device according to claim 1, wherein the timing controller includes a blank power supply control part which controls the data driver to be turned off during the blank period.

7. The display device according to claim 6, wherein the timing controller further includes a register that stores the frame rate of the input image, and wherein

The blank power supply control section outputs a blank control signal that changes in accordance with the frame rate of the input image.

8. The display device of claim 6, wherein the data driver further comprises:

the digital-to-analog conversion circuit comprises a power supply control part, a digital-to-analog conversion part, a buffer part and a first switch part;

wherein the power supply control section controls the power supply based on a blanking control signal determined in accordance with the input image;

the digital-to-analog conversion part converts the data signal from a digital signal to an analog signal;

the buffer portion buffers the data voltage;

the first switching part is turned on during the active period and applies the data voltage to a data line.

9. The display device according to claim 8, wherein the data driver further includes a power switch section that turns off the digital-to-analog conversion section and the buffer section during the blank period.

10. The display device according to claim 8, wherein the data driver further includes a blank voltage supply section that supplies the blank voltage to the second switching section.

11. A method of driving a display panel, the method comprising:

receiving input image data at a first frequency equal to a frame rate of the input image;

generating a data signal having the first frequency based on the input image data having the first frequency;

converting the data signal into a data voltage using a data driver;

an image is displayed based on the data voltages,

the method further includes decoding the input image, storing the decoded input image in a memory, converting the decoded input image into the input image data having the first frequency, and outputting the input image data to a timing controller,

wherein the input image data includes active periods and blank periods alternating with each other, a length of the active periods being less than or equal to a length of the blank periods

Wherein, during the blank period, the second switching part of the data driver is turned on and a blank voltage is applied to the data line,

12. The method of claim 11, wherein each interval between the activity periods is uniform.

13. The method of claim 11, wherein the timing controller controls the data driver to be turned off during the blank period.

14. The method of claim 13, wherein the timing controller further comprises a register to store the frame rate of the input image.