CN105389267A - Method for allocating chip to stats - Google Patents
Method for allocating chip to stats Download PDFInfo
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- CN105389267A CN105389267A CN201510689875.1A CN201510689875A CN105389267A CN 105389267 A CN105389267 A CN 105389267A CN 201510689875 A CN201510689875 A CN 201510689875A CN 105389267 A CN105389267 A CN 105389267A
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- statistics
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- stats
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Display Devices Of Pinball Game Machines (AREA)
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- Communication Control (AREA)
Abstract
The present invention discloses a method for allocating a chip to stats. The method comprises: carrying out public statistics on packets at an inlet port, a queue module, and an outlet port in the chip; and carrying out private statistics on packets at an inbound direction processing module and an outbound direction processing module. A public statistics process comprises: allocating an address index to each type of statistics, wherein the address index is pointed to a storage position in a RAM allocated to each type of statistics, and updating the RAM. A private statistics process comprises: selecting a type of to-be-collected statistics according to packet type information; allocating an address index to each type of statistics, wherein the address index comprises a selected RAM number, and a storage position in a corresponding RAM; and updating the RAM, wherein the number of RAMs is the maximum number of types of statistics to be collected on each packet. The method disclosed by the present invention improves storage flexibility of the stats, and reduces collisions caused due to priority setting.
Description
Technical field
The present invention relates to a kind of counting messages technology, especially relate to the chip implementing method that a kind of stats flexibly distributes.
Background technology
Conveniently keeper carries out malfunction elimination and traffic monitoring to switch, switch is needed to add up the number of various message and total message length in the course of the work, such as pass in and out the message number of port port, three layers of message number forwarded, meet the message number etc. of certain ACE (ACE, the entry namely in ACL) rule.During counting messages, the allocation index that software can distribute RAM for it is as initial storage space, and dissimilar statistical information distributes different storage space, realizes the statistics of message.
The common approach that prior art mainly adopts is: design polylith RAM, for each class stats (statistics) distributes fixing RAM, each class stats can only store in the RAM specified, and is stored in and specifies which position of RAM by software static allocation.When the number needing the stats kind of statistics more than RAM, adopt the stats fixed storage priority of multiple kind, distribute the scheme of the different memory location of same block RAM.
To ensure that often kind of stats distributes a block RAM, cost compare is high, and the area taking chip is larger.Consider the design of cost etc. in practical application, need the stats kind of statistics often more than the number of RAM.If in a repeating process, message needs to be multiple stats to be added up, and when this several stats is by chance fixed again and distributes same block RAM, stats produces conflict, RAM can only upgrade message number corresponding to the highest stats of priority and message length, and the stats that priority is low can not be updated.And other do not need the RAM of the stats done to be exactly now idle condition.Therefore adopt the dirigibility limiting stats storage of the schemes tend of fixed allocation RAM, the reliability causing stats to add up reduces.
Summary of the invention
The object of the invention is to the defect overcoming prior art, the chip implementing method that a kind of stats distributes is provided, the public stats that can both do for each message distributes independently RAM, distribute by the exclusive stats kind of different message share, can the RAM of unrestricted choice, distribute the stats RAM stored to realize dynamic flexible.
For achieving the above object, the present invention proposes following technical scheme: the chip implementing method that a kind of stats distributes, and comprising:
Message enter successively chip inbound port, enter direction processing module, Queue module, outgoing direction processing module and outbound port, do public statistics described inbound port, Queue module and outbound port are all enable, described enter direction processing module and outgoing direction processing module all do exclusive statistics, wherein
Described public statistic processes comprises: be every class statistics distribution allocation index, described allocation index points to the memory location in the RAM having distributed to every class statistics, upgrades described RAM;
Described exclusive statistic processes comprises: according to the kind of information of message, the kind that selection need be added up, and be every class statistics distribution allocation index, described allocation index comprises the RAM label of selection and the memory location in corresponding RAM, upgrade described RAM, wherein, described RAM number is the maximal value that each message needs to do the kind of adding up.
Preferably, when doing described public statistics, the RAM label that described often kind of statistics stores is static allocation, and described often kind of statistics memory location in the RAM be assigned to is dynamic assignment.
Preferably, when doing described exclusive statistics, the RAM label that described often kind of statistics stores and the memory location in the RAM be assigned to are all by dynamic assignment.
Preferably, public statistics and exclusive statistics, after allocation index completes, upgrade the message number and message length information of adding up in described RAM respective memory locations.
Preferably, after message enters the physics inbound port of exchange chip, inbound port has detected that message enters, and does the public statistics of the input flow rate of each port of Way according to enable information.
Preferably, message enters Way in processing module, do comprise based on VlanId, based on MAC, based on the exclusive statistics of ACL etc.
Preferably, message enters Queue module, does the public statistics of the message flow in statistics Queue module different queue ID according to enable information.
Preferably, message enters Way out processing module, do comprise based on message editing, based on the exclusive statistics of VlanId.
Preferably, message arrives specific physics outbound port, does the public statistics of the delivery rate of each port of Way out according to enable information.
The present invention is that the public stats that each message can both do distributes independently RAM, distribute by the exclusive stats kind of different message share, can the RAM of unrestricted choice.Software freely distribute to stats share storage space pointer time, it is no longer the address pointer only distributing RAM inside, but RAMID and RAM home address is distributed to stats simultaneously, such stats freely can select RAM, when multiple stats will store simultaneously, only need to distribute different RAM, conflict can not be brought because of fixed allocation RAM.Technical solution of the present invention improves the dirigibility that stats stores, and reduces the conflict produced because of setting priority.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that the public stats of the present invention distributes independent RAM;
Fig. 2 is that the exclusive stats of the present invention distributes RAM Shared schematic diagram;
Fig. 3 and Fig. 4 is the schematic flow sheet of the chip implementing method that a kind of stats of the present invention distributes.
Embodiment
Below in conjunction with accompanying drawing of the present invention, clear, complete description is carried out to the technical scheme of the embodiment of the present invention.
The chip implementing method that a kind of stats that the present invention discloses distributes, supports independent RAM and RAM Shared and the stats storage mode deposited.The storage of independent RAM mainly stores based on the total stats of often kind of message flow (flow), and the storage of RAM Shared is mainly for the exclusive statistics of each flow.
As shown in Figure 1, suppose that technical solution of the present invention supports L independent RAM, independent RAM1 ~ independent RAML, support the statistics of K kind stats, wherein L=K.The value of L/K is the stats species number that often kind of flow has.Often kind of corresponding block RAM of total stats, when doing public statistics, the RAM label of often kind of statistics storage is static allocation, and often kind of statistics memory location in the RAM be assigned to is dynamic assignment.
If technical solution of the present invention supports N number of shared RAM, RAM Shared 1 ~ RAM Shared N, supports the statistics of M kind stats, wherein M>N, the value of M is the kind sum that various flow needs to be stats, and the value of N is the maximal value that various flow needs to do the kind of stats.The RAM label (RAMID) of often kind of stats storage is by software dynamic assignment, and the memory location in the RAM be assigned to is also by dynamic assignment, ensures that each class message needs the stats done to realize, can not produce conflict again.
Particularly, as shown in Figure 1, for stats public in technical solution of the present invention distributes the schematic diagram of independent RAM, its processing procedure is as follows:
Enablely be public stats, message enters chip, for such stats distributes an allocation index, this allocation index points to static allocation and, to the respective memory locations in the RAM of such stats, upgrades the message number and message length information of adding up in this memory location.
As shown in Figure 2, for stats exclusive in this programme distributes RAM Shared schematic diagram, its processing procedure is as follows:
Message enters chip, according to the kind of information of message, the kind needing statistics is selected from exclusive stats, in Fig. 2, be partly embodied as such stats distributes an allocation index to StatsMux (stats selector switch), and this index comprises the RAMID of selection and the memory location in this RAM.
A message comes in be the stats of multiple kind, will ensure as each stats distributes different RAM during allocation index.In scheme, the various flow of the design of RAM Shared number needs the maximal value of the kind being stats, obviously can meet for each stats distributes the requirement of different RAM.After allocation index completes, upgrade the message number and message length statistical information of specifying assigned address in RAM.
Shown in composition graphs 3 and Fig. 4, be the schematic flow sheet of the chip implementing method that disclosed a kind of stats distributes, realize the statistics of various public stats and shared stats in this process.Its process is as follows:
Enable public stats1, public stats1 and public stats3.
Message enters the physical port of switch, and Port detecting enters to there being message, is public stats1, refers to here be the stats of Way in based on port mouth, and object is the flow of the input in order to add up each port.The RAM that this stats stores is the independent RAM of static allocation.
Message enters Way in processing module, resolve, search, implementation strategy etc., for two layer message, the exclusive stats1 done can based on VLAN label (VlanId), based on mac address of nic (MAC), based on Access Control List (ACL) (ACL) etc.Several different exclusive stats is stored in different RAM respectively above, and the RAMID stored distributes according to allocation algorithm state.
After Way in process completes, message enters Queue module, is public stats2, refers to the stats based on queue ID here, and object is the message flow in statistics Queue module different queue ID. and the RAM that this stats stores is the independent RAM of static allocation.
Message enters Way out processing module, may carry out as required message editor style of writing, the such as adjustment etc. of VLAN (Vlan), be here exclusive stats2 can based on message editing, based on VlanId etc.Several different exclusive stats is stored in different RAM respectively above, and the RAMID stored distributes according to allocation algorithm state.
After Way out process completes, message can export from specific port mouth, is public stats3, refers to here be the stats of Way out based on port, and object is the flow exported to add up each port.The RAM that this stats stores is the independent RAM of static allocation.
The introduction of RAM Shared design philosophy of the present invention can reduce static allocation RAM number or size, reduces chip cost; The possibility that conflict occurs can be reduced simultaneously, improve stats chip-scale statistical accuracy.
Technology contents of the present invention and technical characteristic have disclosed as above; but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from spirit of the present invention based on teaching of the present invention and announcement; therefore; scope should be not limited to the content that embodiment discloses; and various do not deviate from replacement of the present invention and modification should be comprised, and contained by present patent application claim.
Claims (10)
1. a chip implementing method for stats distribution, is characterized in that, comprising:
Message enter successively chip inbound port, enter direction processing module, Queue module, outgoing direction processing module and outbound port, do public statistics described inbound port, Queue module and outbound port are all enable, described enter direction processing module and outgoing direction processing module all do exclusive statistics, wherein
Described public statistic processes comprises: be every class statistics distribution allocation index, described allocation index points to the memory location in the RAM having distributed to every class statistics, upgrades described RAM;
Described exclusive statistic processes comprises: according to the kind of information of message, the kind that selection need be added up, and be every class statistics distribution allocation index, described allocation index comprises the RAM label of selection and the memory location in corresponding RAM, upgrade described RAM, wherein, described RAM number is the maximal value that each message needs to do the kind of adding up.
2. chip implementing method according to claim 1, is characterized in that, when doing described public statistics, the RAM label that described often kind of statistics stores is static allocation.
3. chip implementing method according to claim 1, is characterized in that, when doing described public statistics, described often kind of statistics memory location in the RAM be assigned to is dynamic assignment.
4. chip implementing method according to claim 1, is characterized in that, when doing described exclusive statistics, the RAM label that described often kind of statistics stores and the memory location in the RAM be assigned to are all by dynamic assignment.
5. chip implementing method according to claim 1, is characterized in that, public statistics and exclusive statistics, after allocation index completes, upgrade the message number and message length information of adding up in described RAM respective memory locations.
6. chip implementing method according to claim 1, is characterized in that, after message enters the physics inbound port of exchange chip, inbound port has detected that message enters, and does the public statistics of the input flow rate of each port of Way according to enable information.
7. chip implementing method according to claim 1, is characterized in that, message enters Way in processing module, do comprise based on VlanId, based on MAC, based on the exclusive statistics of ACL.
8. chip implementing method according to claim 1, is characterized in that, message enters Queue module, does the public statistics of the message flow in statistics Queue module different queue ID according to enable information.
9. chip implementing method according to claim 1, is characterized in that, message enters Way out processing module, do comprise based on message editing, based on the exclusive statistics of VlanId etc.
10. chip implementing method according to claim 1, is characterized in that, message arrives specific physics outbound port, does the public statistics of the delivery rate of each port of Way out according to enable information.
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| CN201510689875.1A CN105389267B (en) | 2015-10-21 | 2015-10-21 | The chip implementing method of stats distribution |
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| CN201510689875.1A CN105389267B (en) | 2015-10-21 | 2015-10-21 | The chip implementing method of stats distribution |
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| CN105389267B CN105389267B (en) | 2018-08-21 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108833203A (en) * | 2018-05-23 | 2018-11-16 | 新华三信息安全技术有限公司 | A kind of message statistical method and device |
| CN110658990A (en) * | 2018-06-28 | 2020-01-07 | 希捷科技有限公司 | Data storage system with improved preparation time |
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| CN102752196A (en) * | 2012-06-19 | 2012-10-24 | 中兴通讯股份有限公司 | Statistical information transmitting and counting method and device |
| CN103997415A (en) * | 2013-02-20 | 2014-08-20 | 中兴通讯股份有限公司 | Apparatus and method for realizing message statistics |
| US9003294B1 (en) * | 2014-12-23 | 2015-04-07 | FanActivate, LLC | Scalable systems for change detection of statistic data feeds across multiple servers using shared memory with configurable messaging triggers |
| CN104539490A (en) * | 2015-01-28 | 2015-04-22 | 盛科网络（苏州）有限公司 | Method and device for realizing high-speed message statistics based on switching chip |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101741739A (en) * | 2009-12-01 | 2010-06-16 | 中兴通讯股份有限公司 | Method and device for counting messages of output/input port of exchange equipment |
| CN102752196A (en) * | 2012-06-19 | 2012-10-24 | 中兴通讯股份有限公司 | Statistical information transmitting and counting method and device |
| CN103997415A (en) * | 2013-02-20 | 2014-08-20 | 中兴通讯股份有限公司 | Apparatus and method for realizing message statistics |
| US9003294B1 (en) * | 2014-12-23 | 2015-04-07 | FanActivate, LLC | Scalable systems for change detection of statistic data feeds across multiple servers using shared memory with configurable messaging triggers |
| CN104539490A (en) * | 2015-01-28 | 2015-04-22 | 盛科网络（苏州）有限公司 | Method and device for realizing high-speed message statistics based on switching chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108833203A (en) * | 2018-05-23 | 2018-11-16 | 新华三信息安全技术有限公司 | A kind of message statistical method and device |
| CN110658990A (en) * | 2018-06-28 | 2020-01-07 | 希捷科技有限公司 | Data storage system with improved preparation time |
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| CN105389267B (en) | 2018-08-21 |
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Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Shengke Communication Co.,Ltd. Address before: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |
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