CN105375940A - Interface transceiver with reduced power consumption and management method thereof - Google Patents

Abstract

The invention discloses an interface transceiver with reduced power consumption and a management method thereof. The interface transceiver comprises at least one interface circuit with selectable power consumption, the interface circuit being coupled to one or more interface signals. The interface transceiver also comprises a selection input that is coupled to the at least one interface circuit and used for receiving and selecting the signals. In this way, the level of complexity of the one or more interface circuits can be selected by the logic state of the selection input. The interface transceiver is characterized in that the at least one interface circuit comprises an emitter circuit and a receiver circuit, the emitter receiver includes a digital equalization filter connected to the selection input and having tap joints the number of which is selectable, and the number of the tap joints can be selected according to the logic state of the selection input. Receivers are simple, and the power consumption of emitters is low.

Description

A kind of interface transceiver of lower power consumption and management method thereof

Technical field

The present invention relates to a kind of interface transceiver and management method thereof of lower power consumption.

Background technology

Operating frequency and the complexity of the interface between present-day system devices and between circuit increase.Especially, according to the performance requirement of special interface, HSSI High-Speed Serial Interface needs data/Clock Extraction, jitter elimination, phasing, error correction, error recovery circuits and equalizing circuit, and these circuit can become very complicated.When foregoing circuit becomes more complicated, they have increasing digital logic portion, and the total amount of the Digital Logic used in acceptor circuit and transmitter circuit also considerably increases.

Because the demand of design resource-constrained and the application of demand fulfillment multiple interfaces, user and channel condition, so usually for the error rate and the environmental condition of worst case, design the reflector in above-mentioned interface and receiver, thus make receiver comparatively complicated, the power consumption of reflector is higher.As a result, when high channel quality can be utilized, always can not provide the receiver more complicated unlike desired structure.

When the error rate of worst case and interface condition depart from ideal situation, the complexity of above-mentioned receiver increases.The complexity of reflector also may because use digital equalization circuits and error correction encode and increase.Therefore in interface circuit or system silicon (systemsilicon), required power consumption and heat dissipation also increase, to meet the performance requirement under all expection interface conditions.Therefore, the interface transceiver that a kind of lower power consumption is provided is needed.

Summary of the invention

For solving above-mentioned existing shortcoming, main purpose of the present invention is interface transceiver and the management method thereof of the lower power consumption providing a kind of practicality, and make receiver simple, transmitter power is less.

For reaching above-described object, interface transceiver and the management method thereof of a kind of lower power consumption of the present invention take following technical scheme:

A kind of interface transceiver of lower power consumption and management method thereof, comprise and be coupled to one or more interface signal and at least one interface circuit with selectable power consumption, what be coupled with at least one interface circuit described inputs for receiving the selection selecting signal, whereby can by the described complexity level selecting the logic state of input to select described one or more interface circuit, it is characterized in that, at least one interface circuit described comprises transmitter circuit, acceptor circuit, described transmitter circuit comprise with described select to input be connected and there is the digital equalization filter of multiple taps that selectable number is selected, and can the described logic state inputted be selected to select the described quantity of described multiple tap described in root Ju, described transmitter circuit comprises variable power stage, and can according to the described grade selecting the described logic state of input to select described variable power stage, described acceptor circuit comprises and has multiple tap and input with described selection the digital equalization filter be connected, and can according to the described described quantity selecting the described logic state of input to select described multiple tap, described acceptor circuit comprises and has selectable resolution and the phase-control circuit that enter be connected pleased with described selection, and described selectable resolution can be selected according to the described described logic state of input of selecting, described acceptor circuit comprises for the treatment of described one or more interface signal and inputs with described selection the sample storage be connected, described sample storage has selectable effective dimensions, and described selectable effective dimensions can be selected according to the described described logic state of input of selecting, described acceptor circuit comprises and has selectable sampling window for the treatment of the position received from a described interface signal and input with described selection the signal transacting block be connected, and described selectable sampling window can be selected according to the described described logic state of input of selecting, described acceptor circuit comprises and has selectable CD and input with described selection the Error-Correcting Circuit be connected, and described selectable CD can be selected according to the described described logic state of input of selecting.

The method comprises, receive the instruction that instruction can reduce the power consumption of described interface transceiver, and in response to described receiving step, select the complexity of described receiver, measuring coupling, to the quality of the interface signal of described interface transceiver, judges that whether described quality is higher than threshold levels; And in response to the described quality of judgement higher than threshold levels, produce described instruction, the state of described instruction sends to remote transceiver.

Adopt the present invention of as above technical scheme, there is following beneficial effect:

The present invention makes receiver simple, and transmitter power is less.

Accompanying drawing explanation

Fig. 1 is the block diagram by a transceiver connected according to the interface of one embodiment of the invention.

Fig. 2 is the block diagram of the transceiver according to one embodiment of the invention.

Fig. 3 is the schematic diagram of exemplary power management circuits according to an embodiment of the invention.

Fig. 4 is the flow chart of the method illustrated according to one embodiment of the invention.

Embodiment

In order to further illustrate the present invention, be described further below in conjunction with accompanying drawing:

With reference to accompanying drawing especially with reference to Fig. 1, the block diagram of transceiver 12A and 12B connected by an interface or channel 10 according to one embodiment of the invention is shown.The integrated circuit that transceiver 12A, 12B can be positioned at a device such as computer peripheral, a computer system or interconnect in a system.Interface 10 can be shown single two wire bi-directional interface, can be maybe full duplex one-wire interface or the bus in half-or full-duplex configuration with multiple transceiver.Transceiver 12A with 12B each use one receiver 14A with 14B is connected with interface 10 with reflector 16A with 16B, it should be understood that, the receiver of root Ju one embodiment of the invention or reflector can be incorporated to for being connected with the interface 10 of any one the above-mentioned type and the interconnective equipment of the signal of telecommunication of other form.

Interface circuit (reflector 16A, 16B and receiver 14A, 14B) combines selection input SELA and SELB of the complexity that can reduce be connected interface circuit, to reduce power consumption.When in interface circuit 14A-B and/or 16A-B during processing signals, switch to the circuit block that power consumption is as an alternative lower, or can inhibit circuit block selectively, with the quantity of transformation reducing door, memory circuit and/or occur.When channel condition allows, also can simplify selectively or remove the analog circuit block in interface circuit 14A-B and/or 16A-B.

Therefore, above-mentioned interface electricity-supplied selectable power consumption, this selectable power consumption can be used for the power in transceiver 12A and 12B being used and dissipating lower when channel conditions are good, and the error rate (BER) using higher power consumption state to keep low when channel conditions are poor.Select can be hard-wired via the power consumption state selecting input SELA to carry out, or use an external signal terminal 17 outside programming, or use the bit register (bitregister) 19 in transceiver 12A to programme.Receiver 14A, reflector 16B or both all can by one or more selection signal controlling, each that such as can be in reflector 16A and receiver 14A provides multiple position, thus merit can be intended order for the very finely tradeoffs such as the disposal ability of receiver or the signal strength signal intensity of reflector.Or, single position or exterior terminal can be used to select for reflector 16A and receiver 14A sets single binary power consumption.

Transceiver 12A is an example with the transceiver selected via register programming or the outside outside connected.Like this, it is very useful in the integrated circuit comprising computer system, communication system or ancillary equipment and system, can hardwired exterior terminal 17 be (such as according to application in those equipment, the channel quality that the known short shielded type cable Length Indication be connected with ancillary equipment is high, or the connection of two receivers on a high-quality circuit board also indicates high channel quality).

Transceiver 12B is the example of transceiver having that the automatic complexity measured based on Xin Dao Wide in response to the measurement undertaken by interface quality measurement block 18 selects, and this interface quality measurement block can be for detecting channel quality whether lower than eye pattern (eyediagram) circuit of the threshold value expected, error detect circuit or other mechanism.Select signal SEL8 to be provided by the output of interface quality measurement block 18, and automatically select higher or lower receiver and/or transmitter complexity according to the channel quality measured.

The transceiver power consumption that interface link provides another kind of type controls, and wherein to send via interface 10 by receiving and to be set a register such as programmable register 19 by the receiver command code that such as receiver 14A receives.When the characteristic of receiver and reflector must mate (such as when selecting signal to change error-correction length or when using the filter of coupling at the often end of interface 10), the control of this interface link is very useful.When the transceiver be programmed does not have ability determination channel quality or the information not about channel condition (such as cable length), interface link controls also to can be used for notice transceiver channel situation.

With reference to Fig. 2, it illustrates the details of the device 20 according to one embodiment of the invention.Receive an interface signal at BXDATAIN (receiver data input) place, and this signal is supplied to the acceptor circuit 21 that may comprise and also may not comprise an equalization filter 21A.The output of acceptor circuit 21 passes to a series of sample latch 24 usually, and from sample latch 24, data is supplied to sample storage 25.The signal that sample latch 24 and sample storage 25 receive for " over-sampling ", thus the edge that signal can be determined when there is high dither more accurately.

Edge detection logic 26 detects one or two edge of the signal (usually comprising clock bit and data bit) received, and provides morning/late information to phase control 27, and phase control 27 is transferred control Bian sample latch 24 and shaken with compensate for low frequency.Data selection 28 extracts data, and can to detect and correcting circuit 29 minimizes the error rate of the signal received further by mistake in.

Digital complexity control circuit 23 provides one or more control signal to each above-mentioned module, selects higher or lower power consumption with root Ju channel demands.This selection can be static state or static/programmable as described with reference to FIG. 1, or is dynamic based on the output (or other suitable channel quality indicator) of eye survey map circuit 22.Eye survey map provides the measurement exported the signal quality of receiving circuit 21, gives the instruction of shake on the impact of the error rate.The power consumption of each circuit adjusts by the Direct Power grade reducing total complexity or circuit use, and can be controlled by point other control bit or single control bit.Such as, the quantity of Bian sample latch 24 used and the power consumption of sample latch block 24 proportional, the degree of depth of the resolution of the size of sample storage 25, phase-control circuit 27 and edge detection logic 26, error correction and detection 29 is all proportional with their power consumption.The power consumption of any one or all foregoing circuit blocks can be selectable, and can be controlled independently or jointly in one or more level of power consumption.

The transmitter portion of transceiver 20 comprises the optional equalization filter of an optional error correction coding circuit 31, one 32 and at the upper driver 33 transmitting data of interface TXDATAOUT (emitter data output).Digital complexity controls the complexity that 23 also can control transmitter circuit, the length of the electric current of such as driver 33, the length of equalization filter 32 or error correction coding 31.

Also illustrate that digital complexity controls 23 and is connected for the optional remote complexity control link 34 controlling power consumption with one.The instruction received at RXDATAIN place can be received the decode, with the complexity via the circuit block in the output control & device 20 of data selection 28.Also illustrate digital complexity control with for sending to the transmitter circuit of a remote transceiver to be connected complexity control information.These remote control attributes are optional, and whether their realization is depended on and can be sent and receiving control information by interface channel with hope.

With reference to Fig. 3, it illustrates the technology for the power consumption in the interface circuit of control chart 2.SELECTPD can be used for controlling the power supply to the block be connected with power supply by power control transistor 39 or equivalent device, / SELECTRST forbids a clock via the door 37B or equivalent device being used as clock disable circuit, and SELECTRST makes register 37B remain on reset mode.SEL selects between complex block 37 and replacement block 38 (it will be prohibited usually when complex block circuit 37 is activated).Circuit shown in Fig. 3 is schematic, instead of comprises the typical case of above-mentioned # device circuit of a large amount of register and door.But shown technology jointly or selectively can apply the power consumption of forbidding in the complicated part of above-mentioned receiver.Because only otherwise there is leakage path, eliminate clock in modern digital circuits or state and change and can power identical on the impact of power consumption with removal, so any above-mentioned technology is all enough on the impact of power consumption.Another kind of power reduction mechanism is the simplification of state machine circuit, wherein can and carry out selecting selection mode machine similarly between complex block 37 and replacement block 38, or by forbidding some status register (and correspondingly changing combination feedback logic).

Referring now to Fig. 4, it shows the control method according to one embodiment of the invention with flow chart.First, measurement interface channel quality (step 40), and if interface channel quality is enough to support the power consumption state in transceiver (judging 41), then selects lower two device complexity (step 42) and by interface, selection information sent to the remote transceiver (step 43) of any connection alternatively.Said method comprises optional step 40 and 43, to illustrate the complete function of the Long-distance Control comprising measurement and optional remote transceiver automatically.However, it should be understood that these optional steps are optional for enforcement the present invention.

Claims (2)

1. the interface transceiver of a lower power consumption and management method thereof, comprise and be coupled to one or more interface signal and at least one interface circuit with selectable power consumption, what be coupled with at least one interface circuit described inputs for receiving the selection selecting signal, whereby can by the described complexity level selecting the logic state of input to select described one or more interface circuit, it is characterized in that, at least one interface circuit described comprises transmitter circuit, acceptor circuit, described transmitter circuit comprise with described select to input be connected and there is the digital equalization filter of multiple taps that selectable number is selected, and can the described logic state inputted be selected to select the described quantity of described multiple tap described in root Ju, described transmitter circuit comprises variable power stage, and can according to the described grade selecting the described logic state of input to select described variable power stage, described acceptor circuit comprises and has multiple tap and input with described selection the digital equalization filter be connected, and can according to the described described quantity selecting the described logic state of input to select described multiple tap, described acceptor circuit comprises and has selectable resolution and the phase-control circuit that enter be connected pleased with described selection, and described selectable resolution can be selected according to the described described logic state of input of selecting, described acceptor circuit comprises for the treatment of described one or more interface signal and inputs with described selection the sample storage be connected, described sample storage has selectable effective dimensions, and described selectable effective dimensions can be selected according to the described described logic state of input of selecting, described acceptor circuit comprises and has selectable sampling window for the treatment of the position received from a described interface signal and input with described selection the signal transacting block be connected, and described selectable sampling window can be selected according to the described described logic state of input of selecting, described acceptor circuit comprises and has selectable CD and input with described selection the Error-Correcting Circuit be connected, and described selectable CD can be selected according to the described described logic state of input of selecting.

2. the interface transceiver of a kind of lower power consumption according to claim 1 and management method thereof, it is characterized in that, the method comprises, receive the instruction that instruction can reduce the power consumption of described interface transceiver, and in response to described receiving step, select the complexity of described receiver, measuring coupling, to the quality of the interface signal of described interface transceiver, judges that whether described quality is higher than threshold levels; And in response to the described quality of judgement higher than threshold levels, produce described instruction, the state of described instruction sends to remote transceiver.