CN105375801B - Voltage-sharing control method for modular multilevel converter - Google Patents

Abstract

The invention discloses a voltage-sharing control method of a modular multilevel converter, belonging to the technical field of capacitor voltage control. Initializing the capacitor voltage values of all sub-modules in the voltage-sharing controller; collecting bridge arm current of each phase of the modular multilevel converter, differentiating by using the voltage-current relation of capacitors to obtain the capacitance voltage change value of each control period of all sub-modules, and correcting the capacitance voltage of all sub-modules in the voltage-sharing controller; and acquiring errors between the capacitor voltage storage value in the voltage-sharing controller and the capacitor voltage acquisition value by acquiring a small amount of capacitor voltage, and correcting the capacitor voltage of all sub-modules in the voltage-sharing controller again. The voltage-sharing control of the modular multilevel converter is realized by collecting bridge arm current and a small amount of capacitor voltage, real-time collection of a large amount of sub-module capacitor voltage can be avoided, the voltage-sharing control effect is ensured, and a feasible solution is provided for reducing data communication traffic in actual voltage-sharing control and improving engineering efficiency.

Description

A Modular Multilevel Converter Voltage Equalization Control Method

technical field

The invention belongs to the technical field of capacitor voltage control, and in particular relates to a voltage equalization control method for a modularized multilevel converter.

Background technique

With the development of voltage source converter (VSC) and pulse width modulation technology, HVDC transmission technology has received more and more attention, and it can be widely used in low-power transmission, renewable energy grid connection and Passive network powered. However, VSC usually adopts a 2-level or 3-level topology, which has disadvantages such as difficult dynamic voltage equalization and high switching frequency. Modular multilevel converter (MMC), as a new type of voltage source converter, has received more and more attention in research at home and abroad. Each bridge arm of the MMC is composed of multiple modular sub-modules and bridge arm inductors in series, and multi-level superposition output is realized by controlling the trigger state of the IGBT inside the sub-module.

With the improvement of the transmission power and the increase of the number of levels, it brings certain challenges to the control of the MMC system. Sub-module voltage equalization control is a necessary control link of MMC, which is used to ensure that the capacitor voltage value of the sub-module maintains fluctuations above and below the rated value, so as to reduce the harmonic content of the bridge arm voltage output by the converter. No matter which modulation strategy the high-level MMC system adopts, it needs to collect the capacitor voltages of all sub-modules when performing voltage equalization control, and then use the voltage equalization control algorithm corresponding to the modulation strategy to complete the entire voltage equalization control process.

However, taking the N+1 level MMC system as an example, the upper and lower bridge arms of each phase need to collect the capacitor voltages of N sub-modules when performing voltage equalization control. When the value of N becomes larger, the number of capacitor voltages to be collected will increase correspondingly, and the requirements for the control cycle will also be higher: In the real-time simulator (Real Time Digital Simulation, RTDS), the capacitor voltage of 512 sub-modules is transmitted by optical fiber, It takes 4 small steps with a total period of about 10us; in actual engineering, the voltage equalization control needs to collect the capacitor voltages of the sub-modules arranged in series in a scattered manner, and then merge them together for sorting, which will also consume more control time .

Therefore, the present invention proposes a voltage equalization control method for a modular multilevel converter, which realizes the voltage equalization control of the modular multilevel converter by collecting bridge arm current and a small amount of capacitor voltage, in order to reduce the actual voltage equalization control The amount of data traffic provides a practical solution.

Contents of the invention

The object of the present invention is to propose a method for voltage equalization control of a modular multilevel converter, which is characterized in that it includes the following steps:

1) According to the different conditions of whether the sub-modules are pre-charged when the modular multi-level converter is started, initialize the capacitor voltage values of all sub-modules inside the voltage equalization controller; when the sub-modules are not charged, The capacitor voltages of all sub-modules are initialized to 0; when the sub-modules have been precharged to the rated value, the capacitor voltages of all the sub-modules inside the voltage equalizing controller are initialized to the rated value U _cref ;

2) Collect the bridge arm current of each phase of the modular multilevel converter, use the voltage-current relationship of the capacitor to differentiate, and obtain the capacitance voltage change value ΔU _c (t) of each control cycle Δt of all sub-modules; The capacitance voltage U _{ctr_i} (t) of all sub-modules is superimposed on the capacitance voltage change value ΔU _c (t), and the capacitance voltage U _{ctr_i} (t) of all sub-modules inside the voltage equalization controller is corrected to obtain the capacitance of each sub-module at time t+Δt Voltage U _{ctr_i} (t+Δt);

3) Collect k capacitor voltages, k is a positive integer and k=0.25N, N is the total number of sub-modules on a single bridge arm, and k capacitor voltages include a capacitor voltage U _{cr_m} (t+Δt) input into a sub-module; if The input sub-module is the mth sub-module, and m is a positive integer, then read the capacitance voltage U _{ctr_m} (t+Δt) of the m-th sub-module stored in the voltage equalizing controller, and then obtain the first voltage U ctr_m (t+Δt) stored in the voltage equalizing controller The error value ΔU _cd (t+Δt) between the capacitance voltage U _{ctr_m} (t+Δt) of the m sub-modules and the collected value U _{cr_m} (t+Δt);

4) Use the error value ΔU _cd (t+Δt) to correct the capacitance voltage U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt; when i=m, U _{ctr_i} (t+Δt) is corrected to U _{cr_m} (t +Δt); when i≠m, U _{ctr_i} (t+Δt) is corrected as the difference between U _{cr_m} (t+Δt) and ΔU _cd (t+Δt); for the capacitor voltage of all sub-modules inside the voltage equalizing controller Sorting, selecting the corresponding sub-modules for input, and realizing the voltage equalization control of the modular multi-level converter.

The voltage-current relationship of the capacitor is:

In formula (1), C is the capacitance value of the sub-module capacitor; U _c (t) is the capacitor voltage of the sub-module at time t; i(t) is the current flowing through the sub-module at time t.

The calculation formula of the capacitance voltage change value ΔU _c (t) is:

In formula (2), C is the capacitance value of the sub-module capacitor; U _c (t-Δt) is the capacitor voltage of the sub-module at the time t-Δt; i _c (t-Δt) is the voltage flowing through the sub-module at the time t-Δt current.

The calculation formula of the capacitance voltage value U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt is:

U _{ctr_i} (t+Δt)＝U _{ctr_i} (t)+FP _i1 (t)*ΔU _c (t) (3)

In formula (3), FP _i1 (t) represents the input state of the sub-module capacitor; when the sub-module capacitor is switched on, FP _i1 (t)=1; when the sub-module is not switched on, FP _i1 (t)=0.

The error value _{ΔU cd} (t+Δt)= _{U ctr_m (} t +Δt)−U _{cr_m} (t+Δt).

The beneficial effect of the present invention is to propose a modularized multilevel converter voltage equalization control in view of the problem that the number of collected transmission capacitor voltages is too large in the current voltage equalization control, resulting in too long simulation time or limited simulation step length method, by collecting the bridge arm current and a small amount of capacitor voltage to realize the voltage equalization control of the modular multi-level converter, thereby avoiding the real-time collection of a large number of sub-module capacitor voltages, which can reduce the time occupied by the acquisition capacitor voltage in the control cycle. It can also ensure that the voltage equalization control effect of the sub-module is not affected, and provides a practical solution for reducing the data communication volume in the actual voltage equalization control and improving engineering efficiency.

Description of drawings

Fig. 1 is a flowchart of a voltage equalization control method for a modular multilevel converter.

Figure 2 is a simulation model diagram of a 21-level single-ended MMC direct current transmission system.

Figure 3 is a waveform diagram of the capacitor voltage of the upper arm of the A phase.

detailed description

The present invention proposes a voltage equalization control method for a modularized multilevel converter. The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 shows a flow chart of a voltage equalization control method for a modular multilevel converter, including the following steps:

1) According to the different conditions of whether the sub-modules are pre-charged when the modular multi-level converter is started, initialize the capacitor voltage values of all sub-modules inside the voltage equalization controller; when the sub-modules are not charged, The capacitor voltages of all sub-modules are initialized to 0; when the sub-modules have been precharged to the rated value, the capacitor voltages of all the sub-modules inside the voltage equalizing controller are initialized to the rated value U _cref ;

2) Collect the bridge arm current of each phase of the modular multilevel converter, use the voltage-current relationship of the capacitor to differentiate, and obtain the capacitance voltage change value ΔU _c (t) of each control cycle Δt of all sub-modules; The capacitance voltage U _{ctr_i} (t) of all sub-modules is superimposed on the capacitance voltage change value ΔU _c (t), and the capacitance voltage U _{ctr_i} (t) of all sub-modules inside the voltage equalization controller is corrected to obtain the capacitance of each sub-module at time t+Δt Voltage U _{ctr_i} (t+Δt);

3) Collect k capacitor voltages, k is a positive integer and k=0.25N, N is the total number of sub-modules on a single bridge arm, and k capacitor voltages include a capacitor voltage U _{cr_m} (t+Δt) input into a sub-module; if The input sub-module is the mth sub-module, and m is a positive integer, then read the capacitance voltage U _{ctr_m} (t+Δt) of the m-th sub-module stored in the voltage equalizing controller, and then obtain the first voltage U ctr_m (t+Δt) stored in the voltage equalizing controller The error value ΔU _cd (t+Δt) between the capacitance voltage U _{ctr_m} (t+Δt) of the m sub-modules and the collected value U _{cr_m} (t+Δt);

4) Use the error value ΔU _cd (t+Δt) to correct the capacitance voltage U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt; when i=m, U _{ctr_i} (t+Δt) is corrected to U _{cr_m} (t +Δt); when i≠m, U _{ctr_i} (t+Δt) is corrected as the difference between U _{cr_m} (t+Δt) and ΔU _cd (t+Δt); for the capacitor voltage of all sub-modules inside the voltage equalizing controller Sorting, selecting the corresponding sub-modules for input, and realizing the voltage equalization control of the modular multi-level converter.

Wherein, the voltage-current relationship of the capacitor is:

In formula (1), C is the capacitance value of the sub-module capacitor; U _c (t) is the capacitor voltage of the sub-module at time t; i(t) is the current flowing through the sub-module at time t.

Wherein, the calculation formula of the capacitance voltage change value ΔU _c (t) is:

In formula (2), C is the capacitance value of the sub-module capacitor; U _c (t-Δt) is the capacitor voltage of the sub-module at the time t-Δt; i _c (t-Δt) is the voltage flowing through the sub-module at the time t-Δt current.

Wherein, the calculation formula of the capacitance voltage value U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt is:

U _{ctr_i} (t+Δt)＝U _{ctr_i} (t)+FP _i1 (t)*ΔU _c (t) (3)

In formula (3), FP _i1 (t) represents the input state of the sub-module capacitor; when the sub-module capacitor is switched on, FP _i1 (t)=1; when the sub-module is not switched on, FP _i1 (t)=0.

Wherein, the error value ΔU _cd (t+Δt)=U _{ctr_m} between the capacitor voltage U _{ctr_m} (t+Δt) of the mth sub-module stored inside the voltage equalizing controller and the collected value U _{cr_m} (t+Δt) (t+Δt)-U _{cr_m} (t+Δt).

specifically,

In PSCAD/EMTDC, build the simulation model diagram of the 21-level single-ended MMC DC transmission system shown in Figure 2, and the simulation parameters are shown in Table 1;

Table 1 Simulation parameter table

In the MMC system, the rectifier side adopts constant active power and reactive power control, the controlled active power and reactive power are 10MW and 3Mvar respectively, and the modulation strategy adopts the nearest level approximation modulation.

When the MMC system and the controller are started, the capacitor voltage values of the sub-modules inside the voltage equalizing controller are initialized. The capacitor voltages of all sub-modules are mainly divided into two different situations: the sub-module is not pre-charged, and the sub-module has been pre-charged to Rated value; when the sub-module is not pre-charged, the capacitor voltage of all sub-modules inside the voltage equalizing controller is initialized to 0; when the sub-module has been pre-charged to the rated value, all sub-modules inside the voltage equalizing controller The capacitor voltage is initialized to the sub-module rating of 2.0kV.

Collect the bridge arm current of each phase of the modular multilevel converter, use the voltage-current relationship of the capacitor to differentiate, and obtain the capacitor voltage change value ΔU _c (t) of each control cycle Δt of all sub-modules;

The voltage-current relationship of a capacitor is:

In formula (1), C is the capacitance value of the sub-module capacitor; U _c (t) is the capacitor voltage of the sub-module at time t; i(t) is the current flowing through the sub-module at time t;

Differentiate formula (1) to get:

In formula (2), C is the capacitance value of the sub-module capacitor; U _c (t-Δt) is the capacitor voltage of the sub-module at the time t-Δt; i _c (t-Δt) is the voltage flowing through the sub-module at the time t-Δt current;

Since the sub-modules in the bridge arm are connected in series and the capacitance C is equal, the bridge arm current flowing into the input sub-module in the bridge arm is equal; that is, between each sub-module input in the same bridge arm, the formula (2) i _c (t) is equal, and i _c (t-Δt) in formula (2) is equal; therefore, according to formula (2), the capacitance voltage change value ΔU _c (t) of each control cycle Δt of all sub-modules can be obtained.

The capacitance voltage U _{ctr_i} (t) of all sub-modules is superimposed on the capacitance voltage change value ΔU _c (t), and the capacitance voltage U _{ctr_i} (t) of all sub-modules inside the voltage equalization controller is corrected to obtain the value of each sub-module at time t+Δt The capacitance voltage U _{ctr_i} (t+Δt); the calculation formula of the capacitance voltage value U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt is:

U _{ctr_i} (t+Δt)＝U _{ctr_i} (t)+FP _i1 (t)*ΔU _c (t) (3)

In formula (3), FP _i1 (t) represents the input state of the sub-module capacitor; when the sub-module capacitor is switched on, FP _i1 (t)=1; when the sub-module is not switched on, FP _i1 (t)=0.

The capacitance voltage value of each sub-module at time t+Δt can be obtained by formula (3), without real-time collection of capacitance voltages of all sub-modules from the MMC system, thereby reducing the time taken in the control cycle of collecting capacitance voltage.

Collect k capacitor voltages, k is a positive integer and k=0.25N, N is the total number of sub-modules on a single bridge arm, and k capacitor voltages include a capacitor voltage U _{cr_m} (t+Δt) input into the sub-module; as shown in Figure 2 Take the upper bridge arm of phase A in the built system as an example. If a small number of capacitor voltages collected are 5, the number of sub-modules in each bridge arm is N=20, and the capacitor voltage of the sub-module is therefore corresponding to 20. The bridge arm The neutron modules are numbered 1 to 20.

If the input sub-module is the mth sub-module, and m is a positive integer, then read the capacitor voltage U _{ctr_m} (t+Δt) of the m-th sub-module stored in the voltage equalizing controller, and then obtain the voltage equalizing controller internally stored The error value ΔU _cd (t+Δt) between the capacitance voltage U _{ctr_m} (t+Δt) of the mth sub-module and the collected value U _{cr_m} (t+Δt), namely: ΔU _cd (t+Δt)=U _{ctr_m} ( t+Δt)-U _{cr_m} (t+Δt).

Use the error value ΔU _cd (t+Δt) to correct the capacitance voltage U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt; when i=m, U _{ctr_i} (t+Δt) is corrected to U _{cr_m} (t+Δt ); when i≠m, U _{ctr_i} (t+Δt) is corrected as the difference between U _{cr_m} (t+Δt) and ΔU _cd (t+Δt); sorting the capacitor voltages of all sub-modules inside the voltage equalizing controller, Select the corresponding sub-modules to invest in, and realize the voltage equalization control of the modular multi-level converter.

The cumulative error generated by the operation of the voltage equalization controller is corrected by collecting the capacitor voltage of any input sub-module in real time, so as to ensure that the voltage equalization control effect of the sub-module is not affected by the cumulative error.

For the simulation model of the 21-level single-ended MMC direct current transmission system built in the embodiment, the voltage equalization control method of the modular multilevel converter proposed by the present invention is used for voltage equalization control, and the obtained A-phase upper bridge arm capacitance The voltage waveform diagram is shown in Figure 3; it can be seen from Figure 3 that the fluctuation of the capacitor voltage of the sub-module is below 8% of the rated value, and the control effect is good; the real-time collection of the capacitor voltage of the sub-module is significantly reduced, thus avoiding the actual average The real-time acquisition of the capacitor voltage of a large number of sub-modules in the voltage control application can not only reduce the time occupied by the acquisition of the capacitor voltage in the control cycle, but also ensure that the effect of the voltage equalization control of the sub-modules is not affected. In order to reduce the data in the actual voltage equalization control It provides a practical solution to reduce communication volume and improve engineering efficiency.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (4)

1. A modular multilevel converter voltage equalization control method, characterized in that, comprises the steps: 1) According to the different conditions of whether the sub-modules are pre-charged when the modular multi-level converter is started, initialize the capacitor voltage values of all sub-modules inside the voltage equalization controller; when the sub-modules are not charged, The capacitor voltages of all sub-modules are initialized to 0; when the sub-modules have been precharged to the rated value, the capacitor voltages of all the sub-modules inside the voltage equalizing controller are initialized to the rated value U _cref ; 2) Collect the bridge arm current of each phase of the modular multilevel converter, use the voltage-current relationship of the capacitor to differentiate, and obtain the capacitance voltage change value ΔU _c (t) of each control cycle Δt of all sub-modules; The capacitance voltage U _{ctr_i} (t) of all sub-modules is superimposed on the capacitance voltage change value ΔU _c (t), and the capacitance voltage U _{ctr_i} (t) of all sub-modules inside the voltage equalization controller is corrected to obtain the capacitance of each sub-module at time t+Δt Voltage U _{ctr_i} (t+Δt); 3) Collect k capacitor voltages, k is a positive integer and k=0.25N, N is the total number of sub-modules on a single bridge arm, and k capacitor voltages include a capacitor voltage U _{cr_m} (t+Δt) input into a sub-module; if The input sub-module is the mth sub-module, and m is a positive integer, then read the capacitance voltage U _{ctr_m} (t+Δt) of the m-th sub-module stored in the voltage equalizing controller, and then obtain the first voltage U ctr_m (t+Δt) stored in the voltage equalizing controller The error value ΔU _cd (t+Δt) between the capacitance voltage U _{ctr_m} (t+Δt) of the m sub-modules and the collected value U _{cr_m} (t+Δt); 4) Use the error value ΔU _cd (t+Δt) to correct the capacitance voltage U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt; when i=m, U _{ctr_i} (t+Δt) is corrected to U _{cr_m} (t +Δt); when i≠m, U _{ctr_i} (t+Δt) is corrected as the difference between U _{cr_m} (t+Δt) and ΔU _cd (t+Δt); for the capacitor voltage of all sub-modules inside the voltage equalizing controller Sorting, selecting the corresponding sub-modules for input, and realizing the voltage equalization control of the modular multi-level converter. 2. A method for voltage equalization control of a modular multilevel converter according to claim 1, wherein the voltage-current relationship of the capacitor is: <mrow><mi>i</mi><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mi>C</mi><mfrac><mrow><msub><mi>dU</mi><mi>c</mi></msub><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow></mrow><mrow><mi>d</mi><mi>t</mi></mrow></mfrac><mo>-</mo><mo>-</mo><mo>-</mo><mrow><mo>(</mo><mn>1</mn><mo>)</mo></mrow></mrow> In formula (1), C is the capacitance value of the sub-module capacitor; U _c (t) is the capacitor voltage of the sub-module at time t; i(t) is the current flowing through the sub-module at time t. 3. A method for voltage equalization control of a modular multilevel converter according to claim 1, wherein the formula for calculating the capacitance voltage change value ΔU _c (t) is: <mrow><msub><mi>&amp;Delta;U</mi><mi>c</mi></msub><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>=</mo><msub><mi>U</mi><mi>c</mi></msub><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>-</mo><msub><mi>U</mi><mi>c</mi></msub><mrow><mo>(</mo><mi>t</mi><mo>-</mo><mi>&amp;Delta;</mi><mi>t</mi><mo>)</mo></mrow><mo>=</mo><mfrac><mrow><mi>&amp;Delta;</mi><mi>t</mi></mrow><mrow><mn>2</mn><mi>C</mi></mrow></mfrac><mo>&amp;lsqb;</mo><msub><mi>i</mi><mi>c</mi></msub><mrow><mo>(</mo><mi>t</mi><mo>)</mo></mrow><mo>+</mo><msub><mi>i</mi><mi>c</mi></msub><mrow><mo>(</mo><mi>t</mi><mo>-</mo><mi>&amp;Delta;</mi><mi>t</mi><mo>)</mo></mrow><mo>&amp;rsqb;</mo><mo>-</mo><mo>-</mo><mo>-</mo><mrow><mo>(</mo><mn>2</mn><mo>)</mo></mrow></mrow> In formula (2), C is the capacitance value of the sub-module capacitor; U _c (t-Δt) is the capacitor voltage of the sub-module at the time t-Δt; i _c (t-Δt) is the voltage flowing through the sub-module at the time t-Δt current. 4. A kind of modularized multilevel converter voltage equalization control method according to claim 1, it is characterized in that, the calculation formula of the capacitor voltage value U _{ctr_i} (t+Δt) of each sub-module at the time t+Δt for: U _{ctr_i} (t+Δt)＝U _{ctr_i} (t)+FP _i1 (t)*ΔU _c (t) (3) In formula (3), FP _i1 (t) represents the input state of the sub-module capacitor; when the sub-module capacitor is switched on, FP _i1 (t)=1; when the sub-module is not switched on, FP _i1 (t)=0.