CN105374393A - Memory and memory storage unit reading method - Google Patents
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- 206010070834 Sensitisation Diseases 0.000 claims description 73
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Abstract
The present invention discloses a memory and a memory storage unit reading method. The memory comprises: a storage area for storing data, wherein the storage area comprises a first storage area and a second storage area, and the first storage area and the second storage area respectively comprise a plurality of storage units; a decoding circuit for selecting the storage unit corresponding to an address signal from the storage area according to the input address signal, and the decoding circuit comprises a first decoding circuit and a second decoding circuit; and a sensitive array for reading the storage unit corresponding to the address signal to determine the data form of the storage unit corresponding to the address signal, the first decoding circuit is connected between the first storage area and the sensitive array, and the second decoding circuit is connected between the second storage area and the sensitive array. According to the present invention, the two storage areas share the sensitive array, such that the chip area is reduced, the chip cost is reduced, and the reading performance of the memory can not be reduced.
Description
Technical field
The present invention relates to memory area, particularly relate to the method for the storage unit of a kind of storer and this storer of reading.
Background technology
In flash memory (flashmemory), data store in the memory unit with 1 and 0 two kind of form, wherein, " 1 " corresponds to eraseable memory unit (Erasecell), and " 0 " corresponds to memory cells (Programcell).When reading the data in storer, in order to judge that certain storage unit is Erasecell or Programcell, need storage unit and a reference unit to compare, according to the state of comparative result determining storage unit.Usual employing sense amplifier (SenseAmplifier) circuit compares, and sense amplifier circuit is also called for short SA circuit, and the array be made up of SA circuit is commonly called sensitization array (SenseArray).In flash storage chip, SenseArray is usually by N number of (N=16,32,64,128,256,512,1024,2048 ...) SA circuit composition, occupy larger chip area.
Shown in figure 1, the schematic diagram of the sensitization array layout method of the small-capacity memory provided for prior art.In traditional low capacity flashmemory storer, comprise: one group of sensitization array 11 (SenseArray), one group of decoding scheme 12 (YMUX) and one group of storage area 13 (MemoryArray), wherein, sensitization array 11 is connected with decoding scheme 12, and decoding scheme 12 is connected with storage area 13.Storage area 13 is for storing all data of low capacity flashmemory storer, and decoding scheme 12 chooses corresponding storage unit according to the address signal of input from storage area 13, and sensitization array 12 carries out state reading to the storage unit of described correspondence.But, the layout type of sensitization array 11, decoding scheme 12 and storage area 13 lamination successively, is applied in the flash storage of low capacity, usually as 64M, 32M, 16M, 8M etc., if Large Copacity memory storer adopts the layout type shown in Fig. 1, then reduce memory read/write performance.
Shown in figure 2, the schematic diagram of the sensitization array layout method of the mass storage provided for prior art.Along with the market demand is increasing, the demand of flash storage capacity is also improved constantly, such as NorFlashMemory (rejection gate flash memory) market increases to 128M, 256M etc., and the amount of capacity of NandFlashMemory (Sheffer stroke gate flash memory) tens G especially.For Large Copacity memory storer, such as more than 64M, the left sensitization array of layout 21 (SenseArrayLeft) and right sensitization array 24 (SenseArrayRight), left decoding scheme 22 (YMUXLeft) and right decoding scheme 25 (YMUXRight) are set, the left storage area 23 (MemoryArrayLeft) being divided into capacity equal total storage area and right storage area 26 (MemoryArrayRight), wherein, left storage area 23 is connected with left decoding scheme 22, left decoding scheme 22 is also connected with left sensitization array 21, and right storage area 26 is connected with right decoding scheme 25, right decoding scheme 25 is also connected with right sensitization array 24.The advantage of this left-right layout mode is the readwrite performance that can not reduce storer, and shortcoming is to need a large amount of SA circuit, and also namely SenseArray occupies larger area, is unfavorable for the reduction of chip cost.
The layout type of the sensitization array of above-mentioned different capabilities storer occupies larger chip area, thus the cost of memory chip is increased.
Summary of the invention
The invention provides a kind of method of storer and reading Memory Storage Unit, share a sensitization array by two storage areas of storer, decrease the sensitization array quantity in storer, the effect reach saving chip area, reducing costs.
First aspect, the invention provides a kind of storer, comprising: storage area, decoding scheme and sensitization array;
Described storage area, for storing data, wherein, described storage area comprises the first storage area and the second storage area, and described first storage area and described second storage area comprise several storage unit respectively;
Described decoding scheme, for the address signal according to input, from described storage area, choose the storage unit corresponding with described address signal, wherein, described decoding scheme comprises the first decoding scheme and the second decoding scheme;
Described sensitization array, for reading storage unit corresponding to described address signal, to judge the data mode of the storage unit that described address signal is corresponding;
Described first decoding scheme is connected between described first storage area and described sensitization array, and described second decoding scheme is connected between described second storage area and described sensitization array.
Further, the capacity of described first storage area and described second storage area is equal.
Further, the data mode of the storage data of described storage area comprises: the first data mode and the second data mode;
Wherein, described first data mode is " 1 ", and described second data mode is " 0 ".
Further, when described first data mode is " 1 ", corresponding storage unit is eraseable memory unit;
When described second data mode is " 0 ", corresponding storage unit is memory cells.
Further, described first decoding scheme and described second decoding scheme are array decoding circuit.
Further, described sensitization array is made up of several sense amplifier circuit;
Wherein, described sense amplifier circuit, for reading the storage unit of described first storage area, and for reading the storage unit of described second storage area.
Further, when described first decoding scheme and described second decoding scheme are array decoding circuit, described storer is connected to form in accordance with the order from top to bottom successively by described first storage area, described first decoding scheme, described sensitization array, described second decoding scheme and described second storage area; Or described storer is connected to form in accordance with the order from top to bottom successively by described second storage area, described second decoding scheme, described sensitization array, described first decoding scheme and described first storage area.
Further, described storer is NOR flash memory or NAND quick-flash memory.
Second aspect, the invention provides a kind of method reading Memory Storage Unit, for reading the storer described in above-mentioned first aspect, comprising:
To decoding scheme Input Address signal, wherein, described decoding scheme comprises the first decoding scheme and the second decoding scheme;
According to described address signal, the storage unit corresponding with described address signal is chosen from described storage area, wherein, described storage area comprises the first storage area and the second storage area, and described first storage area and described second storage area comprise several storage unit respectively;
Storage unit corresponding to described address signal is read, to judge the data mode of the storage unit that described address signal is corresponding by described sensitization array.
Further, the first address signal is inputted to described first decoding scheme, according to described first address signal, first storage unit corresponding with described first address signal is chosen from several storage unit described first storage area, described first storage unit is read, to judge the data mode of described first storage unit by described sensitization array; And input the second address signal to described second decoding scheme, according to described second address signal, second storage unit corresponding with described second address signal is chosen from several storage unit described second storage area, described second storage unit is read, to judge the data mode of described second storage unit by described sensitization array.
Further, read storage unit corresponding to described address signal by described sensitization array, to judge the data mode of the storage unit that described address signal is corresponding, comprising:
Apply to read voltage, with the reading electric current making described sensitization array obtain storage unit corresponding to described address signal by the storage unit corresponding to described address signal;
Judge the size of the reading electric current of the storage unit that described address signal is corresponding and the reference current of reference unit;
According to judged result, judge the data mode of the storage unit that described address signal is corresponding.
The method of a kind of storer provided by the invention and reading Memory Storage Unit, by total storage area of storer being divided into the first storage area and second storage area of equal capacity, first storage area and the second storage area pass through with after the first decoding scheme be connected separately and the second decoding scheme, share a sensitization array, sensitization array is for reading the memory cell data form of the first storage area and reading the memory cell data form of the second storage area, compared with the mass storage of prior art, memory chip provided by the invention can reduce the area of a sensitization array, thus reduce chip area and reduce chip manufacturing cost, and the reading performance of storer can not be reduced, compared with the small-capacity memory of prior art, memory chip of the present invention is adopted to improve readwrite performance.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, introduce doing one to the accompanying drawing used required in embodiment or description of the prior art simply below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The schematic diagram of the sensitization array layout method of the small-capacity memory that Fig. 1 provides for prior art;
The schematic diagram of the sensitization array layout method of the mass storage that Fig. 2 provides for prior art;
Fig. 3 is the structural representation of a kind of storer that the embodiment of the present invention one provides;
Fig. 4 is a kind of schematic flow sheet reading the method for Memory Storage Unit that the embodiment of the present invention two provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, hereinafter with reference to the accompanying drawing in the embodiment of the present invention, by embodiment, technical scheme of the present invention is described clearly and completely, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment one
With reference to figure 3, for the structural representation of a kind of storer that the embodiment of the present invention one provides, the storer of the present embodiment can be used as internal memory or portability device, be applied in the products such as various number, electronics, intelligent instrument, be applicable to the situation reducing memory chip cost, saving memory chip area and Memory Storage Unit is carried out to read operation checking.Data type in the mode of the reading cells of the storer that the present embodiment one provides and storage unit is applicable to the small-capacity memory within 64M, is also applicable to the mass storage being greater than 64M simultaneously.
This storer comprises: storage area, decoding scheme and sensitization array.
Wherein, described storage area, for storing data, wherein, described storage area comprises the first storage area 110 and the second storage area 150, and described first storage area 110 and described second storage area 150 comprise several storage unit respectively; Described decoding scheme, for the address signal according to input, from described storage area, choose the storage unit corresponding with described address signal, wherein, described decoding scheme comprises the first decoding scheme 120 and the second decoding scheme 140; Described sensitization array 130, for reading storage unit corresponding to described address signal, to judge the data mode of the storage unit that described address signal is corresponding; Described first decoding scheme 120 is connected between described first storage area 110 and described sensitization array 130, and described second decoding scheme 140 is connected between described second storage area 150 and described sensitization array 130.
Preferably, the capacity of described first storage area 110 and described second storage area 150 is equal.
As mentioned above, total storage area of described storer is divided into the first storage area 110 and the second storage area 150, the capacity of the first storage area 110 and the second storage area 150 is equal, namely there is the storage unit of equal amount, reason is, first storage area 110 and the second storage area 150 share a sensitization array 130, if the capacity of two pieces of storage areas is unequal, when then sensitization array 130 reads larger capacity storage area, reading efficiency is slower, read comparatively low capacity storage area time reading efficiency very fast, unbalanced reading efficiency affects the reading performance of storer, therefore the first storage area 110 and the second storage area 150 should have the storage unit of equal number.By the storage unit of the first storage area 110 according to m capable * n arrange regularly arranged, then the second storage area 150 is also m capable * n array storage unit.Each storage unit has an address, and this address, as the numbering distinguishing different storage unit, also represents storage unit position in memory simultaneously.
Preferably, the data mode of the storage data of described storage area comprises: the first data mode and the second data mode; Wherein, described first data mode is " 1 ", and described second data mode is " 0 ".
Preferably, when described first data mode is " 1 ", corresponding storage unit is eraseable memory unit; When described second data mode is " 0 ", corresponding storage unit is memory cells.
As mentioned above, each storage unit of storage area is for storing data, each storage unit known has an address, the data deposited in each address are the content of storage unit, these data represent usually in binary form, and namely data are stored in each storage unit with the form of " 1 " or " 0 ".When the data mode of a certain storage unit is " 1 ", giving tacit consent to this storage unit is eraseable memory unit, when the data mode of this storage unit is " 0 ", this storage unit is memory cells, and the process that the data of storage unit become " 1 " from " 0 " is called erase operation, the process that the data of storage unit become " 0 " from " 1 " is called programming operation.
Preferably, described first decoding scheme 120 and described second decoding scheme 140 are array decoding circuit.
As mentioned above, described first decoding scheme 120 and described second decoding scheme 140 have identical structure, reason is, first storage area 110 and the second storage area 150 have the storage unit of same quantity row and column, and only read this two storage areas by a sensitization array 130, therefore described first decoding scheme 120 and described second decoding scheme 140 have identical connected mode and identical function, namely from each self-corresponding storage area addressable memory cell to read this storage unit by sensitization array 130.
When the first decoding scheme 120 and the second decoding scheme 140 are array decoding circuit, for carrying out decoding according to the address signal of input, the more multiple storage unit in a wherein row storage array are carried out addressing and chosen.
Preferably, described sensitization array 130 is made up of several sense amplifier circuit; Wherein, described sense amplifier circuit, for reading the storage unit of described first storage area 110, and for reading the storage unit of described second storage area 150.
As mentioned above, each sense amplifier circuit of described sensitization array 130 is all for reading the curtage of the storage unit that decoding scheme is chosen, to judge that according to the curtage of reference unit the data mode of this storage unit is as " 1 " or " 0 ", namely sense amplifier circuit reads out the curtage of Destination Storage Unit, known reference unit curtage now, both compare, if the curtage of storage unit is large, then judge that the data of this storage unit are as " 1 ", if the curtage of storage unit is little, then judge that the data of this storage unit are as " 0 ".
Preferably, when described first decoding scheme 120 and described second decoding scheme 140 are array decoding circuit, described storer is connected to form in accordance with the order from top to bottom successively by described first storage area 110, described first decoding scheme 120, described sensitization array 130, described second decoding scheme 140 and described second storage area 150; Or described storer is connected to form in accordance with the order from top to bottom successively by described second storage area 150, described second decoding scheme 140, described sensitization array 130, described first decoding scheme 120 and described first storage area 110.
As mentioned above, array decoding circuit comprises first row decoding scheme and secondary series decoding scheme, that decoding and addressing are carried out to the storage unit of the n row storage array of the first storage area 110 respectively, decoding and addressing is carried out with the storage unit of the n row storage array to the second storage area 150, first row decoding scheme can be defaulted as and secondary series decoding scheme is all made up of n column decoding unit, i.e. n column decoding unit of the corresponding first row decoding scheme of the n row storage array of the first storage area 110, n column decoding unit of the corresponding secondary series decoding scheme of n row storage array of the second storage area 150, first storage area 110 and the second storage area 150 share a sensitization array 130 simultaneously, therefore the first storage area 110 of storer, first decoding scheme 120, sensitization array 130, second decoding scheme 140 is connected in accordance with the order from top to bottom with the second storage area 150, or the second storage area 150, second decoding scheme 140, sensitization array 130, first decoding scheme 120 is connected in accordance with the order from top to bottom with the first storage area 110.
Preferably, described storer is NOR flash memory or NAND quick-flash memory.
A kind of storer provided by the invention, by total storage area of storer being divided into the first storage area 110 and the second storage area 150 of equal capacity, first storage area 110 and the second storage area 150 pass through with after the first decoding scheme 120 be connected separately and the second decoding scheme 140, share a sensitization array 130, sensitization array 130 is for reading the memory cell data form of the first storage area 110 and reading the memory cell data form of the second storage area 150, compared with the mass storage of prior art, memory chip provided by the invention can reduce the area of a sensitization array 130, thus decrease chip area and reduce chip manufacturing cost, and the reading performance of storer can not be reduced, compared with the small-capacity memory of prior art, memory chip of the present invention is adopted to improve readwrite performance.
Embodiment two
Shown in figure 4, it is a kind of schematic flow sheet reading the method for Memory Storage Unit that the embodiment of the present invention two provides.The storer that this usage provides for reading above-described embodiment, the method specifically comprises the steps:
Step 210, to decoding scheme Input Address signal, wherein, described decoding scheme comprises the first decoding scheme and the second decoding scheme;
Step 220, according to described address signal, the storage unit corresponding with described address signal is chosen from described storage area, wherein, described storage area comprises the first storage area and the second storage area, and described first storage area and described second storage area comprise several storage unit respectively;
Step 230, read storage unit corresponding to described address signal by described sensitization array, to judge the data mode of the storage unit that described address signal is corresponding.
Preferably, the first address signal is inputted to described first decoding scheme, according to described first address signal, first storage unit corresponding with described first address signal is chosen from several storage unit described first storage area, described first storage unit is read, to judge the data mode of described first storage unit by described sensitization array; And input the second address signal to described second decoding scheme, according to described second address signal, second storage unit corresponding with described second address signal is chosen from several storage unit described second storage area, described second storage unit is read, to judge the data mode of described second storage unit by described sensitization array.
Particularly, read storage unit corresponding to described address signal by described sensitization array, to judge the data mode of the storage unit that described address signal is corresponding, can comprise the following steps:
S231, the storage unit applying passed through to described address signal is corresponding read voltage, with the reading electric current making described sensitization array obtain storage unit corresponding to described address signal;
S232, judge the size of the reading electric current of the storage unit that described address signal is corresponding and the reference current of reference unit;
S233, according to judged result, judge the data mode of the storage unit that described address signal is corresponding.
As mentioned above, the first storage area and the second storage area share same sensitization array, and therefore, storer of the present invention can realize the function that same sensitization array reads the storage unit of the first storage area and the second storage area.In the production of reality, the method of above-mentioned reading Memory Storage Unit, not only effectively reduce the area that takies of sensitization array with saving chip area, reduce chip manufacturing cost, and can also ensure that the readwrite performance of storer does not reduce while reduction area.
In memory, data store with " 1 " and " 0 " two kinds of forms, when reading the data of Memory Storage Unit, need to judge that Memory Storage Unit is eraseable memory unit or memory cells, just need to be read storage unit by sensitization array at this, from the different aspect of storer, the method reading Memory Storage Unit is described in detail below, wherein, a kind of storer that storer provides for embodiment one.
Storage unit for storer reads, and the data mode reading the cell stores referred to storer judges, storage unit comprises memory cells and eraseable memory unit, and corresponding data mode is " 0 " and " 1 ".
When the structure of storer is up-down structure, the first decoding scheme wherein and the second decoding scheme are array decoding circuit.The storage unit Cell of the 1st row is arranged with the 2nd of the first storage area reading storer the
12for example, concrete steps are:
(1) first row decoding scheme carries out address signal decoding according to the first address signal of input, and to obtain the address of Destination Storage Unit, and choose this Destination Storage Unit from the first storage area, wherein, Destination Storage Unit is Cell
12, be positioned at the 2nd of the first storage area and arrange the 1st row;
(2) read method of sense amplifier (SA) circuit to Destination Storage Unit in sensitization array has a variety of, adopt in the upper method applying to read voltage of the grid (gate) of storage unit in the present embodiment, by storage unit being converted into the electric current of different size, processed by SA circuit again, thus judge that storage unit is " 1 " cell or " 0 " cell on earth.Particularly, at this Destination Storage Unit Cell
12grid apply read voltage, namely at this Cell
12the sense bit line connected applies voltage, to obtain this Destination Storage Unit Cell
12reading electric current;
(3) from reference unit, obtain reference current, particularly, the storage unit that the 2nd in the second storage area arranges the 1st row is Destination Storage Unit Cell
12reference unit, the voltage of this reference unit is reference voltage, and the electric current of this reference unit is reference current;
(4) SA circuit compares storage unit Cell
12reading electric current and the size of reference current of reference unit, when the reading electric current of storage unit is greater than the reference current of reference unit, give tacit consent to this storage unit Cell
12data mode be " 1 ", namely this storage unit is eraseable memory unit, and when the reading electric current of storage unit is less than reference current, the data mode giving tacit consent to this storage unit is " 0 ", and namely storage unit is memory cells;
(5) by the comparison of SA circuit to the size of the reference current of the reference unit corresponding to the reading electric current of the m × n of a first storage area storage unit and storage unit, judge the data mode of each storage unit, to judge that this storage unit is as memory cells or eraseable memory unit, completes the process of the reading to Memory Storage Unit.
Said process is the structure of storer when being up-down structure, to the reading of the storage unit of the first storage area of storer, accordingly, when the storage unit of the second storage area of storer is read, storage unit identical with the reading cells position of this second storage area in the first storage area is as reference unit, concrete reading process is identical with the reading process of said memory cells, does not repeat at this.
A kind of method reading Memory Storage Unit provided by the invention, decoding and addressing target storage unit is carried out by array decoding circuit, know the position of this Destination Storage Unit in storage area, when reading the reading electric current of Destination Storage Unit, using storage unit identical with the position of this Destination Storage Unit in another storage area as reference unit, the size of electric current and reference unit reference current is read again by SA circuit comparison object storage unit, judge the data mode of Destination Storage Unit, judge that Destination Storage Unit is as eraseable memory unit or memory cells with this, the judgement to the judgement of each storage unit of the first storage area and each storage unit to the second storage area can be met at this sensitization array simultaneously.
The method of reading Memory Storage Unit provided by the invention, while storage chip decreases a sensitization array area, can also ensure that the reading performance of storer does not reduce, storer corresponding to the method has the advantage that chip area reduces and chip manufacturing cost reduces, and ensure that the reading performance that can not reduce storer simultaneously.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (11)
1. a storer, is characterized in that, comprising: storage area, decoding scheme and sensitization array;
Described storage area, for storing data, wherein, described storage area comprises the first storage area and the second storage area, and described first storage area and described second storage area comprise several storage unit respectively;
Described decoding scheme, for the address signal according to input, from described storage area, choose the storage unit corresponding with described address signal, wherein, described decoding scheme comprises the first decoding scheme and the second decoding scheme;
Described sensitization array, for reading storage unit corresponding to described address signal, to judge the data mode of the storage unit that described address signal is corresponding;
Described first decoding scheme is connected between described first storage area and described sensitization array, and described second decoding scheme is connected between described second storage area and described sensitization array.
2. storer according to claim 1, is characterized in that, the capacity of described first storage area and described second storage area is equal.
3. storer according to claim 1, is characterized in that, the data mode of the storage data of described storage area comprises: the first data mode and the second data mode;
Wherein, described first data mode is " 1 ", and described second data mode is " 0 ".
4. storer according to claim 3, is characterized in that, when described first data mode is " 1 ", corresponding storage unit is eraseable memory unit;
When described second data mode is " 0 ", corresponding storage unit is memory cells.
5. storer according to claim 1, is characterized in that, described first decoding scheme and described second decoding scheme are array decoding circuit.
6. storer according to claim 1, is characterized in that, described sensitization array is made up of several sense amplifier circuit;
Wherein, described sense amplifier circuit, for reading the storage unit of described first storage area, and for reading the storage unit of described second storage area.
7. storer according to claim 5, it is characterized in that, when described first decoding scheme and described second decoding scheme are array decoding circuit, described storer is connected to form in accordance with the order from top to bottom successively by described first storage area, described first decoding scheme, described sensitization array, described second decoding scheme and described second storage area; Or
Described storer is connected to form in accordance with the order from top to bottom successively by described second storage area, described second decoding scheme, described sensitization array, described first decoding scheme and described first storage area.
8. the storer according to any one of claim 1 ~ 7, is characterized in that, described storer is NOR flash memory or NAND quick-flash memory.
9. read a method for Memory Storage Unit, for reading the storer according to any one of claim 1-8, it is characterized in that, comprising:
To decoding scheme Input Address signal, wherein, described decoding scheme comprises the first decoding scheme and the second decoding scheme;
According to described address signal, the storage unit corresponding with described address signal is chosen from described storage area, wherein, described storage area comprises the first storage area and the second storage area, and described first storage area and described second storage area comprise several storage unit respectively;
Storage unit corresponding to described address signal is read, to judge the data mode of the storage unit that described address signal is corresponding by described sensitization array.
10. method according to claim 9, it is characterized in that, the first address signal is inputted to described first decoding scheme, according to described first address signal, first storage unit corresponding with described first address signal is chosen from several storage unit described first storage area, described first storage unit is read, to judge the data mode of described first storage unit by described sensitization array; And
The second address signal is inputted to described second decoding scheme, according to described second address signal, second storage unit corresponding with described second address signal is chosen from several storage unit described second storage area, described second storage unit is read, to judge the data mode of described second storage unit by described sensitization array.
11. methods according to claim 9, is characterized in that, read storage unit corresponding to described address signal by described sensitization array, to judge the data mode of the storage unit that described address signal is corresponding, comprising:
Apply to read voltage, with the reading electric current making described sensitization array obtain storage unit corresponding to described address signal by the storage unit corresponding to described address signal;
Judge the size of the reading electric current of the storage unit that described address signal is corresponding and the reference current of reference unit;
According to judged result, judge the data mode of the storage unit that described address signal is corresponding.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060203547A1 (en) * | 2005-03-09 | 2006-09-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| KR20070004333A (en) * | 2005-07-04 | 2007-01-09 | 삼성전자주식회사 | Semiconductor memory device performing multi word line disturb test operation |
| CN1963948A (en) * | 2005-11-08 | 2007-05-16 | 株式会社东芝 | Semiconductor memory device with mos transistors and method of controlling the same |
| US20100118616A1 (en) * | 2008-11-11 | 2010-05-13 | Chung Hoe-Ju | Semiconductor memory device |
-
2014
- 2014-07-18 CN CN201410345320.0A patent/CN105374393A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060203547A1 (en) * | 2005-03-09 | 2006-09-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| KR20070004333A (en) * | 2005-07-04 | 2007-01-09 | 삼성전자주식회사 | Semiconductor memory device performing multi word line disturb test operation |
| CN1963948A (en) * | 2005-11-08 | 2007-05-16 | 株式会社东芝 | Semiconductor memory device with mos transistors and method of controlling the same |
| US20100118616A1 (en) * | 2008-11-11 | 2010-05-13 | Chung Hoe-Ju | Semiconductor memory device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109448771A (en) * | 2018-12-25 | 2019-03-08 | 江苏时代全芯存储科技有限公司 | Memory device |
| CN109448771B (en) * | 2018-12-25 | 2023-08-15 | 北京时代全芯存储技术股份有限公司 | Memory device |
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