CN105359103A - 一种存储器资源优化方法和装置 - Google Patents

一种存储器资源优化方法和装置 Download PDF

Info

Publication number
CN105359103A
CN105359103A CN201480037674.7A CN201480037674A CN105359103A CN 105359103 A CN105359103 A CN 105359103A CN 201480037674 A CN201480037674 A CN 201480037674A CN 105359103 A CN105359103 A CN 105359103A
Authority
CN
China
Prior art keywords
program
llc
partition strategy
working set
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480037674.7A
Other languages
English (en)
Other versions
CN105359103B (zh
Inventor
刘磊
包云岗
吴承勇
冯晓兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Institute of Computing Technology of CAS
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201810316306.6A priority Critical patent/CN108845960B/zh
Priority to CN201480037674.7A priority patent/CN105359103B/zh
Publication of CN105359103A publication Critical patent/CN105359103A/zh
Application granted granted Critical
Publication of CN105359103B publication Critical patent/CN105359103B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3433—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment for load management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0653—Monitoring storage devices or systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3471—Address tracing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/282—Partitioned cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/653—Page colouring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G06F3/0605—Improving or facilitating administration, e.g. storage management by facilitating the interaction with a user or administrator
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Human Computer Interaction (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System (AREA)

Abstract

本发明的实施例提供一种存储器资源优化方法和装置，涉及计算机领域，解决了现有多级存储器资源之间存在的相互影响问题，优化了现有单一的划分机制。具体方案为：通过页着色技术获得工作集中各程序的性能数据，结合访存频度得到各程序的分类，根据各程序的分类选择工作集对应的页着色划分策略，并将页着色划分策略输入操作系统内核，完成相应的着色划分处理。本发明用于结合工作集特点消除或降低进程、线程在存储资源上的相互干扰，提高了计算机的整机性能。

Description

PCT国内申请，说明书已公开。

Claims (14)

  1. PCT国内申请，权利要求书已公开。
CN201480037674.7A 2013-10-23 2014-10-22 一种存储器资源优化方法和装置 Active CN105359103B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201810316306.6A CN108845960B (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置
CN201480037674.7A CN105359103B (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CN201310503238.1A CN104572493A (zh) 2013-10-23 2013-10-23 一种存储器资源优化方法和装置
CN2013105032381 2013-10-23
PCT/CN2014/089194 WO2015058695A1 (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置
CN201480037674.7A CN105359103B (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201810316306.6A Division CN108845960B (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置

Publications (2)

Publication Number Publication Date
CN105359103A true CN105359103A (zh) 2016-02-24
CN105359103B CN105359103B (zh) 2018-06-26

Family

ID=52992282

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201310503238.1A Pending CN104572493A (zh) 2013-10-23 2013-10-23 一种存储器资源优化方法和装置
CN201810316306.6A Active CN108845960B (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置
CN201480037674.7A Active CN105359103B (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置

Family Applications Before (2)

Application Number Title Priority Date Filing Date
CN201310503238.1A Pending CN104572493A (zh) 2013-10-23 2013-10-23 一种存储器资源优化方法和装置
CN201810316306.6A Active CN108845960B (zh) 2013-10-23 2014-10-22 一种存储器资源优化方法和装置

Country Status (12)

Country Link
US (2) US9857980B2 (zh)
EP (2) EP3040868B1 (zh)
JP (1) JP6143277B2 (zh)
KR (1) KR101761301B1 (zh)
CN (3) CN104572493A (zh)
AU (1) AU2014339450B2 (zh)
BR (1) BR112016007492B8 (zh)
CA (1) CA2927372C (zh)
MX (1) MX356304B (zh)
RU (1) RU2631767C1 (zh)
SG (1) SG11201602325VA (zh)
WO (1) WO2015058695A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104572493A (zh) * 2013-10-23 2015-04-29 华为技术有限公司 一种存储器资源优化方法和装置
CN105068940B (zh) * 2015-07-28 2018-07-31 北京工业大学 一种基于Bank划分的自适应页策略确定方法
CN106919516B (zh) * 2015-12-24 2020-06-16 辰芯科技有限公司 Ddr地址映射系统和方法
CN107797941B (zh) * 2016-09-06 2020-07-07 华为技术有限公司 针对查找树的缓存着色内存分配方法和装置
US10515017B2 (en) 2017-02-23 2019-12-24 Honeywell International Inc. Memory partitioning for a computing system with memory pools
US20190095329A1 (en) * 2017-09-27 2019-03-28 Intel Corporation Dynamic page allocation in memory
US10366007B2 (en) 2017-12-11 2019-07-30 Honeywell International Inc. Apparatuses and methods for determining efficient memory partitioning
US10679173B2 (en) 2018-02-19 2020-06-09 Rpmanetworks Holdings End to end logistic chain tracking and control of shipping containers
US10895985B1 (en) * 2018-05-29 2021-01-19 Amazon Technologies, Inc. Real-time estimation of working sets
KR102340444B1 (ko) 2019-12-24 2021-12-16 고려대학교 산학협력단 모놀리식 3D 집적 기술 기반 NoC 구조를 활용한 GPU 캐시 바이패스 방법 및 장치
JP2021170241A (ja) * 2020-04-16 2021-10-28 富士通株式会社 情報処理装置及び制御プログラム
CN112540934B (zh) * 2020-12-14 2022-07-29 山东师范大学 保证多个延迟关键程序共同执行时服务质量的方法及系统
US12026393B2 (en) 2020-12-17 2024-07-02 Electronics And Telecommunications Research Institute Apparatus and method for selecting storage location based on data usage
CN112799809B (zh) * 2021-01-26 2023-12-26 南京大学 基于高速缓存着色的资源共享和隔离的混合关键实时系统
CN112799817A (zh) * 2021-02-02 2021-05-14 中国科学院计算技术研究所 一种微服务资源调度系统和方法
KR102558935B1 (ko) * 2021-08-09 2023-07-24 (주)에스유지 블록체인을 이용한 수산물 이력관리 및 통계분석 시스템

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7434002B1 (en) * 2006-04-24 2008-10-07 Vmware, Inc. Utilizing cache information to manage memory access and cache utilization
US20080313420A1 (en) * 2007-06-15 2008-12-18 Microsoft Corporation Managing working set use of a cache via page coloring
CN101719105A (zh) * 2009-12-31 2010-06-02 中国科学院计算技术研究所 一种多核系统中对内存访问的优化方法和系统
CN102663115A (zh) * 2012-04-16 2012-09-12 中国人民大学 基于页面染色技术的内存数据库访问优化方法
CN103136120A (zh) * 2012-12-31 2013-06-05 北京北大众志微系统科技有限责任公司 行缓冲管理策略确定方法和装置、bank划分方法和装置

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000339220A (ja) * 1999-05-27 2000-12-08 Nippon Telegr & Teleph Corp <Ntt> キャッシュブロック予約方法およびキャッシュブロック予約機能付きコンピュータシステム
US6654859B2 (en) * 2001-07-26 2003-11-25 International Business Machines Corporation NUMA page selection using coloring
US6910106B2 (en) * 2002-10-04 2005-06-21 Microsoft Corporation Methods and mechanisms for proactive memory management
US8914606B2 (en) * 2004-07-08 2014-12-16 Hewlett-Packard Development Company, L.P. System and method for soft partitioning a computer system
US7664796B2 (en) * 2004-10-13 2010-02-16 Microsoft Corporation Electronic labeling for offline management of storage devices
US20060259733A1 (en) 2005-05-13 2006-11-16 Sony Computer Entertainment Inc. Methods and apparatus for resource management in a logically partitioned processing environment
US20070143315A1 (en) * 2005-12-21 2007-06-21 Alan Stone Inter-partition communication in a virtualization environment
US9390031B2 (en) 2005-12-30 2016-07-12 Intel Corporation Page coloring to associate memory pages with programs
US7581064B1 (en) * 2006-04-24 2009-08-25 Vmware, Inc. Utilizing cache information to manage memory access and cache utilization
US7512768B2 (en) * 2006-07-21 2009-03-31 Intel Corporation Dynamically sharing a stack between different code segments
WO2009075177A1 (ja) 2007-12-12 2009-06-18 Nec Corporation メモリ再配置システムおよびメモリ再配置方法
US8209493B2 (en) * 2008-03-26 2012-06-26 Intel Corporation Systems and methods for scheduling memory requests during memory throttling
US8274521B2 (en) 2009-05-08 2012-09-25 Oracle America, Inc. System available cache color map
US9063825B1 (en) * 2009-09-21 2015-06-23 Tilera Corporation Memory controller load balancing with configurable striping domains
US8880682B2 (en) * 2009-10-06 2014-11-04 Emc Corporation Integrated forensics platform for analyzing IT resources consumed to derive operational and architectural recommendations
US8327085B2 (en) * 2010-05-05 2012-12-04 International Business Machines Corporation Characterizing multiple resource utilization using a relationship model to optimize memory utilization in a virtual machine environment
CN101916230A (zh) * 2010-08-11 2010-12-15 中国科学技术大学苏州研究院 基于划分感知和线程感知的末级高速缓存的性能优化方法
US20120079501A1 (en) * 2010-09-27 2012-03-29 Mark Henrik Sandstrom Application Load Adaptive Processing Resource Allocation
US20120059983A1 (en) * 2010-09-03 2012-03-08 David Wilkins Nellans Predictor-based management of dram row-buffers
US8621649B1 (en) * 2011-03-31 2013-12-31 Emc Corporation Providing a security-sensitive environment
US8966171B2 (en) * 2012-04-16 2015-02-24 Renmin University Of China Access optimization method for main memory database based on page-coloring
CN103077128B (zh) * 2012-12-29 2015-09-23 华中科技大学 一种多核环境下的共享缓存动态划分方法
CN104572493A (zh) * 2013-10-23 2015-04-29 华为技术有限公司 一种存储器资源优化方法和装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7434002B1 (en) * 2006-04-24 2008-10-07 Vmware, Inc. Utilizing cache information to manage memory access and cache utilization
US20080313420A1 (en) * 2007-06-15 2008-12-18 Microsoft Corporation Managing working set use of a cache via page coloring
CN101719105A (zh) * 2009-12-31 2010-06-02 中国科学院计算技术研究所 一种多核系统中对内存访问的优化方法和系统
CN102663115A (zh) * 2012-04-16 2012-09-12 中国人民大学 基于页面染色技术的内存数据库访问优化方法
CN103136120A (zh) * 2012-12-31 2013-06-05 北京北大众志微系统科技有限责任公司 行缓冲管理策略确定方法和装置、bank划分方法和装置

Also Published As

Publication number Publication date
US20180011638A1 (en) 2018-01-11
CN108845960A (zh) 2018-11-20
MX2016005088A (es) 2016-08-03
AU2014339450A1 (en) 2016-04-21
US9857980B2 (en) 2018-01-02
MX356304B (es) 2018-05-23
CA2927372C (en) 2018-02-13
BR112016007492A8 (pt) 2020-03-03
JP2016540290A (ja) 2016-12-22
BR112016007492B1 (pt) 2022-07-12
EP3388947A1 (en) 2018-10-17
SG11201602325VA (en) 2016-05-30
EP3040868A1 (en) 2016-07-06
BR112016007492B8 (pt) 2022-07-26
EP3388947B1 (en) 2020-01-15
KR101761301B1 (ko) 2017-07-25
CN108845960B (zh) 2023-12-29
EP3040868A4 (en) 2016-11-23
JP6143277B2 (ja) 2017-06-07
AU2014339450B2 (en) 2016-11-10
CA2927372A1 (en) 2015-04-30
US9983793B2 (en) 2018-05-29
BR112016007492A2 (pt) 2017-08-01
WO2015058695A1 (zh) 2015-04-30
CN104572493A (zh) 2015-04-29
EP3040868B1 (en) 2017-12-13
US20160239213A1 (en) 2016-08-18
KR20160055273A (ko) 2016-05-17
RU2631767C1 (ru) 2017-09-26
CN105359103B (zh) 2018-06-26

Similar Documents

Publication Publication Date Title
CN105359103A (zh) 一种存储器资源优化方法和装置
Liu et al. A software memory partition approach for eliminating bank-level interference in multicore systems
US20150067262A1 (en) Thread cache allocation
US9098406B2 (en) Managing addressable memory in heterogeneous multicore processors
CN108647155B (zh) 一种基于深度学习的多级cache共享的方法和装置
US20120290789A1 (en) Preferentially accelerating applications in a multi-tenant storage system via utility driven data caching
US20090132769A1 (en) Statistical counting for memory hierarchy optimization
EP3846036B1 (en) Matrix storage method, matrix access method, apparatus and electronic device
US20240231653A1 (en) Memory management method and apparatus, processor, and computing device
US10579519B2 (en) Interleaved access of memory
Fang et al. Research on cache partitioning and adaptive replacement policy for CPU-GPU heterogeneous processors
US20140310461A1 (en) Optimized and parallel processing methods with application to query evaluation
CN115328821B (zh) 基于GPU的可重构Cache系统、访存系统及访存方法
TWI420311B (zh) 基於集合分模組之快取記憶體之分割方法
Hao et al. A partition-merge based cache-conscious parallel sorting algorithm for CMP with shared cache
Liu Optimizing Memory Systems for High Efficiency in Computing Clusters
KR20240123185A (ko) 메모리 장치 및 그 동작 방법
Ali et al. CRITICAL ANALYSIS OF 3D MANYCORE MEMORY ARCHITECTURE USING MAPREDUCE
EP4441622A1 (en) Dynamic strategy based parallelization of user requests
Bensberg et al. Parallel Aggregation and Join Computation in NewDB–Project Status October 2010–
Fogli et al. Towards NUMA-Aware Distributed Query Engines

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB03 Change of inventor or designer information

Inventor after: Liu Lei

Inventor after: Wu Chengyong

Inventor after: Feng Xiaobing

Inventor before: Liu Lei

Inventor before: Bao Yungang

Inventor before: Wu Chengyong

Inventor before: Feng Xiaobing

COR Change of bibliographic data
C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20160616

Address after: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen

Applicant after: Huawei Technologies Co., Ltd.

Applicant after: Institute of Computing Technology, Chinese Academy of Sciences

Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen

Applicant before: Huawei Technologies Co., Ltd.

GR01 Patent grant
GR01 Patent grant