CN105338218B - A kind of the zero-order image suppressing method and its circuit of digital hologram - Google Patents
A kind of the zero-order image suppressing method and its circuit of digital hologram Download PDFInfo
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Abstract
The present invention provides the zero-order image suppressing method and its circuit of a kind of digital hologram, and method includes: to obtain digital hologram diagram data；Order according to filter carries out frame window division, getting frame window data to the digital hologram diagram data；Order according to filter carries out the division of pixel window to the frame window data, obtains hologram pixel data；According to the coefficient of filter, convolution sum operation is carried out to the two-dimensional hologram pixel data, and export operation result.The present invention is based on FPGA integrated chips and filter to realize that the zero-order image of digital hologram inhibits treatment process to significantly improve the treatment effeciency of image by the realization of hardware circuit mode, it is made to have real-time；It can restore the parallel processing capability of information image again simultaneously.
Description
Technical field
The present invention relates to digital hologram process fields, particularly relate to a kind of zero-order image suppressing method of digital hologram
And its circuit.
Background technique
Digital Holography is a kind of to replace traditional record dry plate to remember using photoelectric detectors such as charge coupled cells
The amplitude and phase mehtod for recording the light wave of three-dimension object, by the Object light wave diffraction information by the three-dimension object of above-mentioned record
After the acquired card A/D conversion of the interference pattern of object light and reference light wave, it is stored in computer in the form of digital hologram, passes through
Computer simulation optical diffraction process rebuilds the technology of object light field in the Virtual Space of computer, realizes the holography of object again
Now and processing, number have low manufacture cost, image taking speed fast compared with traditional optical holography, and record and reproduction are flexible special
Point.
The Digital Holography of the prior art is realized based on computer software programs, due in off-axis digital holography system
Joined reference light wave in system recording process and be modulated, in digital reconstruction picture will comprising zero-order image and ± 1 grade of diffraction image, zero
Grade is much bigger as beam intensity ratio ± 1 grade diffraction image light intensity, forms very strong interference to diffraction image, reduces the number of original object light field
Quality reproduction；In order to improve digital reproduction image quality amount, the off-axis digital holography system of the prior art all can be first before digital reconstruction
Carry out zero-order image inhibition processing, common zero-order image inhibits processing method to have: (1) object light and reference light intensity distribution are directly eliminated
Method；(2) the primary any phase shift method of reference light；(3) unique step phase shift method etc..
It is known that FIR filter can be made Strict linear phase, and it can have arbitrary amplitude characteristic, and
The unit sample respo of FIR filter is time-limited, therefore must be stable.Inhibit off-axis digital using FIR filter
Zero-order image in hologram only need to pre-process a width digital hologram with digital image processing method in airspace, algorithm letter
It is single, and be significantly improved to image quality measurer is rebuild.
Digital Holography based on software realization, data processing speed is slow, while it is intrinsic to lose information optics again
Parallel processing capability, and the hardware platform based on PC machine is unable to satisfy digital hologram system intelligent, miniaturization, lightness
Application development demand.Therefore, it is necessary to a kind of Real-Time Filtering demand that can satisfy the inhibition of digital hologram zero-order image is provided,
The zero-order image suppressing method and its circuit of the intrinsic parallel processing capability of the information optics that improvement is lost by software realization simultaneously.
Summary of the invention
The technical problems to be solved by the present invention are: providing the zero-order image suppressing method and its electricity of a kind of digital hologram
Road, meets the Real-Time Filtering demand of digital hologram zero-order image inhibition, and is provided simultaneously with parallel processing capability.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention are as follows:
A kind of zero-order image suppressing method of digital hologram is provided, comprising:
Obtain digital hologram diagram data；
Order according to filter carries out frame window division, getting frame window data to the digital hologram diagram data；
Order according to filter carries out the division of pixel window to the frame window data, obtains hologram pixel data；
According to the coefficient of filter, convolution sum operation is carried out to the two-dimensional hologram pixel data, and export operation knot
Fruit.
The beneficial effects of the present invention are: the program software form based on microcomputer is different from the prior art and realizes digital hologram
In the mode that figure zero-order image inhibits, there are data processing speeds slowly, does not have real-time, the intrinsic parallel processing capability of information optics
The deficiencies of forfeiture.The present invention provides the zero-order image suppressing method and its circuit of a kind of digital hologram, is handled based on pixel data
Device and filter circuit realize that the zero-order image of digital hologram inhibits treatment process, realize zero by above-mentioned hardware circuit mode
Grade is handled as inhibition, significantly improves the treatment effeciency of image, it is made to have real-time；Simultaneously again can restore information image and
Row processing capacity.
Detailed description of the invention
Fig. 1 is a kind of flow diagram of the zero-order image suppressing method of digital hologram of the present invention；
Fig. 2 is a kind of flow diagram of the zero-order image suppressing method of digital hologram of the embodiment of the invention；
Fig. 3 is the flow diagram of convolution sum operation in the embodiment of the invention；
Fig. 4 is the overall structure block diagram that a kind of zero-order image of digital hologram of the present invention inhibits system；
Fig. 5 is the structural block diagram of zero-order image suppression circuit in the embodiment of the invention；
Fig. 6 is the structural schematic diagram of zero-order image suppression circuit in the embodiment of the invention；
Fig. 7 is the recording process index path of off-axis digital holography in the embodiment of the present invention three；
Fig. 8 is the zero-order image filtering schematic diagram of the embodiment of the present invention three.
Label declaration:
1, DSP main control processor；2, zero-order image suppression circuit；3, CCD image sensor；
21, pixel data processor；22, filter circuit；23, buffer storage；
211, it seals in and goes out module；212, pixel data refresh module；
221, poly phase module；222, distributed algorithm module；223, summation module.
Specific embodiment
To explain the technical content, the achieved purpose and the effect of the present invention in detail, below in conjunction with embodiment and cooperate attached
Figure is explained.
The most critical design of the present invention is: being realized at the zero-order image inhibition of digital hologram based on hardware circuit mode
Reason process significantly improves the treatment effeciency of image, it is made to have real-time；It can restore the parallel processing of information image again simultaneously
Ability.
Explanation of technical terms of the present invention:
Fig. 1 and Fig. 2 is please referred to, in this, it is assumed that the order of filter is R*R；
The present invention provides a kind of zero-order image suppressing method of digital hologram, comprising:
Obtain digital hologram diagram data；
Order according to filter carries out frame window division, getting frame window data to the digital hologram diagram data；
Order according to filter carries out the division of pixel window to the frame window data, obtains hologram pixel data；
According to the coefficient of filter, convolution sum operation is carried out to the two-dimensional hologram pixel data, and export operation knot
Fruit.
As can be seen from the above description, the beneficial effects of the present invention are: by hardware circuit mode by digital hologram diagram data
Order according to filter is successively converted into frame window data and pixel window data, realizes and turns one-dimensional hologram data
It is changed to two-dimensional hologram pixel data；Two-dimensional hologram pixel data are carried out at convolution sum filtering by filter again
Reason, the hologram data exported after filtering processing reduce the interference of right ± 1 grade of diffraction image of zero-order image in digital reproduction picture, realize
The zero-order image of digital hologram diagram data inhibits so that the digital hologram diagram data being based ultimately upon after zero-order image filtering processing and into
Capable digital reconstruction can obtain the original and conjugate image of more preferable reconstruction quality；The treatment effeciency of image is significantly improved, it is made
Has real-time；It can restore the parallel processing capability of information image again simultaneously.
It is further, described that " order according to filter carries out the division of pixel window to the frame window data, obtains complete
Cease figure pixel data " specifically:
Obtain a serial holoframe window data；
Order according to filter carries out the division of pixel window to described one serial holoframe window data, obtain with
The corresponding parallel hologram pixel data of the order of filter；
Pixel window described in synchronous refresh obtains next parallel hologram pixel data of the hologram data.
It can be seen from the above, the present invention, which is realized, is converted into R parallel holograms for serial holoframe window data
The output of pixel data, and by pixel window described in continuous synchronous refresh, realize the synchronous brush of R pixels arranged side by side
Newly；In conjunction with convolution sum operation, realizes and hologram pixel data are wholly converted into two dimension corresponding with filter coefficient
Hologram pixel data.
Referring to Fig. 3, it is further, it is described " according to the coefficient of filter, the two-dimensional hologram pixel data to be carried out
Convolution sum operation, and export operation result " specifically:
Poly phase calculating is carried out to the hologram pixel data, the hologram data after obtaining each group poly phase；
According to distributed algorithm, product is carried out to the coefficient of hologram data and filter after each group poly phase
And calculating；
Summation operation is carried out to the sum of products of all distributed algorithm module outputs, exports calculated result.
It can be seen from the above, the concurrency of data processing can be effectively improved by poly phase operation, operation speed is improved
Degree；By distributed algorithm, hardware circuit scale can be reduced, be easier to realize pipeline processes, circuit is improved and execute speed.
It is further, described that " order according to filter carries out frame window division to the digital hologram diagram data, obtains
Frame window data " specifically:
In buffer zone, the order according to filter carries out frame window division to the digital hologram diagram data, obtains
One frame window data；
Export the frame window data；
Empty the data in the buffer zone.
It can be seen from the above, the setting of the buffer area, realizes the caching to digital holographic image data, it is preferred to use
The mode of First Input First Output is stored, and the efficiency of data buffer storage can not only be improved, and can help to pixel data processor
Processing.
It is further, described that " order according to filter carries out frame window division to the digital hologram diagram data, obtains
Frame window data；Order according to filter carries out the division of pixel window to the frame window data, obtains hologram image prime number
According to " specifically:
The digital hologram diagram data is classified as a frame by R and carries out frame window division, frame window moves from left to right, by step
The update of frame window data is carried out away from the rule for a column；
One pixel is classified as by R row * R to the frame window data that get of update and carries out the division of pixel window, pixel window from
On move down, by step-length be a line rule carry out pixel window data update, obtain corresponding hologram pixel data.
It can be seen from the above, the present invention realize quickly one-dimensional hologram data is converted into it is corresponding with filter coefficient
Two-dimensional hologram pixel data, significantly improve the concurrency of data processing.
Further, the frame window divides, pixel window divides and the process of convolution sum operation is by may be programmed core
Piece is realized.
It can be seen from the above, the present invention is based on the hologram data zero-order images that programmable chip is realized to inhibit treatment process, fill
Point using programmable chip repeatable editor's characteristic, being provided simultaneously with circuit, algorithm upgrading is convenient, and the development cycle is short, exploitation at
This low advantage.
Please refer to fig. 4 to fig. 6, another technical solution provided by the invention are as follows:
A kind of zero-order image suppression circuit 2 of digital hologram, including DSP main control processor 1 further include pixel data processing
Device 21 and filter circuit 22, the DSP main control processor 1, pixel data processor 21 and filter circuit 22 are sequentially connected,
The filter circuit 22 is also connect with the DSP main control processor 1；
The DSP main control processor 1, for obtaining digital hologram diagram data；
The pixel data processor 21 carries out frame window to the digital hologram diagram data for the order according to filter
Mouth divides, getting frame window data；And the order according to filter carries out the division of pixel window to the frame window data, obtains
Take hologram pixel data；
The filter carries out convolution sum fortune to the two-dimensional hologram pixel data for the coefficient according to filter
It calculates, output operation result to the DSP main control processor 1.
It can be seen from the above, this programme has the beneficial effect that the zero-order image for realizing digital hologram based on hardware circuit
Inhibit processing in real time, improves the parallel processing capability by being lost when software realization, improve execution efficiency.
It further, further include buffer storage 23；The pixel data processor 21 includes interconnected seals in simultaneously
Module 211 and pixel data refresh module 212 out, the buffer storage 23 are separately connected the DSP main control processor 1 and institute
It states and seals in and go out module 211；The pixel data refresh module 212 connects the filter；
The buffer storage 23 carries out frame window to the digital hologram diagram data for the order according to filter and draws
Point, obtain a frame window data；Export the frame window data to it is described seal in and locate module after, empty data；
It is described to seal in and go out module 211, pixel window is carried out to the frame window data for the order according to filter
Mouth divides, and obtains a serial hologram pixel data；And the order according to filter is to described one serial holoframe
Window data carries out the division of pixel window, obtains parallel hologram pixel data；
The pixel data refresh module 212 obtains the hologram data for pixel window described in synchronous refresh
Next parallel hologram pixel data.
It can be seen from the above, the buffer storage 23 realizes the number for sending 1 module of DSP main control processor entirely
The caching for ceasing image data, facilitates the processing of pixel data processor 21.Sealing in and locating module realizes hologram image pixel
One-dimensional turn of two dimension of data；Pixel data refresh module 212 realizes the synchronous refresh of pixel data, obtains R*R rank hologram
As pixel data.
Further, buffer storage 23 is that FIFO lines up memory；The buffer storage 23, pixel data processor
21 and filter circuit 22 be integrated in fpga chip.
It can be seen from the above, the mode that FIFO lines up memory First Input First Output can significantly improve the effect of data buffer storage
Rate facilitates the processing of pixel data processor 21；And the programmable features based on programmable integrated chip, facilitate algorithm liter
Grade, and can reduce development cycle and development cost.
Further, the filter circuit 22 includes poly phase module 221 interconnected, distributed algorithm module
222 and summation module 223；The poly phase module 221 is connect with the pixel data refresh module 212, the summation mould
Block 223 is connect with the DSP main control processor 1；
The poly phase module 221 obtains each group for carrying out poly phase calculating to the hologram pixel data
Hologram data after poly phase；
The distributed algorithm module 222, for foundation distributed algorithm, to the hologram after each group poly phase
The coefficient of data and filter carries out sum of products calculating；
The summation module 223, the sum of products for exporting to all distributed algorithm modules 222 carry out summation fortune
It calculates, output calculated result to the DSP main control processor 1.
Seen from the above description, using multiphase filter structure, it can reduce the sample rate of filter, Optimal Filter is realized
Structure, is effectively reduced the data operation quantity of zero-order image suppression circuit 2, and raising operation efficiency and system signal handle real-time
Property；It is calculated using each group of data after distributed algorithm (DA) realization poly phase and respective filter system sum of products；Effectively subtract
Few hardware circuit scale, improves flexibility.
The embodiment of the present invention one are as follows:
Please refer to fig. 4 to fig. 6, a kind of circuit for realizing that the zero-order image of digital hologram inhibits based on FPGA integrated chip；
Including sequentially connected CCD image sensor 3, DSP main control processor 1 and zero-order image suppression circuit 2；
The zero-order image suppression circuit 2 includes the FPGA integrated chip connecting with DSP main control processor 1；The FPGA collection
At being integrated with sequentially connected buffer storage 23, pixel data processor 21 and filter circuit 22 on chip；The buffering
Memory 23 is connect with DSP main control processor 1 and pixel data processor 21 respectively；
The pixel data processor 21 seals in including sequentially connected and goes out module 211 and pixel data refresh module
212；It is described seal in and go out module 211 connect with the buffer storage 23；The pixel data refresh module 212 and filter
Circuit 22 connects；
The filter circuit 22 includes sequentially connected poly phase module 221, distributed algorithm module 222 and summation
Module 223；The poly phase module 221 is connect with the pixel data processor 21；
The output of the summation module 223 is connect with the DSP main control processor 1.
The major function of CCD image sensor 3 obtains by object light and is formed by digital hologram with reference to the interference of light
Each pixel gray value；DSP main control processor 1, which is mainly responsible for, carries out the pixel grey scale information that CCD image sensor 3 transmits
Storage, and be responsible for the filter result for calling FPGA zero-order image to inhibit filter circuit and carry out original object light field digital reconstruction；FPGA zero
Grade mainly completes DSP main control processor 1 as filter circuit and sends the zero-order image filtering of pixel data, and processing result is returned
It returns in DSP main control processor 1.
Specifically, the buffer storage 23 can be FIFO and line up memory, for storing a frame hologram image pixel
Data, when a frame data are disposed, FIFO lines up memory clear-up, prepares to receive next frame data；
Sealing in and going out module 211 for the pixel data processor 21 can be serial-in parallel-out register, for buffering
Serial hologram image pixel in memory 23 is converted to a column of R*R pixel window, realizes the refreshing of a column pixel, i.e., by one
The hologram image of dimension is changed into two-dimensional hologram image；
The pixel data refresh module 212, for completing to seal in and going out in module 211 R column pixel in pixel window
Refresh；
The poly phase module 221 of filter, for according to M times of line direction lower sampling, institute to be decomposed in N times of column direction lower sampling
The data in pixel data refresh module 212 are stated, each group hologram data after constituting poly phase；
The distributed algorithm module 222, for realizing each group of data after poly phase and corresponding FIR filter factor product
And calculating；
The summation module 223, for realizing the summation operation of each group distribution algorithm unit output, and by summed result
It is sent to the DSP main control processor 1.
Embodiment two
It please refers to Fig.1 to Fig.3, a kind of circuit structure based on embodiment one realizes what the zero-order image of digital hologram inhibited
Method；If the order of the Two dimensional FIR Filter for the inhibition of off-axis digital holography figure zero-order image is R*R；Specifically include following step
It is rapid:
(1) digital hologram diagram data is obtained；Order according to filter carries out frame window to the digital hologram diagram data
It divides, getting frame window data；
The digital hologram diagram data that DSP main control processor 1 is sent, which is first sent to FIFO, lines up memory and is buffered
Storage, here, it is preferred that FIFO lines up memory only stores a frame hologram pixel data every time, to improve at image pixel data
Manage efficiency；
Line up in memory in FIFO, digital hologram diagram data is classified as a frame by R and divides frame window, frame window is in number
According to from left to right moving in hologram, step pitch is that the rule of a column carries out data update, when a frame data are disposed, output
Frame window data seal in pixel data processor 21 and go out module 211；It is emptying that FIFO lines up memory, is next frame data
Processing is prepared；
(2) division of pixel window is carried out to the frame window data according to the order of filter, obtains hologram image prime number
According to；
Pixel data processor 21 seals in and goes out after module 211 receives above-mentioned serial frame window data, by R row * R
It is classified as a pixel and carries out the division of pixel window, obtain R parallel hologram pixel data；Pass through pixel data refresh window
Control pixel window moves from the top down on frame window, carries out the same of R row pixel window data by the rule that step-length is a line
Step updates；The hologram pixel data of parallel R row R column are obtained, and are exported to the poly phase module 221 of filter.
By above-mentioned, realize one-dimensional hologram pixel data conversion at corresponding with the coefficient of the filter
Two-dimensional hologram pixel data.
(4) according to the coefficient of filter, convolution sum operation is carried out to the two-dimensional hologram pixel data, and export fortune
Calculate result；
Referring to Fig. 3, poly phase module 221 receives the hologram pixel data of parallel R row R column, according to line direction M
Sampling under times, N times of the column direction lower principle sampled carry out poly phase, the hologram data after obtaining each group poly phase；It is logical
Poly phase is crossed, the concurrency of data processing can be effectively improved, improves arithmetic speed；
After distributed algorithm module 222 receives the hologram data after above-mentioned each group poly phase, according to distributed algorithm,
Sum of products calculating is carried out to the coefficient of hologram data and filter after each group poly phase；Hardware circuit is reduced with this
Module is easier to realize pipeline processes, improves circuit and executes speed；
Summation operation, operation knot are carried out to the sum of products that all distributed algorithm modules 222 export by summation module 223
Filter result is returned to DSP as final filter result, the final zero-order image inhibition processing for realizing digital hologram by fruit
Original object light field digital reconstruction is carried out in main control processor 1.
Embodiment three
It provides and a kind of specific is processed based on what embodiment one and embodiment two realized that the zero-order image of digital hologram inhibits
Journey；
In the case where object light and angle between reference are met certain condition, diffraction light is not present and interferes with each other off-axis digital holography figure,
It is a kind of most-often used hologram recording method.
The recording process optical path of off-axis digital holography is as shown in Figure 7.
Hologram plane light intensity is object light U (x in Fig. 7H,yH) and reference light R (xH,yH) interference as a result, formula table can be used
It is shown as:
IH(xH,yH)=[U (xH,yH)+R(xH,yH)]·[U(xH,yH)+R(xH,yH)]* (1)
To IH(xH,yH) Direct Digital reconstruction, rebuilding image planes will be present Zero-order diffractive picture and original image and conjugate image, and
Zero-order image causes severe jamming to original and conjugate image, affects the digital reconstruction quality of original object light field.In order to reduce number
The interference of right ± 1 grade of diffraction image of zero-order image in reproduction image can design Two dimensional FIR Filter and carry out zero-order image filter to digital hologram
Digital reconstruction is carried out after wave again, higher reconstruction quality will be obtained by carrying out digital reconstruction with the filtered digital hologram of zero-order image
Original and conjugate image.
Refering to Fig. 8, zero-order image filtering be may be expressed as:
Wherein, IH(m, n) indicates that the digital hologram after holographic facet discretization, Y (m, n) indicate the filtered number of zero-order image
Word hologram；H (m, n) is the Unit sample response for the Two dimensional FIR Filter of digital hologram zero-order image filtering；
Since zero-order image component is located at low frequency position in the frequency spectrum of off-axis digital holography figure, one can be designed first thus
One-dimensional FIR high-pass filter of good performance recycles frequency transformation design method to be transformed to two-dimentional FIR high-pass filter.
Specifically, realizing the design of frequency transformation filter using function ftrans2 in MATLAB；Call format H=
Ftrans2 (B, T), B are one-dimensional FIR filters, and T is the frequency transformation that one-dimensional FIR filter is transformed to Two dimensional FIR Filter
Matrix.
In order to realize that digital hologram zero-order image inhibits processing in real time, by the zero-order image restrainable algorithms based on FIR filter
It is mapped to FPGA programmable chip, and algorithm is realized by hardware chip, improves the information light by being lost when software realization
Intrinsic parallel processing capability is learned, execution efficiency is improved；And the repeatable editor of FPGA is utilized, algorithm upgrading is convenient, the development cycle
Short, development cost is low.
FPGA programmable chip implements the process flow of zero-order image filtering refering to Fig. 2, Fig. 3 and the step of embodiment two
Rapid process.
In conclusion the zero-order image suppressing method and circuit of a kind of digital hologram provided by the invention, based on hardware electricity
The zero-order image that road realizes digital hologram inhibits processing in real time, improves the parallel processing energy by being lost when software realization
Power improves execution efficiency；Moreover, the operand of system is effectively reduced in the application of multiphase filter structure, improve at system signal
The real-time of reason；Furthermore hardware circuit scale is effectively reduced using distributed algorithm, flexibility is high, improves circuit and executes speed
Degree；Finally, repeatable editor's characteristic of FPGA integrated chip, being provided simultaneously with circuit, algorithm upgrading is convenient, and the development cycle is short, opens
The advantage for sending out at low cost.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalents made by bright specification and accompanying drawing content are applied directly or indirectly in relevant technical field, similarly include
In scope of patent protection of the invention.
Claims (8)
1. a kind of zero-order image suppressing method of digital hologram characterized by comprising
Obtain digital hologram diagram data；
Order according to filter carries out frame window division, getting frame window data to the digital hologram diagram data；
Order according to filter carries out the division of pixel window to the frame window data, obtains hologram pixel data；
Poly phase calculating is carried out to the hologram pixel data, the hologram data after obtaining each group poly phase；
According to distributed algorithm, sum of products meter is carried out to the coefficient of hologram data and filter after each group poly phase
It calculates；
Summation operation is carried out to the sum of products of all distributed algorithms output, exports calculated result.
2. a kind of zero-order image suppressing method of digital hologram according to claim 1, which is characterized in that " the foundation
The order of filter carries out the division of pixel window to the frame window data, obtains hologram pixel data " specifically:
Obtain a serial holoframe window data；
Order according to filter carries out the division of pixel window to described one serial holoframe window data, obtains parallel
Hologram pixel data；
Pixel window described in synchronous refresh obtains next parallel hologram pixel data of the hologram data.
3. a kind of zero-order image suppressing method of digital hologram according to claim 1, which is characterized in that " the foundation
The order of filter carries out frame window division, getting frame window data to the digital hologram diagram data " specifically:
In buffer zone, the order according to filter carries out frame window division to the digital hologram diagram data, obtains a frame
Window data；
Export the frame window data；
Empty the data in the buffer zone.
4. a kind of zero-order image suppressing method of digital hologram according to claim 1, which is characterized in that set the filtering
The order of device is R*R, then described " order according to filter carries out frame window division to the digital hologram diagram data, obtains
Frame window data；Order according to filter carries out the division of pixel window to the frame window data, obtains hologram image prime number
According to " specifically:
The digital hologram diagram data is classified as a frame by R and carries out frame window division, frame window moves from left to right, is by step pitch
The rule of one column carries out the update of frame window data；
One pixel is classified as by R row * R to the frame window data that get of update and carries out the division of pixel window, pixel window on to
Lower movement is that the rule of a line carries out the update of pixel window data by step-length, obtains corresponding hologram pixel data.
5. according to a kind of zero-order image suppressing method of digital hologram described in claim 1-4 any one, which is characterized in that
The frame window divides, pixel window divides and the process of convolution sum operation is realized by programmable chip.
6. a kind of zero-order image suppression circuit of digital hologram, including DSP main control processor, which is characterized in that further include pixel
Data processor and filter circuit, the DSP main control processor, pixel data processor and filter circuit are sequentially connected,
The filter circuit is also connect with the DSP main control processor, and the filter circuit includes poly phase interconnected
Module, distributed algorithm module and summation module；The poly phase module is connect with the pixel data processor, described to ask
It is connect with module with the DSP main control processor；
The DSP main control processor, for obtaining digital hologram diagram data；
The pixel data processor carries out frame window to the digital hologram diagram data for the order according to filter and draws
Point, getting frame window data；And the order according to filter carries out the division of pixel window to the frame window data, obtains complete
Cease figure pixel data；
The filter carries out convolution sum operation, output fortune to two-dimensional hologram pixel data for the coefficient according to filter
Result is calculated to the DSP main control processor；
The poly phase module obtains each group multiphase point for carrying out poly phase calculating to the hologram pixel data
Hologram data after solution；
The distributed algorithm module, for according to distributed algorithm, to after each group poly phase hologram data and
The coefficient of filter carries out sum of products calculating；
The summation module, for carrying out summation operation, output meter to the sum of products of all distributed algorithm module outputs
Result is calculated to the DSP main control processor.
7. a kind of zero-order image suppression circuit of digital hologram according to claim 6, which is characterized in that further include buffering
Memory；The pixel data processor include it is interconnected seal in and go out module and pixel data refresh module, it is described slow
Memory is rushed to be separately connected the DSP main control processor and described seal in and go out module；The pixel data refresh module connection
The filter；
The buffer storage carries out frame window division to the digital hologram diagram data for the order according to filter, obtains
Take a frame window data；Export the frame window data to it is described seal in and go out module after, empty data；
It is described to seal in and go out module, the division of pixel window is carried out to the frame window data for the order according to filter,
Obtain a serial hologram pixel data；And according to filter order to described one serial hologram pixel data into
Row pixel window divides, and obtains parallel hologram pixel data；
The pixel data refresh module obtains under the hologram data together for pixel window described in synchronous refresh
Capable hologram pixel data.
8. a kind of zero-order image suppression circuit of digital hologram according to claim 7, which is characterized in that the buffering is deposited
Reservoir is that FIFO lines up memory；The buffer storage, pixel data processor and filter circuit are integrated in programmable core
In piece.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510776694.2A CN105338218B (en) | 2015-11-13 | 2015-11-13 | A kind of the zero-order image suppressing method and its circuit of digital hologram |
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| CN201510776694.2A CN105338218B (en) | 2015-11-13 | 2015-11-13 | A kind of the zero-order image suppressing method and its circuit of digital hologram |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841730A (en) * | 2010-05-28 | 2010-09-22 | 浙江大学 | Real-time stereoscopic vision implementation method based on FPGA |
| CN103235495A (en) * | 2013-04-07 | 2013-08-07 | 哈尔滨工程大学 | Inhibition method of off-axis digital holographic zero-order images based on Gaussian kernel function |
| CN103473742A (en) * | 2013-09-11 | 2013-12-25 | 天津工业大学 | Novel method for suppressing noise in reflective off-axis digital holographic reconstructive image |
| CN104698801A (en) * | 2015-04-07 | 2015-06-10 | 南开大学 | Method for eliminating digital holographic zero-order image through one-step fixed angle phase shift |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101841730A (en) * | 2010-05-28 | 2010-09-22 | 浙江大学 | Real-time stereoscopic vision implementation method based on FPGA |
| CN103235495A (en) * | 2013-04-07 | 2013-08-07 | 哈尔滨工程大学 | Inhibition method of off-axis digital holographic zero-order images based on Gaussian kernel function |
| CN103473742A (en) * | 2013-09-11 | 2013-12-25 | 天津工业大学 | Novel method for suppressing noise in reflective off-axis digital holographic reconstructive image |
| CN104698801A (en) * | 2015-04-07 | 2015-06-10 | 南开大学 | Method for eliminating digital holographic zero-order image through one-step fixed angle phase shift |
Non-Patent Citations (3)
| Title |
|---|
| 图像边缘检测系统的硬件设计;金建平;《信息化研究》;20090430;第35卷(第4期);第52-54页 |
| 基于FPGA的分布式算法FIR滤波器的设计实现;王学梅;《世界电子元器件》;20050728;第65-68页 |
| 基于有限脉冲响应滤波器的数字全息零级像消除;刘雯雯;《光学学报》;20080531;第28卷(第5期);第857-859页 |
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