CN105336681A - Fabrication method of semiconductor device and semiconductor device - Google Patents
Fabrication method of semiconductor device and semiconductor device Download PDFInfo
- Publication number
- CN105336681A CN105336681A CN201410363920.XA CN201410363920A CN105336681A CN 105336681 A CN105336681 A CN 105336681A CN 201410363920 A CN201410363920 A CN 201410363920A CN 105336681 A CN105336681 A CN 105336681A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- groove
- shallow trench
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a fabrication method of a semiconductor device and the semiconductor device. The fabrication method comprises the steps as follows: a substrate is provided; a buried layer is formed in the substrate; the substrate is etched to form first shallow trenches; the depths of the first shallow trenches are smaller than that of the buried layer in the substrate and the substrate between the adjacent first shallow trenches is taken as an active region; an isolating material layer covering the first shallow trenches and the substrate is formed; the isolating material layer and the substrate are etched to form a groove for exposing partial buried layer; the first shallow trenches are located between the active regions and the groove; and a filling material layer is formed in the groove. According to the fabrication method, the damage to the first shallow trenches and the filing material layer in the forming process of the first shallow trenches is avoided, so that the performance of the semiconductor device is improved.
Description
Technical field
The application relates to semiconductor integrated circuit manufacture technology field, in particular to a kind of manufacture method and semiconductor device of semiconductor device.
Background technology
In the manufacturing process of semiconductor device, such as in the manufacturing process of logical device or high tension apparatus etc., usually need to form embedding layer in the substrate with in the vertical direction isolation active area and substrate, then etched substrate forms the groove be connected with embedding layer, and forms encapsulant layer in a groove.In above-mentioned encapsulant layer, material can be isolated material, to isolate active area and substrate in the horizontal.In above-mentioned encapsulant layer, material can also comprise the isolated material be formed on groove inner wall and the electric conducting material being arranged in isolated material, wherein be formed at isolated material on groove inner wall for isolating active area and substrate in the horizontal, the electric conducting material in isolated material is used for forming electrical connection between embedding layer and peripheral circuit.
Fig. 1 to Fig. 5 shows the manufacture method of existing semiconductor device.This manufacture method comprises the following steps: first, provides the substrate 10 ' being formed with embedding layer 20 ' as shown in Figure 1; Then, form mask layer 40 ' on the surface of substrate 10 ', and then form basal body structure as shown in Figure 2; Next, according to form with substrate 10 ' groove 51 ' be connected with embedding layer 20 ' for the downward etching mask layer 40 ' in position of the groove 51 ' be connected with embedding layer 20 ' formed, and at the middle formation encapsulant layer 52 ' of groove 51 ', and then form basal body structure as shown in Figure 3; Next, etch successively formed groove and for be formed with source region position between mask layer 40 ' and substrate 10 ' form shallow trench 61 ', remove mask layer 40 ', and form isolated substance preparation layers 70 ' on shallow trench 61 ' with the substrate surface for being formed with source region, and then form basal body structure as shown in Figure 4; Finally, etching is removed to be positioned at and is formed fleet plough groove isolation structure 71 ' and active area 80 ' for the isolated substance preparation layers 70 ' be formed with on the substrate surface in source region, and then forms basal body structure as shown in Figure 5.
In the manufacture method of above-mentioned semiconductor device, when etching forms shallow trench, be generally dry etching, such as plasma etching.This lithographic method can cause damage to the encapsulant layer that early stage is formed, and can form etch residue on the surface of encapsulant layer, thus affects the carrying out of subsequent technique, and then reduces the performance of semiconductor device.At present, effective solution is not also had for the problems referred to above.
Summary of the invention
The application aims to provide a kind of manufacture method and semiconductor device of semiconductor device, to improve the performance of semiconductor device.
To achieve these goals, according to an aspect of the application, provide a kind of manufacture method of semiconductor device, this manufacture method comprises: provide substrate, is formed with embedding layer in substrate; Etched substrate forms the first shallow trench, and the degree of depth of the first shallow trench is less than the degree of depth of embedding layer in substrate, and using the substrate between adjacent first shallow trench as active area; Form the isolated substance layer of covering first shallow trench and substrate; Etching isolated substance layer and substrate, form the groove that part embedding layer is exposed, wherein, the first shallow trench is between active area and groove; Form encapsulant layer in a groove.
Further, the step forming the first shallow trench comprises: form mask layer on a surface of the substrate; Etching mask layer and substrate successively, to form the first shallow trench; Remove remaining mask layer.
Further, forming the step of groove and comprise: etching the surface exposure of isolated substance layer to substrate downwards along the position corresponded to for forming groove, form cross-sectional area and be greater than first through hole of institute for the cross-sectional area of formation groove; And along etched substrate downward in the first through hole, form groove.
Further, after forming the step of encapsulant layer in a groove, this manufacture method also comprises: along the position etching isolated substance layer corresponding to active area, to expose the surface of active area.
Further, in the step of formation first shallow trench, in the substrate of the first shallow trench away from side, active area, form the second shallow trench.
Further, the step forming the first shallow trench and the second shallow trench comprises: form mask layer on a surface of the substrate; Etching mask layer and substrate successively, to form the first shallow trench and the second shallow trench.
Further, formed in the step of isolated substance layer, the first shallow trench, the second shallow trench and remaining mask layer form isolated substance layer.
Further, forming the step of groove and comprise: etching the surface exposure of isolated substance layer to mask layer downwards along the position corresponded to for forming groove, form cross-sectional area and be greater than first through hole of institute for the cross-sectional area of formation groove; Remove mask layer along the first via etch, in isolated substance layer, form the second through hole; Along the downward etched substrate of the second through hole, to form groove.
Further, after forming the step of encapsulant layer in a groove, this manufacture method also comprises: planarization isolated substance layer, to make remaining mask layer surface exposure; And remove remaining mask layer, to expose the surface of active area.
Further, encapsulant layer is spacer material layer; Or encapsulant layer comprises: be formed at the spacer material layer on groove inner wall and the conductive material layer being arranged in spacer material layer.
Further, when encapsulant layer comprises the spacer material layer be formed on groove inner wall and the conductive material layer being arranged in spacer material layer, the step forming encapsulant layer comprises: carry out thermal oxidation to form spacer material layer to the substrate on groove inner wall, and filled conductive material forms conductive material layer in the groove after thermal oxidation; Or deposition forms spacer material layer on the inwall of groove, and form conductive material layer at the groove filled conductive material being formed with spacer material layer.
Further, embedding layer is N-type layer or P-type layer.
Meanwhile, present invention also provides a kind of semiconductor device, this semiconductor device is made by the manufacture method that the application is above-mentioned.
The technical scheme of application the application, the first shallow trench is formed by etched substrate, and using the substrate between adjacent first shallow trench as active area, and then form the groove that part embedding layer is exposed and the encapsulant layer being arranged in groove, thus the damage that the forming process avoiding the first shallow trench causes encapsulant layer, and then improve the performance of semiconductor device.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 shows in the manufacture method of existing semiconductor device, is formed with the cross-sectional view of the substrate of embedding layer;
Fig. 2 shows the cross-sectional view of the matrix after the surface formation mask layer of substrate shown in Figure 1;
Fig. 3 shows the mask layer of etching shown in Fig. 2 downwards and forms with substrate the groove be connected with embedding layer, and forms the cross-sectional view of the matrix after encapsulant layer in a groove;
Fig. 4 show etch successively the groove shown in Fig. 3 and for be formed with source region position between mask layer and substrate form shallow trench, except mask layer, and the cross-sectional view of matrix form isolated substance preparation layers on shallow trench with the substrate surface for being formed with source region after;
Fig. 5 shows etching and removes the isolated substance layer of the position substrate surface for being formed with source region of the substrate surface shown in Fig. 4 to form the cross-sectional view of the matrix behind fleet plough groove isolation structure and active area;
Fig. 6 shows the schematic flow sheet of the manufacture method of the semiconductor device that the application provides;
In the manufacture method of the semiconductor device that a kind of preferred implementation that Fig. 7-1 shows the application provides, be formed with the cross-sectional view of the matrix after the substrate of embedding layer;
Fig. 7-2 shows the cross-sectional view of the matrix form mask layer on the surface of the substrate shown in Fig. 7-1 after;
Fig. 7-3 shows and etches the mask layer shown in Fig. 7-2 and substrate successively to form the first shallow trench, and removes the cross-sectional view of the matrix after remaining mask layer;
Fig. 7-4 shows the cross-sectional view of the matrix after the isolated substance layer forming the first shallow trench shown in coverage diagram 7-3 and substrate;
Fig. 7-5 shows the isolated substance layer shown in etching Fig. 7-4 and substrate, forms the cross-sectional view of the matrix after the groove that part embedding layer is exposed;
Fig. 7-6 shows the cross-sectional view of the matrix form encapsulant layer in the groove shown in Fig. 7-5 after;
Fig. 7-7 shows and etches the isolated substance layer shown in Fig. 7-6 along corresponding to the position of active area, with the cross-sectional view of the matrix behind the surface of exposing active area;
In the manufacture method of the semiconductor device that the another kind of preferred implementation that Fig. 8-1 shows the application provides, be formed with the cross-sectional view of the matrix after the substrate of embedding layer;
Fig. 8-2 shows the cross-sectional view of the matrix form mask layer on the surface of the substrate shown in Fig. 8-1 after;
Fig. 8-3 shows and etches the mask layer shown in Fig. 8-2 and substrate successively, to form the cross-sectional view of the matrix after the first shallow trench and the second shallow trench;
Fig. 8-4 shows the cross-sectional view of the matrix form isolated substance layer on the first shallow trench shown in Fig. 8-3, the second shallow trench and remaining mask layer after;
Fig. 8-5 shows isolated substance layer, mask layer and the substrate shown in etching Fig. 8-4, forms the cross-sectional view of the matrix after the groove that part embedding layer is exposed;
Fig. 8-6 shows the cross-sectional view of the matrix form encapsulant layer in the groove shown in Fig. 8-5 after; And
Fig. 8-7 shows and etches the isolated substance layer shown in Fig. 8-6 and mask layer along corresponding to the position of active area, with the cross-sectional view of the matrix behind the surface of exposing active area.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
As what introduce in background technology, the damage that in existing method, the forming process of the first shallow trench can cause encapsulant layer, and then the performance reducing semiconductor device.Present inventor studies for the problems referred to above, proposes a kind of manufacture method of semiconductor device.As shown in Figure 6, this manufacture method comprises: provide substrate, is formed with embedding layer in substrate; Etched substrate forms the first shallow trench, and the degree of depth of the first shallow trench is less than the degree of depth of embedding layer in substrate, and using the substrate between adjacent first shallow trench as active area; Form the isolated substance layer of covering first shallow trench and substrate; Etching isolated substance layer and substrate, form the groove that part embedding layer is exposed, wherein, the first shallow trench is between active area and groove; Form encapsulant layer in a groove.
Above-mentioned manufacture method forms the first shallow trench by etched substrate, and using the substrate between adjacent first shallow trench as active area, and then form the groove that part embedding layer is exposed and the encapsulant layer being arranged in groove, thus the damage that the forming process avoiding the first shallow trench causes encapsulant layer, and then improve the performance of semiconductor device.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
In the manufacture method of the semiconductor device that a kind of preferred implementation that Fig. 7-1 to Fig. 7-7 shows the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 7-1 to Fig. 7-7, further illustrate the manufacture method of the semiconductor device that the application provides.
First, provide the substrate 10 being formed with embedding layer 20, its structure is as shown in Fig. 7-1.Wherein, embedding layer 20 is the semiconductor material layer that conduction type is contrary with the conduction type of substrate 10.Preferably, when semiconductor material layer is N-type ion implantation, embedding layer 20 is P type ion implantation, and when semiconductor material layer is P type ion implantation, embedding layer 20 is N-type ion implantation.The technique forming above-mentioned embedding layer 20 can be epitaxial growth or ion implantation etc.The material of above-mentioned substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carborundum (SiC), also can be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be other material, the III-V such as such as GaAs.
After completing the step that the substrate 10 being formed with embedding layer 20 is provided, etched substrate 10 forms the first shallow trench 61, the degree of depth of the first shallow trench 61 is less than the degree of depth of embedding layer 20 in substrate 10, and using the substrate 10 between adjacent first shallow trench 61 as active area 30.Preferably, this step comprises: first, and the surface of substrate 10 forms mask layer 40, and then forms the basal body structure as shown in Fig. 7-2; Then, etching mask layer 40 and substrate 10 are to form the first shallow trench 61 successively, and remove remaining mask layer 40, and then form the basal body structure as shown in Fig. 7-3.
The shape of above-mentioned first shallow trench 61 can be shape common in this area, such as inverted trapezoidal or U-shaped etc.Above-mentioned etching can be dry etching, is preferably plasma etching.In the optional execution mode of one, the process conditions of plasma etching are: etching gas is CF
4and CHF
3, etching power is 400 ~ 1000 watts, and etching temperature is 25 ~ 60 DEG C, and etch period is 30 ~ 360 seconds.
Above-mentioned mask layer 40 can adopt mask material common in this area, such as SiN, SiON or SiO
2deng.The technique forming above-mentioned mask layer 40 can be chemical vapour deposition (CVD), sputtering etc.
Complete etched substrate 10 and form the first shallow trench 61, the degree of depth of the first shallow trench 61 is less than the degree of depth of embedding layer 20 in substrate 10, and using the substrate 10 between adjacent first shallow trench 61 as active area 30 step after, form the isolated substance layer 70 of covering first shallow trench 61 and substrate 10, and then form the basal body structure as shown in Fig. 7-4.
Above-mentioned isolated substance layer 70 can be common dielectric material, such as SiO
2, SiN or SiOC etc.The technique forming above-mentioned isolated substance layer 70 can be chemical vapour deposition (CVD) or sputtering etc., and wherein chemical vapour deposition (CVD) comprises plasma reinforced chemical vapour deposition, high-aspect-ratio chemical vapour deposition (CVD) etc.Above-mentioned technique is prior art in this area, does not repeat them here.
After completing the step of the isolated substance layer 70 forming covering first shallow trench 61 and substrate 10, etching isolated substance layer 70 and substrate 10, form the groove 51 that part embedding layer 20 is exposed, wherein, first shallow trench 61 between active area 30 and groove 51, and then forms the basal body structure as shown in Fig. 7-5.Preferably, this step comprises: along corresponding to the surface exposure etching isolated substance layer 70 to substrate 10 for forming the position of groove 51 downwards, forms cross-sectional area and is greater than first through hole of institute for the cross-sectional area of formation groove 51; And along etched substrate 10 downward in the first through hole, form the groove 51 shown in Fig. 7-5.
In the step of above-mentioned etching, utilize the feature that isolated substance layer 70 is different with the material of substrate 10, and adopt the speed of etching isolated substance layer 70 to etch much smaller than the etching gas of the speed of etched substrate 10 substrate, just can realize etching " autoregistration " of substrate 10 material.Meanwhile, different etching gas can be adopted for different etachable material.Such as, SF can be adopted when etching Si substrate 10
6as etching gas, etching SiO
2time can adopt C
4f
8as etching gas, during etching SiN, CHF can be adopted
3or CH
3f is as etching gas.The technique of above-mentioned etching can set according to existing technique, and in the optional execution mode of one, the process conditions of above-mentioned etching are: etching power is 400 ~ 1000 watts, and etching temperature is 25 ~ 60 DEG C, and etch period is 30 ~ 360 seconds.
Complete etching isolated substance layer 70 and substrate 10, form the groove 51 that part embedding layer 20 is exposed, wherein, after the step of the first shallow trench 61 between active area 30 and groove 51, in groove 51, form encapsulant layer 52, and then form the basal body structure as shown in Fig. 7-6.In a preferred embodiment, encapsulant layer 52 is spacer material layer.The now effect of encapsulant layer 52 is for isolating adjacent active area 80 better.Above-mentioned spacer material layer can be dielectric material common in this area, such as SiO
2, SiN, SiC or SiOC etc.The technique forming above-mentioned spacer material layer can be chemical vapour deposition (CVD) or sputtering etc., and wherein chemical vapour deposition (CVD) comprises plasma reinforced chemical vapour deposition or high-aspect-ratio chemical vapour deposition (CVD) etc.Above-mentioned technique is state of the art, does not repeat them here.
In the step of above-mentioned formation encapsulant layer 52, in another preferred embodiment, encapsulant layer 52 comprises the spacer material layer be formed on groove 51 inwall and the conductive material layer being arranged in spacer material layer.Wherein be formed at spacer material layer on groove 51 inwall for isolating adjacent active area 80 and substrate 10 better, the conductive material layer in spacer material layer is used for forming electrical connection between embedding layer 20 and peripheral circuit.Above-mentioned spacer material layer can be dielectric material common in this area, such as SiO
2, SiN, SiC or SiOC etc.Above-mentioned conductive material layer can be polysilicon or metal material (such as Cu or Al etc.).
Form the above-mentioned step including the encapsulant layer 52 of spacer material layer and conductive material layer to comprise: carry out thermal oxidation to form spacer material layer to the substrate 10 on groove 51 inwall; And filled conductive material forms conductive material layer in the groove 51 after thermal oxidation; Or deposition forms spacer material layer on the inwall of groove 51, form conductive material layer at the groove 51 filled conductive material being formed with spacer material layer.Above-mentioned thermal oxidation and depositing operation are state of the art, do not repeat them here.
After completing the step forming encapsulant layer 52 in groove 51, along the position etching isolated substance layer 70 corresponding to active area 30, to expose the surface of active area 30, and then form the basal body structure as shown in Fig. 7-7.Wherein, the technique of etching isolated substance layer 70 can be dry etching etc., and its concrete technology parameter with reference to prior art, can not repeat them here.
In the manufacture method of the semiconductor device that the another kind of preferred implementation that Fig. 8-1 to Fig. 8-7 shows the application provides, the cross-sectional view of the matrix obtained after each step.Below in conjunction with Fig. 8-1 to Fig. 8-7, further illustrate the manufacture method of the semiconductor device that the application provides.
First, provide the substrate 10 being formed with embedding layer 20, its structure is as shown in Fig. 8-1.Wherein, embedding layer 20 is the semiconductor material layer that conduction type is contrary with the conduction type of substrate 10.Preferably, when semiconductor material layer is N-type ion implantation, embedding layer 20 is P type ion implantation, and when semiconductor material layer is P type ion implantation, embedding layer 20 is N-type ion implantation.The technique forming above-mentioned embedding layer 20 can be epitaxial growth or ion implantation etc.The material of above-mentioned substrate 10 can be monocrystalline silicon (Si), monocrystalline germanium (Ge), SiGe (GeSi) or carborundum (SiC), also can be silicon-on-insulator (SOI), germanium on insulator (GOI), or can also be other material, the III-V such as such as GaAs.
After completing the step that the substrate 10 being formed with embedding layer 20 is provided, etched substrate 10 forms the first shallow trench 61 and the second shallow trench 62, and using the substrate 10 between adjacent first shallow trench 61 as active area 30, wherein the second shallow trench is formed in the substrate of the first shallow trench away from side, active area, and the degree of depth of the first shallow trench 61 is less than the degree of depth of embedding layer 20 in substrate 10.Preferably, this step comprises: first, and the surface of substrate 10 forms mask layer 40, and then forms the basal body structure as shown in Fig. 8-2; Then, etching mask layer 40 and substrate 10 are to form the first shallow trench 61 and the second shallow trench 62 successively, and then are formed as figure, the basal body structure shown in 8-3.
The shape of above-mentioned first shallow trench 61 can be shape common in this area, such as inverted trapezoidal or U-shaped etc.Above-mentioned etching can be dry etching, is preferably plasma etching.In the optional execution mode of one, the process conditions of plasma etching are: etching gas is CF
4and CHF
3, etching power is 400 ~ 1000 watts, and etching temperature is 25 ~ 60 DEG C, and etch period is 30 ~ 360 seconds.
Above-mentioned mask layer 40 can adopt mask material common in this area, such as SiN, SiON or SiO
2deng.The technique forming above-mentioned mask layer 40 can be chemical vapour deposition (CVD), sputtering etc.
Complete etched substrate 10 and form the first shallow trench 61 and the second shallow trench 62, and using the substrate 10 between adjacent first shallow trench 61 as active area 30, wherein the second shallow trench is formed in the substrate of the first shallow trench away from side, active area, after the degree of depth of the first shallow trench 61 is less than the step of the degree of depth of embedding layer 20 in substrate 10, form the isolated substance layer 70 of covering first shallow trench 61, second shallow trench 62 and mask layer 40, and then form basal body structure as shown in fig. 8-4.
Above-mentioned isolated substance layer 70 can be common dielectric material, such as SiO
2, SiN or SiOC etc.The technique forming above-mentioned isolated substance layer 70 can be chemical vapour deposition (CVD) or sputtering etc., and wherein chemical vapour deposition (CVD) comprises plasma reinforced chemical vapour deposition, high-aspect-ratio chemical vapour deposition (CVD) etc.Above-mentioned technique is prior art in this area, does not repeat them here.
After completing the step of the isolated substance layer 70 forming covering first shallow trench 61, second shallow trench 62 and mask layer 40, etching isolated substance layer 70, mask layer 40 and substrate 10, form the groove 51 that part embedding layer 20 is exposed, wherein, first shallow trench 61 between active area 30 and groove 51, and then forms the basal body structure as shown in Fig. 8-5.Preferably, this step comprises: along corresponding to the surface exposure etching isolated substance layer 70 to mask layer 40 for forming the position of groove 51 downwards, forms cross-sectional area and is greater than first through hole of institute for the cross-sectional area of formation groove 51; Remove mask layer 40 along the first via etch, in isolated substance layer 70, form the second through hole; Along the downward etched substrate 10 of the second through hole, to form the groove 51 as shown in Fig. 8-5.
In the step of above-mentioned etching, utilize the feature that mask layer 40 is different from the etch rate of substrate 10, and adopt the speed of etching mask layer 40 to etch much smaller than the etching gas of the speed of etched substrate 10 substrate, just can realize etching " autoregistration " for forming the groove 51 be connected with embedding layer 20.Meanwhile, different etching gas can be adopted for different etachable material.Such as, SF can be adopted when etching Si substrate 10
6as etching gas, etching SiO
2time can adopt C
4f
8as etching gas, during etching SiN, CHF can be adopted
3or CH
3f is as etching gas.The technique of above-mentioned etching can set according to existing technique, and in the optional execution mode of one, the process conditions of above-mentioned etching are: etching power is 400 ~ 1000 watts, and etching temperature is 25 ~ 60 DEG C, and etch period is 30 ~ 360 seconds.
Complete etching isolated substance layer 70, mask layer 40 and substrate 10, after forming the step of the groove 51 that part embedding layer 20 is exposed, in groove 51, form encapsulant layer 52, and then form the basal body structure as shown in Fig. 8-6.In a preferred embodiment, encapsulant layer 52 is spacer material layer.The now effect of encapsulant layer 52 is for isolating adjacent active area 80 better.Above-mentioned spacer material layer can be dielectric material common in this area, such as SiO
2, SiN, SiC or SiOC etc.The technique forming above-mentioned spacer material layer can be chemical vapour deposition (CVD) or sputtering etc., and wherein chemical vapour deposition (CVD) comprises plasma reinforced chemical vapour deposition or high-aspect-ratio chemical vapour deposition (CVD) etc.Above-mentioned technique is state of the art, does not repeat them here.
In the step of above-mentioned formation encapsulant layer 52, in another preferred embodiment, encapsulant layer 52 comprises the spacer material layer be formed on groove 51 inwall and the conductive material layer being arranged in spacer material layer.Wherein be formed at spacer material layer on groove 51 inwall for isolating adjacent active area 80 and substrate 10 better, the conductive material layer in spacer material layer is used for forming electrical connection between embedding layer 20 and peripheral circuit.Above-mentioned spacer material layer can be dielectric material common in this area, such as SiO
2, SiN, SiC or SiOC etc.Above-mentioned conductive material layer can be polysilicon or metal material (such as Cu or Al etc.).
Form the above-mentioned step including the encapsulant layer 52 of spacer material layer and conductive material layer to comprise: carry out thermal oxidation to form spacer material layer to the substrate 10 on groove 51 inwall; And filled conductive material forms conductive material layer in the groove 51 after thermal oxidation; Or deposition forms spacer material layer on the inwall of groove 51, form conductive material layer at the groove 51 filled conductive material being formed with spacer material layer.Above-mentioned thermal oxidation and depositing operation are state of the art, do not repeat them here.
After completing the step forming encapsulant layer 52 in groove 51, along the position etching isolated substance layer 70 and the mask layer 40 that correspond to active area 30, to expose the surface of active area 30, and then form the basal body structure as shown in Fig. 8-7.Preferably, this step comprises: planarization isolated substance layer 70, to make remaining mask layer 40 surface exposure; And remove remaining mask layer 40, to expose the surface of active area 30.Flatening process can be chemico-mechanical polishing etc., and the technique removing remaining mask layer 40 can be wet etching etc., and above-mentioned technique is state of the art, does not repeat them here.
Present invention also provides a kind of semiconductor device, the manufacture method of the semiconductor device that this semiconductor device is provided by the application is made.In this semiconductor device, encapsulant layer can not sustain damage, and then improves the performance of semiconductor device.
From above description, can find out, the application's the above embodiments achieve following technique effect: form the first shallow trench by etched substrate, and using the substrate between adjacent first shallow trench as active area, and then form the groove that part embedding layer is exposed and the encapsulant layer being arranged in groove, thus the damage that the forming process avoiding the first shallow trench causes encapsulant layer, and then improve the performance of semiconductor device.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (13)
1. a manufacture method for semiconductor device, is characterized in that, described manufacture method comprises:
Substrate is provided, in described substrate, is formed with embedding layer;
Etch described substrate and form the first shallow trench, the degree of depth of described first shallow trench is less than the degree of depth of described embedding layer in described substrate, and using the described substrate between adjacent described first shallow trench as active area;
Form the isolated substance layer covering described first shallow trench and described substrate;
Etch described isolated substance layer and described substrate, form the groove that the described embedding layer of part is exposed, wherein, described first shallow trench is between described active area and described groove; Encapsulant layer is formed in described groove.
2. manufacture method according to claim 1, is characterized in that, the step forming described first shallow trench comprises:
The surface of described substrate forms mask layer;
Etch described mask layer and described substrate successively, to form described first shallow trench;
Remove remaining described mask layer.
3. manufacture method according to claim 2, is characterized in that, the step forming described groove comprises:
Etching the surface exposure of described isolated substance layer to described substrate along corresponding to downwards for forming the position of described groove, forming cross-sectional area and being greater than first through hole of institute for the cross-sectional area of formation groove; And
Etch described substrate downwards along in described first through hole, form described groove.
4. manufacture method according to claim 3, it is characterized in that, form the step of described encapsulant layer in described groove after, described manufacture method also comprises: etch described isolated substance layer, to expose the surface of described active area along the position corresponding to described active area.
5. manufacture method according to claim 1, is characterized in that, in the step forming described first shallow trench, in the described substrate of described first shallow trench away from side, described active area, forms the second shallow trench.
6. manufacture method according to claim 5, is characterized in that, the step forming described first shallow trench and described second shallow trench comprises:
The surface of described substrate forms mask layer;
Etch described mask layer and described substrate successively, to form described first shallow trench and described second shallow trench.
7. manufacture method according to claim 6, is characterized in that, is formed in the step of described isolated substance layer, and described first shallow trench, described second shallow trench and remaining described mask layer form described isolated substance layer.
8. manufacture method according to claim 7, is characterized in that, the step forming described groove comprises:
Etching the surface exposure of described isolated substance layer to described mask layer along corresponding to downwards for forming the position of described groove, forming cross-sectional area and being greater than first through hole of institute for the cross-sectional area of formation groove;
Remove described mask layer along described first via etch, in described isolated substance layer, form the second through hole;
Described substrate is etched downwards, to form described groove along described second through hole.
9. manufacture method according to claim 8, is characterized in that, form the step of described encapsulant layer in described groove after, described manufacture method also comprises:
Isolated substance layer described in planarization, to make remaining described mask layer surface exposure; And
Remove remaining described mask layer, to expose the surface of described active area.
10. manufacture method according to any one of claim 1 to 9, is characterized in that,
Described encapsulant layer is spacer material layer; Or
Described encapsulant layer comprises: be formed at the spacer material layer on described groove inner wall and the conductive material layer being arranged in described spacer material layer.
11. manufacture methods according to claim 10, it is characterized in that, when described encapsulant layer comprises the described spacer material layer be formed on described groove inner wall and the described conductive material layer being arranged in described spacer material layer, the step forming described encapsulant layer comprises:
Thermal oxidation is carried out to form described spacer material layer to the described substrate on described groove inner wall, and filled conductive material forms described conductive material layer in the described groove after described thermal oxidation; Or
On the inwall of described groove, deposition forms described spacer material layer, and forms described conductive material layer at the described groove filled conductive material being formed with described spacer material layer.
12. manufacture methods according to any one of claim 1 to 9, is characterized in that, described embedding layer is N-type layer or P-type layer.
13. 1 kinds of semiconductor device, is characterized in that, the manufacture method of described semiconductor device according to any one of claim 1 to 12 is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410363920.XA CN105336681B (en) | 2014-07-28 | 2014-07-28 | The production method and semiconductor devices of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410363920.XA CN105336681B (en) | 2014-07-28 | 2014-07-28 | The production method and semiconductor devices of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105336681A true CN105336681A (en) | 2016-02-17 |
| CN105336681B CN105336681B (en) | 2018-05-04 |
Family
ID=55287120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410363920.XA Active CN105336681B (en) | 2014-07-28 | 2014-07-28 | The production method and semiconductor devices of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105336681B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1030363A2 (en) * | 1999-02-18 | 2000-08-23 | Chartered Semiconductor Manufacturing Pte Ltd. | Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors |
| CN101288173A (en) * | 2005-08-25 | 2008-10-15 | 飞思卡尔半导体公司 | Semiconductor devices employing poly-filled trenches |
| CN101764092A (en) * | 2008-12-23 | 2010-06-30 | 国际商业机器公司 | Semiconductor structure, forming and operating method thereof |
| CN101764104A (en) * | 2008-12-23 | 2010-06-30 | 国际商业机器公司 | Semiconductor structures, methods of manufacturing the same, and methods of operating the same. |
-
2014
- 2014-07-28 CN CN201410363920.XA patent/CN105336681B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1030363A2 (en) * | 1999-02-18 | 2000-08-23 | Chartered Semiconductor Manufacturing Pte Ltd. | Integration of bipolar and CMOS devices for sub-0.1 micrometer transistors |
| CN101288173A (en) * | 2005-08-25 | 2008-10-15 | 飞思卡尔半导体公司 | Semiconductor devices employing poly-filled trenches |
| CN101764092A (en) * | 2008-12-23 | 2010-06-30 | 国际商业机器公司 | Semiconductor structure, forming and operating method thereof |
| CN101764104A (en) * | 2008-12-23 | 2010-06-30 | 国际商业机器公司 | Semiconductor structures, methods of manufacturing the same, and methods of operating the same. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105336681B (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI514580B (en) | Semiconductor device and method for manufacturing the same | |
| US9087870B2 (en) | Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same | |
| TWI498998B (en) | Method of forming finned semiconductor devices with trench isolation | |
| TW201806155A (en) | Semiconductor structures and methods for fabricating the same | |
| JP2020507211A (en) | Gate structure of semiconductor device and manufacturing method | |
| CN106531686B (en) | Interconnection structure, method of manufacturing the same, and semiconductor device | |
| TWI509710B (en) | Semiconductor devices having improved gate height uniformity and methods for fabricating same | |
| US10199392B2 (en) | FinFET device having a partially dielectric isolated fin structure | |
| TW201725658A (en) | Method of manufacture semiconductor structure | |
| CN104425377B (en) | The forming method of CMOS transistor | |
| CN106558614A (en) | Semiconductor structure and forming method thereof | |
| CN105551958B (en) | The forming method of transistor | |
| CN104835774A (en) | Semiconductor device preparation method | |
| CN103730404B (en) | The manufacturing method of shallow trench isolation | |
| JP2009522800A (en) | Manufacturing method of semiconductor device and semiconductor device obtained by this method | |
| US8524566B2 (en) | Methods for the fabrication of integrated circuits including back-etching of raised conductive structures | |
| CN103367394A (en) | Semiconductor device and manufacturing method | |
| CN103681275B (en) | A kind of semiconductor device with highly controllable fin and preparation method | |
| US20150162248A1 (en) | Method for the formation of dielectric isolated fin structures for use, for example, in finfet devices | |
| CN105336681A (en) | Fabrication method of semiconductor device and semiconductor device | |
| CN104091779A (en) | Shallow trench isolation structure forming method | |
| US20120126244A1 (en) | Shallow trench isolation structure and method for forming the same | |
| CN103681339A (en) | Fin field effect transistor preparation method | |
| CN103165461B (en) | Make the method for semiconductor device | |
| CN109148580B (en) | FinFET device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |