CN105322971B - For the LDPC code word of next-generation radio broadcasting and coding method and codec - Google Patents

Abstract

Present invention discloses LDPC code word, corresponding encoder, decoder and the coding method of a kind of repetition accumulation type (S-IRA) of novel structuring, the structure of code word is H=[H '₁Π P '], H '₁For information bit matrix, P ' is check bit matrix, and Π P ' is to do capable transformation to the check bit matrix, wherein information bit matrix H '₁Including multiple circulation submatrix p_i,j, each circulation submatrix can only be unit circle excursion matrix or full null matrix.Using technical solution of the present invention, pass through a large amount of analogue simulations, the information bit matrix structure for being more suitable for a kind of LDPC code word of HSS decoding algorithm than the prior art is had found, and using encoder, the decoder of this LDPC code, improves the performance of LDPC code word.In addition, the present invention, which opens, discloses a kind of coding method for corresponding to above-mentioned S-IRA structure, encoder.

Description

For the LDPC code word of next-generation radio broadcasting and coding method and codec

Technical field

The present invention relates to a kind of LDPC code word and using encoder, the decoder, corresponding coding method of the code word, more It says to body, is related to a kind of S-IRA LDPC code word and corresponding encoder, decoder and coding method.

Background technique

Low density parity check codewords (Low density Parity Check, LDPC) can mainly divide according to its structure For two classes, one kind is random code word, most classic to surely belong to MacKay code, and there are also the various code words that special webpage provides him for he (MacKay 1999)(Richardson2001)(Luby 2001)(Richardson and Urbanke 2001)；Other one Class is the code word designed based on algebraic combination structure (Combinatorial).Random code word can have very good approximation to Shannon The limit, but due to the randomness of ' 1 ' distribution, lead to the design of encoder and the design of decoder and do not have parallel or rule Rule property is feasible, so being not suitable for needing to have certain throughput systems, therefore is not also just widely used.

And the problem of appearance very good solution of the code word based on algebraic combination structure this respect, among these, there is one kind Code word based on finite field (Finite Geometry) design has good performance (Y.Kou and S.Lin 2001), but The shortcomings that being this kind of code word is since its H-matrix density is relatively high (big row rearranges weight), so being based on belief propagation when using A kind of algorithm when, complexity is very high.And another kind of quasi-cyclic code word (Quasi-cyclic LDPC, QC-LDPC) is a kind of The very important code word based on algebraic combination construction.The main construction of QC-LDPC code word is based on the sub- square of quasi-cyclic unit Battle array.(J.L.Fan2000)(R.M.Tanner 2001)(R.M.Tanner 2001)(T.Okamura 2003)(R.M.Tanner 2004) this quasi-cyclic unit submatrix structure is very suitable to realize the hardware of parallel work-flow, for example, realize degree of parallelism it is big, into And the decoder of high-throughput.Traditional this QC-LDPC code word is improved and is gulped down although the decoder for being suitble to degree of parallelism high is realized Rate is spat, but may be not sparse by the generator matrix that reverse method has obtained QC structure, even if sparse, use generation Matrix come encode to obtain check bit be not it is obvious, to be obtained by seeking system of linear equations, therefore traditional QC-LDPC The encoder of code word or relative complex.In order to solve this problem, the structuring that scholar Zhang and Ryan are proposed first Repeat accumulated code (Structured Irregular Repeat Accumulator code, S-IRA) LDPC code word (Zhang And Ryan 2006), which, can be in the method for very simple and effective while being suitble to the realization of high parallel decoder To complete to encode.This kind of codeword structure has following features, and matrix part corresponding to information bit is made of quasi- circulation submatrix, And what matrix part corresponding to check bit was made of bidiagonal matrix.

S-IRA code word has been widely used in major communication standard at present, mainly includes, and European second generation number is wide It is serial (ETSI, 2006, DVBT22009, DVB-C22009, DVB-NGH 2012) to broadcast TV transmission standards DVB；IEEE 802.11n WLAN standard (IEEE 802.11n 2009)；IEEE802.11e wireless wide area network standard (IEEE 802.16e2006)；China Digital TV ground transmission standard (DTTB) (GB20600-2006)；Mobile multimedia broadcasting (CMMB 2006)；The near-earth deep space communication system (CCSDS2007) of North America CCSDS；And standard of some disk storage equipments etc.. From the point of view of the developing state of entire international coverage digital communicating field, also has more standards and or in the future use LDPC Code word.

From standard submitted at present, especially commercial extremely successful DVBT2, DVBS2 standard, and recently From the point of view of just fixing standard and commercially having the DVB-NGH standard (end of the year 2012 final version) of bright prospects, the S-IRA code that uses Check matrix master structure to be used corresponding to word is as follows:

H=[∏ H₁P]

Wherein H₁It is the corresponding matrix part of information bit, ∏ is to H₁A some form of row transformation, and P is school Test the corresponding matrix part of bit.

And:

Be byThe circulation submatrix of size or 0 matrix composition.

For example, P_i,jThe first structure it is as follows:

At this point, P_i,jIt is made of two unit offset battle arrays.Further Ground, P_i,jIt can also be and be made of N number of unit circle matrix, the integer of N > 2.

P_i,jSecond of structure it is as follows:

At this time P_i,jIt is made of full null matrix.

Due to P_i,jIt can be made of more than one unit circle battle array, it is caused to be not appropriate for HSS (Horizontal Shuffle scheduling) decoding algorithm hardware implement.Have in the document of the implementation method of DVBT2 and S2 in this regard It is much mentioned to, and proposes the relevant solution for sacrificing complexity.

And P is the corresponding matrix part of check bit, is following bidiagonal matrix:

Summary of the invention

The purpose of the present invention is intended to provide a kind of S-IRA LDPC code word and corresponding encoder, decoder and coding staff Method, to solve to be not suitable for HSS brought by the structure of the check matrix of S-IRA LDPC code common in the art (Horizontal shuffle scheduling) decoding algorithm influences the problem of entire LDPC code word performance.

This patent proposes a kind of P_i,jOnly 0 or 1 unit circle matrix composition structure.In retention property Under conditions of, it is suitable for HSS and decodes.It proposes the code word and its code table of a kind of design parameter simultaneously, and proposes corresponding coding Method encoder, interpretation method and decoder.

According to above-mentioned purpose, implement a kind of S-IRA LDPC code word for codec of the invention, the knot of code word Structure are as follows: H=[H '₁∏ P '], H '₁For information bit matrix, P ' is check bit matrix, and ∏ P ' is to do row to check bit matrix Transformation.Wherein, information bit matrix H '₁Including multiple circulation submatrix p_i,j, each circulation submatrix can only be unit circle Excursion matrix or full null matrix.

According to above-mentioned purpose, implements a kind of LDPC encoder of the invention, use a kind of LDPC code of S-IRA structure Word, the structure of S-IRA LDPC code word are as follows: H=[H '₁∏ P '], H '₁For information bit matrix, P ' is check bit matrix, ∏ P ' It is that capable transformation is done to check bit matrix.Wherein, information bit matrix H '₁Including multiple circulation submatrix p_i,j, each circulation Submatrix can only be unit circle excursion matrix or full null matrix.

According to above-mentioned purpose, implements a kind of LDPC decoder of the invention, use a kind of LDPC code of S-IRA structure Word, the structure of S-IRA LDPC code word are as follows: H=[H '₁∏ P '], H '₁For information bit matrix, P ' is check bit matrix, ∏ P ' It is that capable transformation is done to check bit matrix.Wherein, information bit matrix H '₁Including multiple circulation submatrix p_i,j, each circulation Submatrix can only be unit circle excursion matrix or full null matrix.

According to above-mentioned main feature, the information bit of inventive encoder, decoder and S-IRA LDPC code word therein Matrix is m row × n-m column matrix:

Wherein each circulation submatrix p_i,jSize be

According to above-mentioned main feature, the check bit of inventive encoder, decoder and S-IRA LDPC code word therein Matrix P ' is m row × m column matrix:It is on its leading diagonal and minor diagonal 1, remaining position is 0.

According to above-mentioned purpose, implement the coding method of S-IRA LDPC code word of the invention the following steps are included:

Obtain information bit { i₀,i₁,i₂,i₃,i₄,i₅,...,i_n-m-1}；

Initiation verification bit p₀=0, p₁=0, p₂=0, p₃=0, p₄=0 ..., p_m-1=0；

By each check bit p_kAnd coupled information bit is 2 He of mould, k=0,1,2 ... m-1, and does weight New arrangement, the check bit sequence after being reset

By the check bit sequence after rearrangementIt does following cumulative:

p′₀=p '₀

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According to above-mentioned purpose, implement LDPC coding method and encoder of the invention, wherein the coding fortune built in encoder Calculate the coding method that module uses the LDPC comprising:

Computation of parity bitsWherein, j=0,1,2,3 ..., m-1；It indicates in low-density surprise In even parity check matrix with p_jAssociated information bit；y_jIt is information bitSerial number, obtain according to the following formula:

Wherein, q=320, m=14400, x indicate to participate in the address of the cumulative information bit of Parity Check Bits, the table of x Are as follows:

Code table: code rate 3/4m=14400, code length n=57600

It has found by a large amount of analogue simulations using technical solution of the present invention and is more suitable for HSS than the prior art A kind of information bit matrix knot of the S-IRA LDPC code word of (Horizontal shuffle scheduling) decoding algorithm Structure, and using encoder, the decoder of this S-IRA LDPC code, to produce unexpected S-IRA LDPC code word Promotion in performance.

Specific embodiment

Technical solution of the present invention is further illustrated below by embodiment.

Difference of HSS (the Horizontal Shuffle Scheduling) algorithm compared to flood (Flooding) algorithm It is, Flooding algorithm is must be after all rows have operated, and obtained data are disposably updated, then It uses in next iteration, and in HSS algorithm in certain an iteration, it can be immediately per the result obtained after operating line by line It updates, uses still in the operation of row next time of current iteration, the convergence rate of decoding algorithm can be greatly improved in this way. On the other hand, (m is check matrix for HSS algorithm only needs to save n (n is code length) Soft Inform ation sums data and m × 2 Line number) the result soft value information of row operation saves chip areas much more very compared to Flooding algorithm.

But existing HSS algorithm, when selection recycles sub-block, circulation sub-block is not usually unit sub-block, but two Or more than two unit sub-blocks, this certainly will lead to the conflict of internal storage access during parallel work-flow.This is because such as Fruit circulation sub-block is made of more than two unit sub-blocks, then there are two meetings when recycling sub-block when parallel-by-bit operates Capable row operation input requires to read same memory simultaneously, and after having operated while writing same memory.This did not both have There is the original intention for reaching HSS algorithm, also results in internal storage conflict.

Therefore, the shortcomings that being based on LDPC code word structure in existing standard, is the circulation in information bit matrix specifically Submatrix may lead to be not suitable for the problem of HSS decoding algorithm is realized by being made of multiple circulating unit battle arrays, and the present invention proposes one The structure of the new S-IRA LDPC code word of kind, the structure of check matrix are as follows:

H=[H '₁∏P′]

Wherein, H '₁It is information bit matrix, P ' is check bit matrix, and ∏ P ' is one done to check bit matrix P ' A some form of row transformation.

Information bit matrix H '₁It is a m row × n-m column matrix, specific structure is as follows:

In the present invention, information bit matrix H '₁Including multiple circulation submatrix p_i,j, H '₁Each of the sub- square of circulation Battle array p_i,jSize beEach circulation submatrix can only be unit circle excursion matrix or full null matrix, i.e., here H '₁It is by L × JThe unit circle excursion matrix of size or 0 matrix are constituted.Here unit circle offset Matrix, which refers to, recycles what offset to the right obtained by an equal amount of unit matrix.

According to above-mentioned p_i,jThe restriction of structure is available, circulation submatrix p of the invention_i,jIt is only possible to be the following two kinds Specific structure type:

1)P at this time_i,jIt is made of unit circle excursion matrix.

2)P at this time_i,jIt is to be made of full null matrix.

On the other hand, in order to cooperate information bit matrix H '₁Structure, check bit matrix P ' of the invention is a m The matrix of row × m column, specific structure are as follows:

Check bit matrix P ' is a kind of special dual-diagonal matrix it can be seen from above structure, is led on diagonal all It is ' 1 ', is also ' 1 ' on minor diagonal, is ' 0 ' on the rest part position of each row, column.

In addition a kind of LDPC encoder is also disclosed in the present invention, what is used is exactly above-mentioned S-IRALDPC code word, specific next It says, the specific structure of check matrix is:

H=[H '₁∏ P '], wherein H '₁For information bit matrix, P ' is check bit matrix, and ∏ P ' is to check bit Matrix does capable transformation.Particularly, information bit matrix H '₁Including multiple circulation submatrix p_i,j, each circulation submatrix can only It is unit circle excursion matrix or full null matrix.

In addition a kind of LDPC decoder is also disclosed in the present invention, what is used is exactly above-mentioned S-IRA LDPC code word, specifically For, the specific structure of check matrix is:

H=[H '₁∏ P '], wherein H '₁For information bit matrix, P ' is check bit matrix, and ∏ P ' is to check bit Matrix does capable transformation.Particularly, information bit matrix H '₁Including multiple circulation submatrix p_i,j, each circulation submatrix can only It is unit circle excursion matrix or full null matrix.

Since encoder and decoder of the invention are all made of LDPC code word disclosed above, LDPC code word its He discloses details characteristic in the above specification, and explanation is not repeated herein.

In addition, key step is as follows the invention also discloses the coding method of above-mentioned LDPC code word:

Step S1: obtaining information bit, and it is { i that known information bit, which is arranged,₀,i₁,i₂,i₃,i₄,i₅,...,i_n-m-1, institute Meaning coding finds out check bit using check matrix H:

Step S2: initiation verification bit p₀=0, p₁=0, p₂=0, p₃=0, p₄=0 ..., p_m=0；

Step S3: by each check bit p_iAnd coupled information bit does 2 He of mould, it may be assumed that p_i=p_i With p_i2 He of mould of connected information bit, wherein i=0,1,2 ... m-1.Later, the check bit p by above-mentioned mould 2 and later_iDo weight New arrangement:Thus the check bit sequence after being reset

Step S4: by the check bit sequence after rearrangementIt does following cumulative:

p′₀=p '₀

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Finally obtain check bit sequence:

Technical solution disclosed in specification through the invention as it can be seen that the characteristics of S-IRA LDPC code word of the invention be Circulation submatrix in its information bit matrix is only possible to be made of unit circle excursion matrix other than the structure of 0 matrix, It is the technical characteristic based on circulation sub-block that the selection of this circulation submatrix, which has adapted to HSS algorithm parallel computation, therefore when circulation Sub-block is required to read same memory simultaneously there is no the row operation input of two rows, also not deposited when parallel-by-bit operates After having operated while same content is write, can be avoided internal storage conflict in this way.

S-IRA LDPC code that information bit matrix and check bit matrix according to the present invention are constituted, using the present invention Encoder, the decoder of LDPC code can have preferable codeword performance in HSS algorithm.

In addition, invention additionally discloses a kind of coding method corresponding with above-mentioned S-IRA LDPC code word and encoders, and And above structure can be corresponded to.Encoder is built-in with encoding operation module, and encoding operation module uses following LDPC Coding method:

In encoding operation module,

Computation of parity bitsWherein, j=0,1,2,3 ..., m-1；It indicates in low-density surprise In even parity check matrix with p_jAssociated information bit；y_jIt is information bitSerial number, obtain according to the following formula:

Wherein, q=320, m=14400, x indicate to participate in the address of the cumulative information bit of Parity Check Bits, the table of x Are as follows:

Code table: code rate 3/4m=14400, code length n=57600

Specifically, the code word of LDPC is enabled are as follows:

C=(i₀,i₁,...,i_j,...,i_K-1,p₀,p₁,...,p_m-1)；Wherein, (i₀,i₁,...,i_n-m-1) it is information bit Bit is known { 1,0 } sequence.(p₀,p₁,p₂,...,p_m-1) it is check bit, it is bit to be calculated.

Each check bit corresponding to the check part is initialized first,

That is p₀=0, p₁=0, p₂=0, p₃=0, p₄=0, p₅=0 ..., p_m-1=0, wherein each p_iRepresent check matrix In a line, such as p_mRepresent the m row in check matrix.

It is one group according to q bit for check bit to be grouped to obtain multiple check bit groups.

Specifically, firstly, it is { p that the check bit, which is arranged,₀,p₁,p₂,p₃,p₄,p₅,...,p_m-1}.Then, by the school It tests bit and is grouped in order with q bit for one group to obtain multiple check bit groups.

For example, j-th of check bit group are as follows:

{p_jq+0,p_jq+1,...,p_jq+(q-1), wherein j value be (0,1,2 ..., Q-1), wherein

Secondly, by check bit and its associated information in low-density parity check (LDPC) matrix in each check bit group Bit carries out accumulation process.

Specifically, to q bit p in each check bit group_mMake following XOR operation:

Wherein, j=0,1,2,3 ..., m-1；It indicates in low-density parity check (LDPC) matrix With p_jAssociated information bit；y_jIt is information bitSerial number, obtain according to the following formula:

Wherein, q=320, m=24000, x indicate to participate in the address of the information bit to add up with Parity Check Bits

X indicates in each check bit group that first check bit (such as can be p₀, p_q+0, p_2q+0..., p_jq+0...) and representated by the low-density parity check (LDPC) matrix in row (corresponding 0th, q, 2q, 3q ..., jq ... row) it is inner The position of " 1 " column, but do not include the position of the column of " 1 " in the low-density parity check (LDPC) matrix in check part.

By taking the code word of table 1 as an example, q=320, check bit number m=19200, information bit n-m=38400.

The first row number in table 1:

Each number represents the first row (corresponding first check bit p in low-density parity check (LDPC) matrix₀) in " 1 " Position (position arranged), but this position do not include low-density parity check (LDPC) matrix check part it is (i.e. double to diagonal Part) " 1 " column position.

In addition the number of the row is x, represents first bit p in first check bit group₀Representative verification The position (position arranged, column are equally started counting with 0) of " 1 " of the 0th row in matrix.

So have:

After finishing this, then had according to formula (1):

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(1) for other rows according to above-mentioned formula and so on, it is numerous to list herein.

Interleaving treatment is made to each check bit after adding up later.

Specifically, comprising: interleaving treatment is made according to permutation format to each check bit after cumulative, wherein the displacement lattice Formula is realized by following formula:

p_iQ'=p_i；p_iQ+1'=p_i+q；p_iQ+2'=p_i+2q；p_iQ+3'=p_i+3q；

p_iQ+4'=p_i+4q,...,p_iQ+Q-1'=p_i+(Q-1)q；

Wherein, i=0,1,2,3 ..., q-1.

For example,

p₀'=p₀；p₁'=p_0+q；p₂'=p_0+2q；p₃'=p_0+3q；

p₄'=p_0+4q,...,p_Q-1'=p_0+(Q-1)q；

p_Q'=p₁；p_Q+1'=p_1+q；p_Q+2'=p_1+2q；p_Q+3'=p_1+3q；

p_Q+4'=p_1+4q,...,p_2Q-1'=p_1+(Q-1)q；

p_(q-1)Q'=p_q-1；p_(q-1)Q+1'=p_(q-1)+q；p_(q-1)Q+2'=p_(q-1)+2q；

p_(q-1)Q+3'=p_(q-1)+3q；

p_(q-1)Q+4'=p_(q-1)+4q,...,p_(q-1)Q+Q-1'=p_(q-1)+(Q-1)q；

Wherein,

In the present embodiment, { p₀,p₁,p₂,p₃,p₄,p₅,...,p_m-1Indicate the check bit before interweaving；

{p₀',p₁',p₂',p₃',p₄',p₅',...,p_m-1' indicate the check bit after interweaving.

Each check bit after interleaving treatment is finally subjected to mould 2 plus operation to obtain final check bit.

Specifically, this step is realized by following formula:

p′₀=p '₀

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Obtained (p₀',p₁',...p_m-1') it is check bit after final coding, finally obtained LDPC code c= (i₀,i₁,...,i_j,...,i_n-m-1,p₀',p₁',...,p_m-1')。

Internal storage conflict when for solving the problems, such as LDPC code for HSS algorithm by sacrifice complexity in the prior art, S-IRA LDPC code of the invention is set using the selection of the information bit matrix in the encoder of S-IRA LDPC code, decoder Meter can generate unexpected technical effect, from codeword structure sheet, significantly reduce the complexity of HSS algorithm, solve It has determined above-mentioned technical problem existing in the prior art.

It will be understood to one skilled in the art that above specification is only one of numerous embodiments of the present invention Or several embodiments, and not use limitation of the invention.Any equivalent change for embodiment described above, modification with And the technical solutions such as equivalent substitute will all fall in claims of the present invention as long as meeting spirit of the invention In the range of protecting.

Claims (2)

1. a kind of coding method of LDPC code, which comprises the following steps:

Computation of parity bitsWherein, j=0,1,2,3 ..., m-1；It indicates in low-density checksum In matrix with p_jAssociated information bit；y_jIt is information bitSerial number, obtain according to the following formula:

Wherein, number of bits q=320 in check bit group, check bit number m=14400, x indicate participation Parity Check Bits The address of cumulative information bit, the table of x are as follows:

Code table: code rate 3/4m=14400, code length n=57600

。

2. a kind of LDPC encoder, which is characterized in that the encoder includes:

Encoding operation module, to computation of parity bitsWherein, j=0,1,2,3 ..., m-1；

Indicate in low-density parity check (LDPC) matrix with p_jAssociated information bit；y_jIt is information bitSerial number, root It is obtained according to following formula:

Wherein, number of bits q=320 in check bit group, check bit number m=14400, x indicate participation Parity Check Bits The address of cumulative information bit, the table of x are as follows:

Code table: code rate 3/4m=14400, code length n=57600

。