CN105321885B - Memory device and its manufacture method - Google Patents
Memory device and its manufacture method Download PDFInfo
- Publication number
- CN105321885B CN105321885B CN201410313511.9A CN201410313511A CN105321885B CN 105321885 B CN105321885 B CN 105321885B CN 201410313511 A CN201410313511 A CN 201410313511A CN 105321885 B CN105321885 B CN 105321885B
- Authority
- CN
- China
- Prior art keywords
- layer
- drain
- remaining portions
- source
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention is on a kind of memory device and its manufacture method, which includes substrate, column-like paths layer and electric charge capture layer, which is arranged on the substrate, and includes peripheral sidewalls, the electric charge capture layer, around the peripheral sidewalls.The manufacture method includes providing workpiece, wherein the workpiece include the strip drain/source material sections with side wall, the channel material area that is arranged on the strip drain/source material sections and cover the strip drain/source material sections the side wall isolation dielectric material area；And by the specific part and the specific part in the isolation dielectric material area for removing the channel material area, the side wall of the exposure strip drain/source material sections and the remaining portions formation column-like paths floor for making the channel material area.Using the memory device in the present invention and its manufacture method to improve short-channel effect so that the channel length of memory device increases its passage length from the influence of gate cd.
Description
Technical field
The invention relates to a kind of semiconductor device, and especially with regard to a kind of memory device and its manufacture method.
Background technology
Referring to Fig. 1, it is a kind of schematic diagram of Nonvolatile memory device 10 in prior art.Nonvolatile memory
Device 10 includes memory cell 101.Memory cell 101 include semiconductor substrate 11, lightly-doped layer 12, source electrode 13, drain electrode 14, every
From dielectric layer 15, oxide skin(coating) 16, electric charge capture layer 17, oxide skin(coating) 18, grid 19 and dielectric layer 1A.Lightly-doped layer 12 is set
It is placed on semiconductor substrate 11.Source electrode 13 and drain electrode 14 may be contained within lightly-doped layer 12.Isolation dielectric layer 15 is arranged at source electrode
13 and drain electrode 14 on, and be coupled in oxide skin(coating) 16, electric charge capture layer 17, oxide skin(coating) 18 and grid 19.
Oxide skin(coating) 16 is arranged on lightly-doped layer 12, and between source electrode 13 and drain electrode 14.Electric charge capture layer 17 is set
It is placed on oxide skin(coating) 16.Oxide skin(coating) 18 is arranged on electric charge capture layer 17.Grid 19 is arranged on oxide skin(coating) 18.Dielectric
Layer 1A is arranged on grid 19 and isolation dielectric layer 15.In general, semiconductor substrate 11, oxide skin(coating) 16, electric charge capture layer 17, oxygen
Compound layer 18 and grid 19 are respectively P-type silicon substrate, silicon oxide layer, silicon nitride layer, silicon oxide layer and polysilicon gate, with shape
Into SONOS (Silicion-Oxide-Nitride-Oxide-Silicion) structure.
Electric charge capture layer 17 is to represent numerical data 1 or 0 for catching and storing electric charge.By oxide-nitride
Thing-oxide (Oxide-Nitride-Oxide, ONO) structure, the memory cell 101 of Nonvolatile memory device 10 can store up
Deposit two data.
However, the Nonvolatile memory device 10 with the SONOS structures runs into some challenges in development.Compared to thin
Gate CMOS transistor, plane SONOS Nonvolatile memories cell element has thicker ONO structure, therefore compares and be difficult to contract
Small size.Development restriction for the SONOS Nonvolatile memory cell elements is mainly caused by short-channel effect.Therefore, need
Want a kind of new memory device and its manufacture method.
The content of the invention
It is an object of the invention to provide a kind of memory device and its manufacture method, to improve short-channel effect so that interior
The channel length of cryopreservation device increases its passage length from the influence of gate cd.
The purpose of the present invention is realized using following technical scheme.According to a kind of memory device proposed by the present invention,
Comprising：Substrate；Column-like paths layer, is arranged on the substrate, and includes peripheral sidewalls；And electric charge capture layer, around the column
The peripheral sidewalls of channel layer.
The purpose of the present invention can be also applied to the following technical measures to achieve further.
Preferably, foregoing memory device, wherein described substrate includes：Body part, comprising table top and adjacent to
The groove of the table top；Lightly doped district, is arranged on the table top, and includes top surface and basal surface；And isolation dielectric layer, set
It is higher than the basal surface of the lightly doped district on the groove, and comprising top surface, wherein top surface of the isolation dielectric layer, and
Less than the top surface of the lightly doped district；The memory device further includes：Strip drain/source, is arranged at the lightly doped district and the column
Between shape channel layer；Cap layers drain/source, is arranged on the column-like paths layer, and comprising peripheral sidewalls and adjacent to the perimeter sides
The top surface of wall, the wherein electric charge capture layer more surround the peripheral sidewalls of the cap layers drain/source, and the table top, this is lightly doped
Area, the strip drain/source, the column-like paths floor and cap layers drain/source arrangement are in alignment；First oxide skin(coating), is set
In the electric charge capture layer and the strip drain/source, the electric charge capture layer and the column-like paths layer and the electric charge capture layer and it is somebody's turn to do
Between cap layers drain/source；Second oxide skin(coating), is arranged on the electric charge capture layer；And grid, it is arranged at second oxide
On layer, and the peripheral sidewalls and the peripheral sidewalls of the cap layers drain/source around the column-like paths layer.
Preferably, foregoing memory device, wherein described strip drain/source include top surface, the first side wall and
The top surface of the second sidewall on the first side wall opposite of the strip drain/source, wherein the strip drain/source includes and the column
First sublist face of shape channel layer contact and extend from the second sublist face in the first sublist face and the 3rd sublist face, and this
Two with not homonymy that the 3rd sublist face is positioned at the column-like paths layer；And the electric charge capture layer covers the cap layers drain/source
The top surface, the first side wall of the strip drain/source, the second sidewall and this second with the 3rd sublist face and should
Isolate the top surface of dielectric layer.
The purpose of the present invention is also realized using following technical scheme.According to a kind of manufacture memory device proposed by the present invention
Method, it includes the following steps：Workpiece is provided, the wherein workpiece includes the strip drain/source material sections with side wall, sets
It is situated between in the isolation of the channel material area on the strip drain/source material sections and the side wall for covering the strip drain/source material sections
Electric material area；And by the specific part and the specific part in the isolation dielectric material area for removing the channel material area, exposure
The side wall of the strip drain/source material sections and the remaining portions formation column-like paths floor for making the channel material area.
The purpose of the present invention can be also applied to the following technical measures to achieve further.
Preferably, foregoing method, wherein the step of offer workpiece includes substep：Substrate is provided；
The first dielectric layer is formed on the substrate；Lightly-doped layer is formed in the substrate under first dielectric layer, to be lightly doped at this
The first remaining portions of the substrate are formed under layer；The first drain/source material is formed in the lightly-doped layer under first dielectric layer
The bed of material, to form the first remaining portions of the lightly-doped layer under the first drain/source material layer, wherein the lightly-doped layer should
Remaining portions include top surface and basal surface；Remove first dielectric layer；Non-crystalline silicon is formed in the first drain/source material layer
Layer；Rigid shielded layer is formed on the amorphous silicon layer；The spy of the rigid shielded layer is removed by the rigid shielded layer is patterned
Fixed part, the specific part of the amorphous silicon layer, the specific part of the first drain/source material layer, the lightly-doped layer this first
The subdivision of the first remaining portions of this of the subdivision of remaining portions and the substrate, to form first groove structure, the rigid screen
Cover the remaining portions of layer, first remaining portions of the amorphous silicon layer, the first drain/source material layer remaining portions, this is light
First remaining portions of second remaining portions of doped layer and the second remaining portions of the substrate, the wherein amorphous silicon layer
Comprising top surface and with the top surface top, and the remaining portions of the first drain/source material layer include top surface and
Side wall；The groove structure is filled up with isolation dielectric structure；By the specific part and the rigid screen for removing the isolation dielectric structure
Cover the remaining portions of layer and expose the top surface of first remaining portions of the amorphous silicon layer and form the isolation dielectric knot
First remaining portions of first remaining portions of structure, wherein the isolation dielectric structure include top surface and side wall, and the amorphous
The top surface of first remaining portions of silicon layer is flushed with the top surface of first remaining portions for isolating dielectric structure；
And the second drain/source material layer is formed in the top of first remaining portions of the amorphous silicon layer, with this second leakage/
The second remaining portions of the amorphous silicon layer are formed under source electrode material layer, to form the workpiece, wherein：The second drain/source material
Layer includes top surface；The remaining portions of the first drain/source material layer and second remaining portions difference of the amorphous silicon layer
It is the strip drain/source material sections and the channel material area；And side of the remaining portions of the first drain/source material layer
Wall is the side wall of the strip drain/source material sections, and is coupled in the side of first remaining portions of the isolation dielectric structure
Wall.
Preferably, foregoing method, wherein the step of formation column-like paths layer includes substep：At this
Light is formed on the top surface of the top surface of second drain/source material layer and first remaining portions of the isolation dielectric structure
Photoresist patterned layer, to expose the relevant portion of the top surface of the second drain/source material layer；By the photoresist pattern layer,
The subdivision of the specific part of the second drain/source material layer and second remaining portions of the amorphous silicon layer is removed, to be formed
The relevant portion of the top surface of the remaining portions of second groove structure and exposure the first drain/source material layer；Removing should
Photoresist pattern layer；And the subdivision by first remaining portions for removing the isolation dielectric structure, form the 3rd groove
Structure, the remaining portions of the second drain/source material layer, the second of the column-like paths layer and the isolation dielectric structure are retained
Part, and the side wall of the remaining portions of the first drain/source material layer is exposed, the wherein column-like paths layer includes perimeter sides
Wall, the remaining portions of the second drain/source material layer include top surface and peripheral sidewalls, the isolation dielectric structure this second
Remaining portions include top surface, and the top surface of second remaining portions of the isolation dielectric structure is higher than the lightly-doped layer
The basal surface of the remaining portions and the top surface for being less than the remaining portions of the lightly-doped layer；This method further includes following
Step：The top surface and the peripheral sidewalls, the column-like paths layer in the remaining portions of the second drain/source material layer should
Peripheral sidewalls, the relevant portion of the top surface of the remaining portions of the first drain/source material layer, first drain/source
On the top surface of the side wall of the remaining portions of material layer and second remaining portions of the isolation dielectric structure, formed
First oxide skin(coating)；Charge trapping material layers are formed on first oxide skin(coating)；Is formed on the Charge trapping material layers
Dioxide layer；And form grid on second oxide skin(coating).
The purpose of the present invention is also realized using following technical scheme.According to a kind of memory device proposed by the present invention, its
Comprising：Substrate；Strip drain/source, is arranged on the substrate；And column-like paths layer, it is arranged in the strip drain/source.
The purpose of the present invention can be also applied to the following technical measures to achieve further.
Preferably, foregoing memory device, wherein described substrate includes：Body part, comprising table top and adjacent to
The groove of the table top；Lightly doped district, is arranged on the table top, and includes top surface and basal surface；And isolation dielectric layer, set
It is higher than the basal surface of the lightly doped district on the groove, and comprising top surface, wherein top surface of the isolation dielectric layer, and
Less than the top surface of the lightly doped district；And the strip drain/source is arranged between the lightly doped district and the column-like paths layer.
Preferably, foregoing memory device, it is further included：Cap layers drain/source, is arranged on the column-like paths layer, and wraps
Top surface containing peripheral sidewalls and adjacent to the peripheral sidewalls, the wherein table top, the lightly doped district, the strip drain/source, the column
Shape channel layer and cap layers drain/source arrangement are in alignment；Electric charge capture layer, around the periphery of the column-like paths layer
The peripheral sidewalls of side wall and the cap layers drain/source；First oxide skin(coating), is arranged at the electric charge capture layer and the strip leakage/source
Between pole, the electric charge capture layer and the column-like paths layer and the electric charge capture layer and the cap layers drain/source；Second oxide
Layer, is arranged on the electric charge capture layer；And grid, it is arranged on second oxide skin(coating), and around the column-like paths layer
The peripheral sidewalls of the peripheral sidewalls and the cap layers drain/source.
Preferably, foregoing memory device, wherein described strip drain/source include top surface, the first side wall and
The top surface of the second sidewall on the first side wall opposite of the strip drain/source, wherein the strip drain/source includes and the column
First sublist face of shape channel layer contact and extend from the second sublist face in the first sublist face and the 3rd sublist face, and this
Two with not homonymy that the 3rd sublist face is positioned at the column-like paths layer；And the electric charge capture layer covers the cap layers drain/source
The top surface, the first side wall of the strip drain/source, the second sidewall and this second with the 3rd sublist face and should
Isolate the top surface of dielectric layer.
By above-mentioned technical proposal, memory device of the present invention and its manufacture method at least have following advantages and beneficial to effect
Fruit：Due to the influence that short-channel effect, process variation and reliability reduce, further reduce of planar devices faces extreme
Challenge.The memory device and its manufacture method of the present invention provides mechanism to improve short-channel effect so that the channel of memory device
Length from gate cd influence, to increase its passage length.
Described above is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow the above and other objects, features and advantages of the present invention can
Become apparent, below especially exemplified by preferred embodiment, and coordinate attached drawing, describe in detail as follows.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of Nonvolatile memory device in prior art.
Fig. 2A, Fig. 2 B and Fig. 2 C are respectively a kind of three-dimensional signal of memory device in present invention embodiment of all kinds
Figure, side elevational cross-section schematic diagram and main view diagrammatic cross-section.
Fig. 3 is a kind of schematic diagram of the workpiece of memory device manufacture method in present invention embodiment of all kinds.
Fig. 4 is the schematic diagram of the workpiece of the memory device manufacture method in present invention embodiment of all kinds.
Fig. 5 is the schematic diagram of the workpiece of the memory device manufacture method in present invention embodiment of all kinds.
Fig. 6 is the schematic diagram of the workpiece of the memory device manufacture method in present invention embodiment of all kinds.
Fig. 7 A and Fig. 7 B are respectively the master of the workpiece of the memory device manufacture method in present invention embodiment of all kinds
Depending on diagrammatic cross-section and schematic perspective view.
Fig. 8 A and Fig. 8 B are respectively the master of the workpiece of the memory device manufacture method in present invention embodiment of all kinds
Depending on diagrammatic cross-section and schematic perspective view.
Fig. 9 A, Fig. 9 B and Fig. 9 C are respectively the workpiece of the memory device manufacture method in present invention embodiment of all kinds
Schematic perspective view, main view diagrammatic cross-section and side elevational cross-section schematic diagram.
Figure 10 is the schematic perspective view of the workpiece of the memory device manufacture method in present invention embodiment of all kinds.
Figure 11 is the schematic perspective view of the workpiece of the memory device manufacture method in present invention embodiment of all kinds.
Figure 12 A and Figure 12 B are respectively the workpiece of the memory device manufacture method in present invention embodiment of all kinds
Main view diagrammatic cross-section and schematic perspective view.
Figure 13 A and Figure 13 B are respectively the workpiece of the memory device manufacture method in present invention embodiment of all kinds
Main view diagrammatic cross-section and schematic perspective view.
Figure 14 A and Figure 14 B are respectively the workpiece of the memory device manufacture method in present invention embodiment of all kinds
Main view diagrammatic cross-section and schematic perspective view.
Figure 15 is the diagrammatic cross-section of the workpiece of the memory device manufacture method in present invention embodiment of all kinds.
Figure 16 A, Figure 16 B and Figure 16 C are respectively the memory device manufacture method in present invention embodiment of all kinds
Schematic perspective view, side elevational cross-section schematic diagram and the main view diagrammatic cross-section of memory device.
【Main element symbol description】
10：Nonvolatile memory device 101,311,312,313,314：Memory cell
11：Semiconductor substrate 12,43：Lightly-doped layer
13：Source electrode 14：Drain electrode
15、213：Isolate dielectric layer
16、18、25、27、531、533、611、613：Oxide skin(coating)
17、26、532：Electric charge capture layer 19,28,558：Grid
1A、42：Dielectric layer 20,914：Memory device
21、41：Substrate 23,458：Column-like paths layer
211：Body part 212：Lightly doped district
2111：Table top 2112：Groove
212A、213A、22A、24A、23B、432A、442A、452A、462A、482A、483A、492A、53A、552A：Top
Surface
212B、432B：Basal surface 22：Strip drain/source
23A、24B、454A、492B、53B：Peripheral sidewalls
24、498：Cap layers drain/source 22B, 22C, 442B, 482B：Side wall
22A1、22A2、22A3：Sublist face 321,322：Row
331、332：Row 29,61：Charge storing structure
291、538：Bottom passageway 34：Wordline
35、37、30、58、59、60：Contact
36、39：Bit line
411、412、431、432、442、452、453、454、462、482、483、492、552、553、5311、5321、
5331、539：Remaining portions
4111、4311、4531、4811、4812、4821、5521：Subdivision
44、49：Drain/source material layer
441、451、461、481、491、551、535、536：Specific part
442A1、482A1、49A1、552A1、442A2：Relevant portion
447：Strip drain/source material sections 45：Amorphous silicon layer
4521：Top 46：Rigid shielded layer
47、51、52、54、57：Groove structure 48：Isolate dielectric structure
50、56：Photoresist pattern layer 53：Charge storage material structure
532：Charge trapping material layers 55：Conductive layer
901、902、903、904、905、906、907、908、909、910、911、912、913：Workpiece H1：Highly
L1：Length W1：Width
Embodiment
Further to illustrate the present invention to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Attached drawing and preferred embodiment, to the embodiment according to a kind of memory device proposed by the present invention and its manufacture method, knot
Structure, feature and its effect, describe in detail as after.
Fig. 2A, Fig. 2 B and Fig. 2 C are referred to, it is respectively the vertical of the memory device 20 in present invention embodiment of all kinds
Body schematic diagram, side elevational cross-section schematic diagram and main view diagrammatic cross-section.Fig. 2 B show that the side view at reference line A A ' places in fig. 2 is cutd open
Face schematic diagram.Fig. 2 C show the main view diagrammatic cross-section at reference line B B ' places in fig. 2.Memory device 20 include substrate 21,
Column-like paths layer 23 and electric charge capture layer 26.Column-like paths layer 23 is arranged on substrate 21, and includes peripheral sidewalls 23A.Electric charge
Trapping layer 26 surrounds peripheral sidewalls 23A.
In certain embodiments, substrate 21 includes body part 211, lightly doped district 212 and isolation dielectric layer 213.Gently mix
Miscellaneous area 212 and isolation dielectric layer 213 are adjacent, and may be contained within substrate 21.Body part 211 include table top 2111 and adjacent to
The groove 2112 of table top 2111.Lightly doped district 212 is arranged on table top 2111, and comprising top surface 212A and in top surface 212A
The basal surface 212B on opposite.Isolation dielectric layer 213 is arranged on groove 2112, and comprising top surface 213A, wherein isolating dielectric
The top surface 213A of layer 213 is higher than the basal surface 212B of lightly doped district 212, and less than the top surface 212A of lightly doped district 212.
In certain embodiments, memory device 20 further includes strip drain/source 22, cap layers drain/source 24, oxide skin(coating)
25th, oxide skin(coating) 27 and grid 28.Strip drain/source 22 is arranged between lightly doped district 212 and column-like paths layer 23.For example,
Strip drain/source 22 is laterally arranged in lightly doped district 212, and column-like paths layer 23 is arranged on strip drain/source 22.
Cap layers drain/source 24 is arranged on column-like paths layer 23, and includes top surface 24A and the peripheral sidewalls adjacent to top surface 24A
24B.For example, cap layers drain/source 24 is arranged on the top surface 23B of column-like paths layer 23.For example, strip drain/source 22 is source
One of pole and drain electrode.When strip drain/source 22 is source electrode, cap layers drain/source 24 is and the matched drain electrode of the source electrode.
For example, when strip drain/source 22 is drain electrode, cap layers drain/source 24 is and the matched source electrode of the drain electrode.
Electric charge capture layer 26 more surrounds or the peripheral sidewalls 24B completely about cap layers drain/source 24, and table top 2111,
Lightly doped district 212, strip drain/source 22, column-like paths layer 23 and cap layers drain/source 24 arrange in alignment.Oxide skin(coating)
25 are arranged at electric charge capture layer 26 and strip drain/source 22, electric charge capture layer 26 and column-like paths layer 23 and electric charge capture layer
Between 26 and cap layers drain/source 24.Oxide skin(coating) 27 is arranged on electric charge capture layer 26.Grid 28 is arranged at oxide skin(coating) 27
On, and surround or completely about the peripheral sidewalls 23A of the column-like paths layer 23 and peripheral sidewalls 24B of cap layers drain/source 24.Example
Such as, column-like paths layer 23 has length L1, width W1 and height H1, and height H1 is more than length L1, and height H1 is more than width W1.
The height H1 of column-like paths layer 23 is used for the channel length for representing memory device 20.
Strip drain/source 22 includes top surface 22A, side wall 22B and the side wall 22C on side wall 22B opposites.Strip leakage/source
The top surface 22A of pole 22 includes the sublist face 22A1 contacted with column-like paths layer 23 and the sublist face for extending from sublist face 22A1
22A2 and sublist face 22A3, and sublist face 22A2 and 22A3 is the not homonymy positioned at column-like paths layer 23.Electric charge capture layer 26 covers
The top surface 24A of cap drain/source 24, the side wall 22B of strip drain/source 22, side wall 22C and sublist face 22A2 and 22A3,
And the top surface 213A of isolation dielectric layer 213.
In the embodiment of all kinds provided according to Fig. 2A, Fig. 2 B and Fig. 2 C, a kind of memory device 20 includes substrate
21st, strip drain/source 22 and column-like paths layer 23.Strip drain/source 22 is arranged on substrate 21.Column-like paths layer 23 is arranged at
In strip drain/source 22.For example, strip drain/source 22 is arranged between lightly doped district 212 and column-like paths layer 23.
In the embodiment of all kinds provided according to Fig. 2A, Fig. 2 B and Fig. 2 C, a kind of memory device 20 includes multiple
Memory cell 311,312,313 and 314.The plurality of memory cell 311,312,313 and 314 be arranged in multiple row (Row) (such as
322) and multirow (Column) (such as 331 and 332) 321 and.Each of the plurality of memory cell 311,312,313 and 314
Cell element includes substrate 21, strip drain/source 22, column-like paths layer 23, cap layers drain/source 24, charge storing structure 29, grid 28
With contact 30.Charge storing structure 29 has bottom passageway 291.Contact 30 is arranged at cap layers by bottom passageway 291
On the top surface 24A of drain/source 24.Charge storing structure 29 includes oxide skin(coating) 25, electric charge capture layer 26 and oxide skin(coating) 27.
Each row of the plurality of row 321 and 322 include a wordline 34 and the contact 35 being arranged in wordline 34, wordline
34 directly form multiple grids 28 of each row.Every a line of the plurality of row 331 and 332 includes bit line 39, bit line 36 and sets
The contact 37 being placed on bit line 36, bit line 36 directly form multiple strip drain/source 22 per a line.It is for example, the plurality of
Each cell element of memory cell 311,312,313 and 314 is used to store two data.For example, to be electrically connected to this each for bit line 39
Capable multiple contacts 30.
Referring to Fig. 3, it is the signal of the workpiece 901 of memory device manufacture method in present invention embodiment of all kinds
Figure.The memory device manufacture method is used to manufacture multiple memory cells or multiple Nonvolatile memory cell elements.For the sake of clarity,
At least one the memory device manufacture method is described with manufacture in the plurality of memory cell.The method for forming workpiece 901 is chatted
State as follows.Substrate 41 is provided.For example, substrate 41 is a semiconductor substrate, such as P-type semiconductor substrate.The shape on substrate 41
Into dielectric layer 42.For example, the dielectric layer 42 on substrate 41, and dielectric layer 42 is oxide skin(coating).Base under dielectric layer 42
Lightly-doped layer 43 is formed in plate 41, with the remaining portions 411 of 43 times forming substrates of lightly-doped layer 41.For example, pass through dielectric layer
42, carrier or the first dopant are injected in substrate 41, to form lightly-doped layer 43.
Drain/source material layer 44 is formed in lightly-doped layer 43 under dielectric layer 42, with formed workpiece 901 and leakage/
The remaining portions 431 of lightly-doped layer 43 are formed under source electrode material layer 44.For example, by dielectric layer 42, the second dopant is injected
In lightly-doped layer 43, to form drain/source material layer 44.Drain/source material layer 44 and lightly-doped layer 43 have first to mix respectively
Dopant concentrations and the second concentration of dopant, and first concentration of dopant is more than second concentration of dopant.
Referring to Fig. 4, it is that the workpiece 902 of the memory device manufacture method shows in present invention embodiment of all kinds
It is intended to.Fig. 3 is please extraly referred to, the method for forming workpiece 902 is described below.Remove the dielectric layer 42 of workpiece 901.In leakage/source
Amorphous silicon layer 45 is formed in pole material layer 44.For example, the deposition of amorphous silicon layers 45 in drain/source material layer 44.In amorphous silicon layer
Rigid shielded layer 46 is formed on 45, to form workpiece 902.For example, rigid shielded layer 46 is deposited on amorphous silicon layer 45, and it is rigid
Shielded layer 46 is silicon nitride layer.
Referring to Fig. 5, it is that the workpiece 903 of the memory device manufacture method shows in present invention embodiment of all kinds
It is intended to.The method for forming workpiece 903 is described below.The specific of rigid shielded layer 46 is removed by rigid shielded layer 46 is patterned
Part 461, the specific part 451 of amorphous silicon layer 45, drain/source material layer 44 specific part 441, lightly-doped layer 43 retention
The subdivision 4111 of the subdivision 4311 of part 431 and the remaining portions 411 of substrate 41, to form groove structure 47, rigid screen
Cover the remaining portions 462 of layer 46, the remaining portions 452 of amorphous silicon layer 45, drain/source material layer 44 remaining portions 442, gently mix
The remaining portions 432 of diamicton 43, the remaining portions 412 of substrate 41 and workpiece 903.
The remaining portions 462 of rigid shielded layer 46 include top surface 462A.The remaining portions 452 of amorphous silicon layer 45 include top
Surface 452A and the top 4521 with top surface 452A.The remaining portions 442 of drain/source material layer 44 include top surface 442A
With the side wall 442B adjacent to top surface 442A.The remaining portions 432 of lightly-doped layer 43 include top surface 432A and in top surfaces
The basal surface 432B on 432A opposites.For example, in rigid shielded layer 46, amorphous silicon layer 45, drain/source material layer 44, lightly-doped layer
Groove structure 47 is etched in 43 remaining portions 431 and the remaining portions 411 of substrate 41.For example, drain/source material layer 44
Remaining portions 442 form strip drain/source material sections 447.
Referring to Fig. 6, it is that the workpiece 904 of the memory device manufacture method shows in present invention embodiment of all kinds
It is intended to.The method for forming workpiece 904 is described below.Groove structure 47 is filled up with isolation dielectric structure 48, to form workpiece 904.
For example, deposition isolation dielectric structure 48 in groove structure 47 and on the remaining portions 462 of rigid shielded layer 46, and isolate dielectric
Structure 48 is oxide structure.For example, isolation dielectric structure 48 includes the top surface with the remaining portions 452 of amorphous silicon layer 45
The relevant specific parts 481 of 452A.The specific part 481 for isolating dielectric structure 48 includes the remaining portions with rigid shielded layer 46
The 462 relevant subdivisions 4811 of top surface 462A and in subdivision 4811 times and with the remaining portions 452 of amorphous silicon layer 45
The relevant subdivisions 4812 of top surface 452A.
Fig. 7 A and Fig. 7 B are referred to, it is respectively the memory device manufacture method in present invention embodiment of all kinds
The main view diagrammatic cross-section and schematic perspective view of workpiece 905.Fig. 6 is please extraly referred to, forms the method narration of workpiece 905 such as
Under.By the specific part 481 and the remaining portions 462 of rigid shielded layer 46 for removing isolation dielectric structure 48, exposure non-crystalline silicon
The top surface 452A of the remaining portions 452 of layer 45 and the remaining portions 482 for forming isolation dielectric structure 48, to form workpiece 905.
The remaining portions 482 of isolation dielectric structure 48 include the top surface 482A and side wall 482B adjacent to top surface 482A, and amorphous
The top surface 482A of remaining portions 482 of the top surface 452A of the remaining portions 452 of silicon layer 45 with isolating dielectric structure 48 is flushed.
For example, the remaining portions 482 of isolation dielectric structure 48 are tabular dielectric layers.
Remove isolation dielectric structure 48 specific part 481 and rigid shielded layer 46 remaining portions 462 the step of include
Substep.The specific part 481 of isolation dielectric structure 48 is removed by chemical mechanical grinding (CMP) technique or etch-back technics
Subdivision 4811, with planarization isolation dielectric structure 48 and the remaining portions 462 of the rigid shielded layer 46 of exposure.For example, by
The remaining portions 462 of rigid shielded layer 46, stop chemical mechanical grinding (CMP) technique or the etch-back technics, with planarization every
From dielectric structure 48.Remove the remaining portions 462 of rigid shielded layer 46.By wet type cleaning process, isolation dielectric structure is removed
The subdivision 4812 of 48 specific part 481, so that the top surface 452A of the remaining portions 452 of amorphous silicon layer 45 is with isolating dielectric
The top surface 482A of the remaining portions 482 of structure 48 is flushed.The side wall 442B couplings of the remaining portions 442 of drain/source material layer 44
Together in the side wall 482B of the remaining portions 482 of isolation dielectric structure 48.For example, 482 shape of remaining portions of isolation dielectric structure 48
Into isolation dielectric material area.
Fig. 8 A and Fig. 8 B are referred to, it is respectively the memory device manufacture method in present invention embodiment of all kinds
The main view diagrammatic cross-section and schematic perspective view of workpiece 906.Fig. 7 A and Fig. 7 B are please extraly referred to, the method for forming workpiece 906
It is described below.Drain/source material layer 49 is formed in the top 4521 of the remaining portions 452 of amorphous silicon layer 45, with drain/source
The remaining portions 453 of amorphous silicon layer 45 are formed under material layer 49, to form workpiece 906.For example, dopant is injected into amorphous silicon layer
In the top 4521 of 45 remaining portions 452, to form drain/source material layer 49.Drain/source material layer 49 includes top surface
49A.For example, the remaining portions 453 of amorphous silicon layer 45 form channel material area.
Fig. 9 A, Fig. 9 B and Fig. 9 C are referred to, it is respectively the memory device manufacture in present invention embodiment of all kinds
Schematic perspective view, main view diagrammatic cross-section and the side elevational cross-section schematic diagram of the workpiece 907 of method.Fig. 9 B show and refer in figure 9 a
The main view diagrammatic cross-section at line CC ' places.Fig. 9 C show the side elevational cross-section schematic diagram at reference line DD ' places in figure 9 a.Please volume
Other places refers to Fig. 8 A and Fig. 8 B, and the method for forming workpiece 907 is described below.Drain/source material layer 49 top surface 49A and every
Photoresist pattern layer 50 is formed on top surface 482A from the remaining portions 482 of dielectric structure 48, to expose drain/source material layer
The dependent part of the top surface 482A of the relevant portion 49A1 of 49 top surface 49A and the remaining portions 482 of isolation dielectric structure 48
Divide 482A1 and form workpiece 907.
Referring to Fig. 10, it is the workpiece 908 of the memory device manufacture method in present invention embodiment of all kinds
Schematic perspective view.Fig. 9 A, Fig. 9 B and Fig. 9 C are please extraly referred to, the method for forming workpiece 908 is described below.By photoresist figure
Pattern layer 50, removes the subdivision of the specific part 491 of drain/source material layer 49 and the remaining portions 453 of amorphous silicon layer 45
4531, to form the dependent part of the top surface 442A of the remaining portions 442 of groove structure 51 and exposure drain/source material layer 44
Divide 442A1.The specific part 491 of drain/source material layer 49 includes the relevant portion of the top surface 49A of drain/source material layer 49
49A1.For example, etch groove structure 51 in the remaining portions 453 of drain/source material layer 49 and amorphous silicon layer 45.Remove
Photoresist pattern layer 50, to form workpiece 908.
1 is please referred to Fig.1, it is the workpiece 909 of the memory device manufacture method in present invention embodiment of all kinds
Schematic perspective view.Figure 10 is please extraly referred to, the method for forming workpiece 909 is described below.Isolate dielectric structure 48 by removing
Remaining portions 482 subdivision 4821, formed groove structure 52, remaining portions 492, the non-crystalline silicon of drain/source material layer 49
The remaining portions 454 of layer 45 and the retention portion of the remaining portions 483 of isolation dielectric structure 48 and exposure drain/source material layer 44
Divide 442 side wall 442B, to form workpiece 909.For example, by etch-back technics, form groove structure 52, and groove structure 51 with
Groove structure 52 communicates.
The remaining portions 454 of amorphous silicon layer 45 form column-like paths layer 458.The remaining portions 454 of amorphous silicon layer 45 include
Peripheral sidewalls 454A, the remaining portions 492 of drain/source material layer 49 form cap layers drain/source 498, and include top surface 492A
With the peripheral sidewalls 492B adjacent to top surface 492A.The remaining portions 483 of isolation dielectric structure 48 include top surface 483A, and
Isolate basal surfaces of the top surface 483A higher than the remaining portions 432 of lightly-doped layer 43 of the remaining portions 483 of dielectric structure 48
432B and the top surface 432A for being less than the remaining portions 432 of lightly-doped layer 43.
2A and Figure 12 B are please referred to Fig.1, it is respectively the memory device manufacture method in present invention embodiment of all kinds
Workpiece 910 main view diagrammatic cross-section and schematic perspective view.The main view that Figure 12 A are shown in reference line EE ' places in Figure 12 B is cutd open
Face schematic diagram.Figure 11 is please extraly referred to, the method for forming workpiece 910 is described below.In the retention portion of drain/source material layer 49
Points 492 top surface 492A and peripheral sidewalls 492B, the peripheral sidewalls 454A of the remaining portions 454 of amorphous silicon layer 45, drain/source
The relevant portion 442A1 of the top surface 442A of the remaining portions 442 of material layer 44, the remaining portions 442 of drain/source material layer 44
Side wall 442B and isolate dielectric structure 48 remaining portions 483 top surface 483A on, formed charge storage material structure
53, to form workpiece 910 and groove structure 54.
Charge storage material structure 53 includes the top surface 53A and peripheral sidewalls 53B adjacent to top surface 53A, and groove
Structure 54 surrounds peripheral sidewalls 53B.For example, top surface 492A, groove knot in the remaining portions 492 of drain/source material layer 49
Deposited charge storage material structure 53 on structure 51 and groove structure 52.For example, charge storing structure 53 be oxide-nitride-
Oxide (oxide-nitride-oxide, ONO) layer.
In certain embodiments, charge storage material structure 53 includes oxide skin(coating) 531,532 and of Charge trapping material layers
Oxide skin(coating) 533, wherein oxide skin(coating) 531 are arranged at Charge trapping material layers 532 and the remaining portions of drain/source material layer 44
442nd, the remaining portions 454 of Charge trapping material layers 532 and amorphous silicon layer 45, Charge trapping material layers 532 and drain/source material
Between the remaining portions 492 of layer 49, and Charge trapping material layers 532 are arranged between oxide skin(coating) 531 and oxide skin(coating) 533.
For example, the material of Charge trapping material layers 532 be selected from nitride, high-dielectric coefficient oxide, nitrogen oxides, and combinations thereof it
One.
3A and Figure 13 B are please referred to Fig.1, it is respectively the memory device manufacture method in present invention embodiment of all kinds
Workpiece 911 main view diagrammatic cross-section and schematic perspective view.Figure 12 A and Figure 12 B are please extraly referred to, form workpiece 911
Method is described below.Groove structure 54 is filled up with conductive layer 55, to form workpiece 911.For example, in charge storage material structure 53
Upper deposition conductive layer 55.For example, conductive layer 55 is polysilicon layer, and include the top surface 53A with charge storage material structure 53
Relevant specific part 551.
4A and Figure 14 B are please referred to Fig.1, it is respectively the memory device manufacture method in present invention embodiment of all kinds
Workpiece 912 main view diagrammatic cross-section and schematic perspective view.The main view that Figure 14 A are shown in reference line FF ' places in Figure 14 B is cutd open
Face schematic diagram.Figure 13 A and Figure 13 B are please extraly referred to, the method for forming workpiece 912 is described below.By chemical mechanical grinding
(CMP) technique or etch-back technics, remove the specific part 551 of conductive layer 55, to planarize conductive layer 55, form conductive layer 55
The top surface 53A of remaining portions 552 and exposure charge storage material structure 53.The remaining portions 552 of conductive layer 55 include top table
Face 552A.
For example, by the top surface 53A of charge storage material structure 53, stop chemical mechanical grinding (CMP) technique or
The etch-back technics, to planarize conductive layer 55, so that the retention of the top surface 53A of charge storage material structure 53 and conductive layer 55
The top surface 552A of part 552 is flushed.
5 are please referred to Fig.1, it is the workpiece 913 of the memory device manufacture method in present invention embodiment of all kinds
Diagrammatic cross-section.Figure 14 A and Figure 14 B are please extraly referred to, the method for forming workpiece 913 is described below.In charge storage material
The top surface 53A of structure 53 on the top surface 552A of the remaining portions 552 of conductive layer 55 with forming photoresist pattern layer 56, with sudden and violent
Reveal the relevant portion 552A1 of the top surface 552A of the remaining portions 552 of conductive layer 55 and form workpiece 913.For example, conductive layer
55 remaining portions 552 include subdivision 5521 relevant with photoresist pattern layer 56.The son of the remaining portions 552 of conductive layer 55
Part 5521 includes the relevant portion 552A1 of the top surface 552A of the remaining portions 552 of conductive layer 55.Charge storage material structure
53 include specific part 536 and are relevant to the specific part 535 of photoresist pattern layer 56.
6A, Figure 16 B and Figure 16 C are please referred to Fig.1, it is respectively the memory device system in present invention embodiment of all kinds
Make the schematic perspective view, side elevational cross-section schematic diagram and main view diagrammatic cross-section of the memory device 914 of method.Figure 16 B are shown in figure
The side elevational cross-section schematic diagram at reference line GG ' places in 16A.Figure 16 C are shown in the main view section at reference line HH ' places in Figure 16 A
Schematic diagram.Figure 14 A, Figure 14 B and Figure 15 are please extraly referred to, the method for forming memory device 914 is described below.
By photoresist pattern layer 56, the subdivision 5521 and photoetching agent pattern of the remaining portions 552 of removal conductive layer 55
The specific part 535 of layer 56, to form the remaining portions 553 of groove structure 57 and conductive layer 55 and exposure drain/source material layer
The relevant portion 442A1 of the top surface 442A of 44 remaining portions 442.For example, in the remaining portions 552 and electric charge of conductive layer 55
Groove structure 57 is etched in storage material structure 53.
Remove photoresist pattern layer 56.Charge storage material structure is removed by patterning charge storage material structure 53
53 specific part 536, to form the bottom passageway 538 of charge storage material structure 53 and remaining portions 539.For example, electric charge
The remaining portions 539 of storage material structure 53 form charge storing structure 61, and include the remaining portions of oxide skin(coating) 531
5311st, the remaining portions 5331 of the remaining portions 5321 of Charge trapping material layers 532 and oxide skin(coating) 533.For example, oxide
The remaining portions of 531 remaining portions 5311 of layer, the remaining portions 5321 of Charge trapping material layers 532 and oxide skin(coating) 533
5331 be oxide skin(coating) 611, electric charge capture layer 612 and oxide skin(coating) 613 respectively.
By the bottom passageway 538 of charge storage material structure 53, in the remaining portions 492 of drain/source material layer 49
Contact 58 is formed on top surface 492A.In the relevant portion of the top surface 442A of the remaining portions 442 of drain/source material layer 44
Contact 59 is formed on 442A2.Contact 60 is formed on the remaining portions 553 of conductive layer 55, to form memory device 914.
For example, the remaining portions 553 of conductive layer 55 form grid 558, and the week of the remaining portions 492 around drain/source material layer 49
The peripheral sidewalls 454A of the remaining portions 454 of avris wall 492B and amorphous silicon layer 45.
In the embodiment of all kinds provided according to Fig. 3 to Figure 16 C, a kind of method bag for manufacturing memory device 914
Containing the following steps：Workpiece 906 is provided, wherein workpiece 906 includes the strip drain/source material sections 447 with side wall 442B, sets
In the side wall 442B of the channel material area on strip drain/source material sections 447 and covering strip drain/source material sections 447 every
From dielectric material area；And by the specific part (such as subdivision 4531) and isolation dielectric material area for removing channel material area
Specific part (such as subdivision 4821), the side wall 442B of exposure strip drain/source material sections 447 and make channel material area
Remaining portions 454 form column-like paths layer 458.
In certain embodiments, there is provided the step of workpiece 906 is described below.Substrate 41 is provided.Formed and be situated between on substrate 41
Electric layer 42.Lightly-doped layer 43 is formed in substrate 41 under dielectric layer 42, with the retention of 43 times forming substrates of lightly-doped layer 41
Part 411.Drain/source material layer 44 is formed in lightly-doped layer 43 under dielectric layer 42, with 44 times shapes of drain/source material layer
Into the remaining portions 431 of lightly-doped layer 43.
The step of providing workpiece 906 continues to be described below.Remove dielectric layer 42.Formed in drain/source material layer 44 non-
Crystal silicon layer 45.Rigid shielded layer 46 is formed on amorphous silicon layer 45.Rigid shielding is removed by rigid shielded layer 46 is patterned
The specific part 461 of layer 46, the specific part 451 of amorphous silicon layer 45, drain/source material layer 44 specific part 441, be lightly doped
The subdivision 4111 of the subdivision 4311 of the remaining portions 431 of layer 43 and the remaining portions 411 of substrate 41, to form groove knot
Structure 47, the remaining portions 462 of rigid shielded layer 46, amorphous silicon layer 45 remaining portions 452, drain/source material layer 44 retention
The remaining portions 412 of part 442, the remaining portions 432 of lightly-doped layer 43 and substrate 41.The remaining portions 452 of amorphous silicon layer 45
Top 4521 comprising top surface 452A and with top surface 452A.The remaining portions 442 of drain/source material layer 44 include top table
Face 442A and side wall 442B.The remaining portions 432 of lightly-doped layer 43 include top surface 432A and basal surface 432B.
The step of providing workpiece 906 continues to be described below.Groove structure 47 is filled up with isolation dielectric structure 48.By removal
Isolate the specific part 481 of dielectric structure 48 and the remaining portions 462 of rigid shielded layer 46 and expose the retention of amorphous silicon layer 45
The top surface 452A of part 452 and the remaining portions 482 for forming isolation dielectric structure 48.Isolate the remaining portions of dielectric structure 48
482 include top surface 482A and side wall 482B, and the top surface 452A of the remaining portions 452 of amorphous silicon layer 45 is with isolating dielectric knot
The top surface 482A of the remaining portions 482 of structure 48 is flushed.
The step of providing workpiece 906 continues to be described below.The shape in the top 4521 of the remaining portions 452 of amorphous silicon layer 45
Into drain/source material layer 49, to form the remaining portions 453 of amorphous silicon layer 45 under drain/source material layer 49, to form workpiece
906.Drain/source material layer 49 includes top surface 49A.The remaining portions 442 of drain/source material layer 44 and amorphous silicon layer 45
Remaining portions 453 are strip drain/source material sections 447 and channel material area respectively.The remaining portions of drain/source material layer 44
442 side wall 442B is the side wall 442B of strip drain/source material sections 447, and is coupled in the retention portion of isolation dielectric structure 48
Divide 482 side wall 482B.
In certain embodiments, the step of forming column-like paths layer 458 is described below.On the top of drain/source material layer 49
Photoresist pattern layer 50 is formed on the top surface 482A of the remaining portions 482 of surface 49A and isolation dielectric structure 48, with exposure
The relevant portion 49A1 of the top surface 49A of drain/source material layer 49.By photoresist pattern layer 50, drain/source material layer is removed
The subdivision 4531 of 49 specific part 491 and the remaining portions 453 of amorphous silicon layer 45, to form groove structure 51 and exposure
The relevant portion 442A1 of the top surface 442A of the remaining portions 442 of drain/source material layer 44.Remove photoresist pattern layer 50.
The step of forming column-like paths layer 458 continues to be described below.By the remaining portions for removing isolation dielectric structure 48
482 subdivision 4821, forms groove structure 52, the remaining portions 492 of drain/source material layer 49,458 and of column-like paths layer
Isolate the side wall 442B of the remaining portions 483 of dielectric structure 48 and the remaining portions 442 of exposure drain/source material layer 44.Column
Channel layer 458 includes peripheral sidewalls 454A.The remaining portions 492 of drain/source material layer 49 form cap layers drain/source 498, and wrap
492A containing top surface and peripheral sidewalls 492B.The remaining portions 483 of isolation dielectric structure 48 include top surface 483A.Isolate dielectric
The top surface 483A of the remaining portions 483 of structure 48 is higher than the basal surface 432B of the remaining portions 432 of lightly-doped layer 43 and is less than
The top surface 432A of the remaining portions 432 of lightly-doped layer 43.
In certain embodiments, the method for manufacturing memory device 914 further includes the following steps.In drain/source material layer 49
The top surface 492A and peripheral sidewalls 492B of remaining portions 492, column-like paths layer 458 peripheral sidewalls 454A, draw/source electrode material
The relevant portion 442A1 of the top surface 442A of the remaining portions 442 of the bed of material 44, the remaining portions 442 of drain/source material layer 44
On the top surface 483A of the remaining portions 483 of side wall 442B and isolation dielectric structure 48, oxide skin(coating) 531 is formed.In oxide
Charge trapping material layers 532 are formed on layer 531.Oxide skin(coating) 533 is formed on Charge trapping material layers 532.In oxide skin(coating)
Grid 558 is formed on 533.
Due to the influence that short-channel effect, process variation and reliability reduce, further reduce of planar devices faces
The challenge of extreme.Memory device 20 or 914 in the present invention includes following features.The present invention provides a kind of for forming memory
The technique of Cellular structure, the memory cell structure include the multi-grid structure around ONO structure.Memory device in the present invention
20 or 914 offer mechanism are to improve short-channel effect.Memory device 20 or 914 in this exposure provides mechanism so that memory
The channel length of device 20 or 914 from gate cd influence.Memory device 20 or 914 in the present invention provides machine
Make to increase its passage length.
The above described is only a preferred embodiment of the present invention, not make limitation in any form to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, without departing from the scope of the present invention, when the technology contents using the disclosure above make a little change or modification
For the equivalent embodiment of equivalent variations, as long as being the content without departing from technical solution of the present invention, the technical spirit according to the present invention
Any simple modification, equivalent change and modification made to above example, in the range of still falling within technical solution of the present invention.
Claims (7)
1. a kind of memory device, it is characterised in that include：
Substrate；The substrate includes：
Body part, the groove comprising table top and adjacent to the table top；
Lightly doped district, is arranged on the table top, and includes top surface and basal surface；And
Isolate dielectric layer, be arranged on the groove, and it is light higher than this comprising top surface, wherein top surface of the isolation dielectric layer
The basal surface of doped region, and less than the top surface of the lightly doped district；
Column-like paths layer, is arranged on the substrate, and includes peripheral sidewalls；
Electric charge capture layer, around the peripheral sidewalls of the column-like paths layer；
Strip drain/source, is arranged between the lightly doped district and the column-like paths layer；
Cap layers drain/source, is arranged on the column-like paths layer, and the top table comprising peripheral sidewalls and adjacent to the peripheral sidewalls
Face, the wherein electric charge capture layer more surround the peripheral sidewalls of the cap layers drain/source, and the table top, the lightly doped district, the strip
Drain/source, the column-like paths layer and cap layers drain/source arrangement are in alignment；
First oxide skin(coating), is arranged at the electric charge capture layer and the strip drain/source, the electric charge capture layer and the column-like paths
Between layer and the electric charge capture layer and the cap layers drain/source；
Second oxide skin(coating), is arranged on the electric charge capture layer；And
Grid, is arranged on second oxide skin(coating), and around the peripheral sidewalls and the cap layers drain/source of the column-like paths layer
The peripheral sidewalls.
2. memory device according to claim 1, it is characterised in that：
The strip drain/source include top surface, the first side wall and on the first side wall opposite of the strip drain/source second
The top surface of side wall, wherein the strip drain/source includes the first sublist face contacted with the column-like paths layer and extends from this
The second sublist face in the first sublist face and the 3rd sublist face, and this second with the 3rd sublist face positioned at the column-like paths layer
Not homonymy；And
The electric charge capture layer cover the top surface of the cap layers drain/source, the strip drain/source the first side wall, this second
Side wall and second top surface for isolating dielectric layer with the 3rd sublist face and this.
A kind of 3. method for manufacturing memory device as claimed in claim 1, it is characterised in that comprise the steps of：
Workpiece is provided, the wherein workpiece includes the strip drain/source material sections with side wall, is arranged at the strip drain/source material
Expect the channel material area in area and cover the isolation dielectric material area of the side wall of the strip drain/source material sections；And
By the specific part and the specific part in the isolation dielectric material area for removing the channel material area, exposed strip leakage/
The side wall in source electrode material area and the remaining portions formation column-like paths floor for making the channel material area.
4. according to the method described in claim 3, it is characterized in that the step of providing the workpiece includes substep：
Substrate is provided；
The first dielectric layer is formed on the substrate；
Lightly-doped layer is formed in the substrate under first dielectric layer, is stayed with forming the first of the substrate under the lightly-doped layer
Nonresident portion；
The first drain/source material layer is formed in the lightly-doped layer under first dielectric layer, with the first drain/source material
The first remaining portions of the lightly-doped layer are formed under layer, wherein first remaining portions of the lightly-doped layer include top surface and bottom
Surface；
Remove first dielectric layer；
Amorphous silicon layer is formed in the first drain/source material layer；
Rigid shielded layer is formed on the amorphous silicon layer；
By pattern the rigid shielded layer and remove the specific part of the rigid shielded layer, the amorphous silicon layer specific part,
The specific part of the first drain/source material layer, the subdivision of first remaining portions of the lightly-doped layer and the substrate should
The subdivision of first remaining portions, with formed first groove structure, the remaining portions of the rigid shielded layer, the amorphous silicon layer
One remaining portions, the remaining portions of the first drain/source material layer, the second remaining portions and the substrate of the lightly-doped layer
The second remaining portions, wherein first remaining portions of the amorphous silicon layer include top surface and with the top surface top,
And the remaining portions of the first drain/source material layer include top surface and side wall；
The first groove structure is filled up with isolation dielectric structure；
The non-crystalline silicon is exposed by the specific part of the isolation dielectric structure and the remaining portions of the rigid shielded layer are removed
The top surface of first remaining portions of layer simultaneously forms the first remaining portions of the isolation dielectric structure, wherein the isolation dielectric
First remaining portions of structure include top surface and side wall, and the top surface of first remaining portions of the amorphous silicon layer with
The top surface of first remaining portions of the isolation dielectric structure flushes；And
The second drain/source material layer is formed in the top of first remaining portions of the amorphous silicon layer, with this second leakage/
The second remaining portions of the amorphous silicon layer are formed under source electrode material layer, to form the workpiece, wherein：
The second drain/source material layer includes top surface；
The remaining portions of the first drain/source material layer and second remaining portions of the amorphous silicon layer are the strip respectively
Drain/source material sections and the channel material area；And
The side wall of the remaining portions of the first drain/source material layer is the side wall of the strip drain/source material sections, and coupling
Together in the side wall of first remaining portions of the isolation dielectric structure.
5. according to the method described in claim 4, it is characterized in that：
The step of forming the column-like paths layer includes substep：
In the top surface of the top surface and first remaining portions of the isolation dielectric structure of the second drain/source material layer
Upper formation photoresist pattern layer, to expose the relevant portion of the top surface of the second drain/source material layer；
By the photoresist pattern layer, remove the second drain/source material layer specific part and the amorphous silicon layer this second
The subdivision of remaining portions, to form second groove structure and expose being somebody's turn to do for the remaining portions of the first drain/source material layer
The relevant portion of top surface；
Remove the photoresist pattern layer；And
By remove the isolation dielectric structure first remaining portions subdivision, formed the 3rd groove structure, this second leakage/
Second remaining portions of the remaining portions of source electrode material layer, the column-like paths layer and the isolation dielectric structure, and exposure this
The side wall of the remaining portions of one drain/source material layer, wherein the column-like paths layer include peripheral sidewalls, second leakage/source
The remaining portions of pole material layer include top surface and peripheral sidewalls, and second remaining portions of the isolation dielectric structure include top
Surface, and the top surface of second remaining portions of the isolation dielectric structure being somebody's turn to do higher than the remaining portions of the lightly-doped layer
Basal surface and the top surface for being less than the remaining portions of the lightly-doped layer；
This method further includes the following steps：
The top surface and the peripheral sidewalls, the column-like paths layer in the remaining portions of the second drain/source material layer should
Peripheral sidewalls, the relevant portion of the top surface of the remaining portions of the first drain/source material layer, first drain/source
On the top surface of the side wall of the remaining portions of material layer and second remaining portions of the isolation dielectric structure, formed
First oxide skin(coating)；
Charge trapping material layers are formed on first oxide skin(coating)；
The second oxide skin(coating) is formed on the Charge trapping material layers；And
Grid is formed on second oxide skin(coating).
6. a kind of memory device, it is characterised in that include：
Substrate；The substrate includes：
Body part, the groove comprising table top and adjacent to the table top；
Lightly doped district, is arranged on the table top, and includes top surface and basal surface；And
Isolate dielectric layer, be arranged on the groove, and it is light higher than this comprising top surface, wherein top surface of the isolation dielectric layer
The basal surface of doped region, and less than the top surface of the lightly doped district；
Strip drain/source, is arranged on the substrate；And
Column-like paths layer, is arranged in the strip drain/source, which is arranged at the lightly doped district and the column is led to
Between channel layer；
Cap layers drain/source, is arranged on the column-like paths layer, and the top table comprising peripheral sidewalls and adjacent to the peripheral sidewalls
Face, the wherein table top, the lightly doped district, the strip drain/source, the column-like paths layer and the cap layers drain/source are arranged in one
Bar straight line；
Electric charge capture layer, around the peripheral sidewalls of the column-like paths layer and the peripheral sidewalls of the cap layers drain/source；
First oxide skin(coating), is arranged at the electric charge capture layer and the strip drain/source, the electric charge capture layer and the column-like paths
Between layer and the electric charge capture layer and the cap layers drain/source；
Second oxide skin(coating), is arranged on the electric charge capture layer；And
Grid, is arranged on second oxide skin(coating), and around the peripheral sidewalls and the cap layers drain/source of the column-like paths layer
The peripheral sidewalls.
7. memory device according to claim 6, it is characterised in that：
The strip drain/source include top surface, the first side wall and on the first side wall opposite of the strip drain/source second
The top surface of side wall, wherein the strip drain/source includes the first sublist face contacted with the column-like paths layer and extends from this
The second sublist face in the first sublist face and the 3rd sublist face, and this second with the 3rd sublist face positioned at the column-like paths layer
Not homonymy；And
The electric charge capture layer cover the top surface of the cap layers drain/source, the strip drain/source the first side wall, this second
Side wall and second top surface for isolating dielectric layer with the 3rd sublist face and this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410313511.9A CN105321885B (en) | 2014-07-02 | 2014-07-02 | Memory device and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410313511.9A CN105321885B (en) | 2014-07-02 | 2014-07-02 | Memory device and its manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105321885A CN105321885A (en) | 2016-02-10 |
| CN105321885B true CN105321885B (en) | 2018-04-13 |
Family
ID=55248988
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410313511.9A Active CN105321885B (en) | 2014-07-02 | 2014-07-02 | Memory device and its manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105321885B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1400669A (en) * | 2001-06-26 | 2003-03-05 | 因芬尼昂技术股份公司 | Longitudinal transistor, memory device and longitudinal transistor making process |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070034922A1 (en) * | 2005-08-11 | 2007-02-15 | Micron Technology, Inc. | Integrated surround gate multifunctional memory device |
| KR100866966B1 (en) * | 2007-05-10 | 2008-11-06 | 삼성전자주식회사 | Non-volatile memory device, method of fabricating the same, and semiconductor package |
-
2014
- 2014-07-02 CN CN201410313511.9A patent/CN105321885B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1400669A (en) * | 2001-06-26 | 2003-03-05 | 因芬尼昂技术股份公司 | Longitudinal transistor, memory device and longitudinal transistor making process |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105321885A (en) | 2016-02-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102358686B1 (en) | Semiconductor storage device, manufacturing method thereof, and electronic device including storage device | |
| CN109285836B (en) | Semiconductor memory device, method of manufacturing the same, and electronic apparatus including the same | |
| US9379004B1 (en) | Semiconductor device with air gap and method for fabricating the same | |
| KR102033785B1 (en) | Semiconductor device having buried metal silicide layer and method of fabricating the same | |
| US20140008719A1 (en) | Semiconductor device and a bit line and the whole of a bit line contact plug having a vertically uniform profile | |
| WO2012052298A1 (en) | Vertical semiconductor memory device and manufacturing method thereof | |
| US9646980B2 (en) | Logic compatible flash memory cells | |
| WO2023011085A1 (en) | Nor type memory device and manufacturing method therefor, and electronic device comprising memory device | |
| WO2023097902A1 (en) | Semiconductor structure manufacturing method and semiconductor structure | |
| TWI490984B (en) | Memory device and method for manufacturing the same | |
| KR20130047410A (en) | Semiconductor device and method for fabricating the same | |
| CN208819879U (en) | Integrated circuit memory | |
| KR20220090208A (en) | Semiconductor memory devices | |
| US20140302651A1 (en) | Method for manufacturing semiconductor device with first and second gates over buried bit line | |
| CN105321885B (en) | Memory device and its manufacture method | |
| CN108122840A (en) | A kind of semiconductor devices and preparation method, electronic device | |
| KR20130107542A (en) | Capacitorless memory device | |
| US20240120382A1 (en) | Storage device, method for manufacturing the same, and electronic apparatus including storage device | |
| US11621271B2 (en) | Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof | |
| US10868141B2 (en) | Spacer structure and manufacturing method thereof | |
| JP2013098532A (en) | Semiconductor device and method of forming the same | |
| CN114256158A (en) | Manufacturing method of semiconductor structure and semiconductor structure | |
| TWI566332B (en) | Memory device and method for manufacturing the same | |
| TWI523235B (en) | Semiconductor device and manufacturing method thereof | |
| US8664709B2 (en) | Non-volatile memory and fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |