CN105306075A - Best polarity search method for power consumption of three-value FPRM circuit - Google Patents

Abstract

The invention discloses a best polarity search method for power consumption of a three-value FPRM circuit. The best polarity search method comprises the following steps: at first, expressing a three-value FPRM circuit by use of the three-value FPRM logic function under p polarity, decomposing multi-input operation contained in the three-value FPRM logic function to obtain multiple two-input module 3 addition doors and multiple two-input module 3 multiplication doors under the p polarity, using power consumption generated by the two-input module 3 addition doors and the two-input module 3 multiplication doors as the power consumption of the three-value FPRM circuit under the p polarity, establishing a power consumption estimation model of the three-value FPRM circuit, and finally, using a genetic simulated annealing algorithm to carry out best polarity search on the power consumption of the three-value FPRM circuit to optimize the power consumption of the three-value FPRM circuit. The best polarity search method has the advantages of achieving the best polarity search of the power consumption of the three-value FPRM circuit to optimize the power consumption of the three-value FPRM circuit; 13 MCNC Benchmark circuits are randomly adopted to carry out simulation verification, compared with 0 polarity, in the best polarity of the power consumption searched by the best polarity search method disclosed by the invention, the number of the module 3 addition doors is saved for 57.6% on average, the number of the two-input module 3 multiplication doors is saved for 46.25% on average, and the power consumption is saved for 73.98%.

Description

Method for searching power consumption optimal polarity of three-value FPRM circuit

Technical Field

The invention relates to a power consumption optimization method for a three-value FPRM circuit, in particular to a power consumption optimal polarity search method for the three-value FPRM circuit.

Background

With the continuous development of the scale and integration of integrated circuits, digital circuits must suffer from problems of power consumption, area, speed, etc. Most of traditional digital circuits adopt binary logic, but the low information content of binary signals becomes a main factor restricting the development of integrated circuits. The multi-value logic circuit increases the information carrying capacity of a single wire, can effectively improve the utilization rate of space or time, reduces the connecting wires of a digital system, and saves the circuit area and the cost. The three-valued logic with the base number of 3 has the smallest base number in a multi-valued logic algebraic system, is easy to realize and is representative.

Any logic function can be represented by Boolean logic and Reed-Muller (RM) logic, and compared with the traditional Boolean logic circuit, the RM logic-based circuit has the following advantages in three aspects: first, among some functional circuits (e.g., communication circuits, parity check circuits, arithmetic circuits, etc.), circuits represented by RM logic exhibit great advantages in terms of power consumption, area, speed, and the like; secondly, the circuit expressed by RM logic has strong testability; finally, the circuit structure represented by the RM logic is more compact. The RM logic function generally adopts two expressions of Fixed-polarity reed-Muller (FPRM) and Mixed-polarity reed-Muller (MPRM). There are 3 in the three-valued FPRM logical function of the n variableⁿA fixed polarity, 3ⁿA fixed polarity corresponds to 3ⁿThe simplicity or non-simplicity of the ternary FPRM expression is determined by the corresponding polarity, and the simplicity or non-simplicity of the ternary FPRM expression directly determines performance indexes such as power consumption and area of the ternary FPRM circuit, so that the polarity has great influence on the performance indexes such as power consumption and area of the FPRM circuit.

Due to the many advantages of multivalued logic and RM logic, many experts and scholars at home and abroad have studied multivalued RM logic. However, experts and scholars at home and abroad mainly concentrate on researching the polarity conversion technology of the multi-valued RM logic circuit, and do not research the power consumption optimization technology of the multi-valued RM logic circuit. Therefore, a power consumption optimal polarity searching method of the three-value FPRM circuit is designed based on the simulated annealing genetic algorithm to search the power consumption optimal polarity of the three-value FPRM circuit, and the method has important significance for power consumption optimization of the three-value FPRM circuit.

Disclosure of Invention

The invention aims to provide a method for searching the optimal polarity of the power consumption of a three-value FPRM circuit. The method can quickly search the optimal polarity of the power consumption, thereby realizing the optimization of the power consumption.

The technical scheme adopted by the invention for solving the technical problems is as follows: a power consumption optimal polarity searching method for a three-value FPRM circuit comprises the following steps:

establishing a power consumption estimation model of a three-value FPRM circuit:

phi-1 represents a three-valued FPRM circuit in the form of a three-valued FPRM logic function:

$f^p(x_{n-1},x_{n-2},\mathrm{...},x_0)=\⊕\underset{i=0}{\overset{3^n-1}{\Σ}}{a}_i*\underset{j=0}{\overset{n-1}{\Π}}{\stackrel{\·}{x}}_j^{i_j}---\left(1\right)$

wherein n is a function f^p(x_n-1,x_n-2,…,x₀) Number of input variables, x_n-1,x_n-2,…,x₀Representing function f^p(x_n-1,x_n-2,…,x₀) N input variables of (a) and p represents a function f^p(x_n-1,x_n-2,…,x₀) Of (1), the polarity p being represented in ternary form as p_n-1p_n-2…p₀，p_j∈ {0,1,2}, j-0, 1,2, …, n-1, ⊕ denotes a modulo-3 addition, ∑ is the cumulative sign, the sign "×" is the multiplication sign, and the subscript i-0, 1,2, …,3ⁿ1, i is represented in ternary form as i_n-1i_n-2…i₀，a_iIs the FPRM coefficient; a is_i∈ {0,1,2}, pi represents a modulo-3 multiplication operation,the expansion formula is as follows:wherein i_j∈{0,1,2}, $\begin{array}{cc}{\stackrel{\·}{x}}_j=(x_j\⊕p_j),& {\stackrel{\·}{x}}_j^0=1,{\stackrel{\·}{x}}_j^1={\stackrel{\·}{x}}_j,{\stackrel{\·}{x}}_j^2={\stackrel{\·}{x}}_j*{\stackrel{\·}{x}}_j\end{array},$ Polarity p and subscript i determine the variablesA representation of (a);

the ternary FPRM logical function under the polarity of-2 p comprises two types of multi-input operations, wherein the two types of multi-input operations are respectively a multi-input modulo-3 addition operation and a multi-input modulo-3 multiplication operation, the ternary FPRM logical function is decomposed into a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations according to a ternary FPRM logical function expansion formula, then each multi-input operation is respectively decomposed into a two-input operation, and the two-input modulo-3 addition operation and the two-input modulo-3 multiplication operation are obtained, and the specific decomposition process is as follows:

taking the 1 st input variable and the 2 nd input variable of the multi-input operation as two input variables of the first second input operation to obtain an output variable of the first second input operation; taking the output variable of the first second input operation and the 3 rd input variable of the multiple input operation as two input variables of the second input operation to obtain the output variable of the second input operation; taking the output variable of the second two-input operation and the 4 th input variable of the multiple-input operation as two input variables of the third two-input operation to obtain the output variable of the third two-input operation; repeating the operation steps until all the input variables of the multi-input operation are used as the input variables of the two-input operation, and completing the decomposition of the multi-input operation;

decomposing the three-valued FPRM logic function under the p polarity to obtain a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations, wherein the multi-input modulo-3 addition operations are also called multi-input modulo-3 addition gates, the multi-input modulo-3 multiplication operations are also called multi-input modulo-3 multiplication gates, the number of the multi-input modulo-3 addition gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as N, and the number of the multi-input modulo-3 multiplication gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as W; decomposing each multi-input modulo-3 addition operation to obtain a plurality of binary input modulo-3 addition operations, decomposing each multi-input modulo-3 multiplication operation to obtain a plurality of binary input modulo-3 multiplication operations, wherein the binary input modulo-3 addition operation is also called a binary input modulo-3 addition gate, and the binary input modulo-3 multiplication operation is also called a binary input modulo-3 multiplication gate; recording the number of the two input module 3 adding gates after the H-th multiple input module 3 adding gates are decomposed as N_HH ═ 1,2, …, N; recording the number of the second input modulo 3 times gate after the o-th multiple input modulo 3 times gate is decomposed as W_o，o＝1,2,…,W；

Firstly, power consumption caused by a two-input modulo-3 adding gate and a two-input modulo-3 multiplying gate obtained after a ternary FPRM logic function under the p polarity is decomposed is taken as power consumption of a ternary FPRM circuit under the p polarity, power consumption caused by the two-input modulo-3 adding gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, power consumption caused by the two-input modulo-3 multiplying gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, the switching activity of the gate circuit is expressed by the output variable probability of an output end of the gate circuit, power consumption caused by the two-input modulo-3 adding gate is expressed by the output variable probability of an output end of the gate circuit, and power consumption caused by the two-input modulo-3 multiplying gate is expressed by;

① -4 calculating the output variable probability of the kth second input modulo-3 adding gate after H multiple input modulo-3 adding gate decomposition according to the formulas (2), (3) and (4), wherein k is 1,2, …, N_H；

P₁(k)_H＝Pk_y11*Pk_y20+Pk_y10*Pk_y21+Pk_y12*Pk_y22(2)

P₂(k)_H＝Pk_y12*Pk_y20+Pk_y11*Pk_y21+Pk_y10*Pk_y22(3)

P₀(k)_H＝1-P₁(k)_H-P₂(k)_H(4)

Calculating the output variable probability of the g-th two-input modulo 3 times gate after the o-th multiple-input modulo 3 times gate decomposition according to the formulas (5), (6) and (7), wherein g is 1,2, …, W_o：

Q₁(g)_o＝Qg_r11*Qg_r21+Qg_r12*Qg_r22(5)

Q₂(g)_o＝Qg_r11*Qg_r22+Qg_r12*Qg_r21(6)

Q₀(g)_o＝1-Q₁(g)_o-Q₂(g)_o(7)

Wherein,P₁(k)_Hdenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 1, P₂(k)_HDenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 2, P₀(k)_HDenotes the probability that the k-th two-input modulo-3-add-gate output variable after the H-th multiple-input modulo-3-add-gate decomposition is 0, y1 and y2 denote the two input variables of the two-input modulo-3-add-gate, Pk_y1mRepresents the probability that the input variable y1 is m in the kth two-input modulo 3 adder, m ∈ {0,1,2}, Pk_y2mDenotes the probability that the input variable y2 is m in the k-th two-input modulo-3 adder gate, and when k is 1, Pk is_y1mProbability of m being the 1 st input variable for multiple-input modulo-3 addition, Pk_y2mProbability of m being the 2 nd input variable for multiple input modulo 3 addition, when k>1 time, Pk_y1mFor the k-1 th two-input modulo-3 plus-gate output variable, the probability of m, Pk_y2mProbability that the (k + 1) th input variable of the add gate for multiple input modulo 3 is m;

Q₁(g)_odenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 1, Q₂(g)_oDenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 2, Q₀(g)_oDenotes the probability that the output variable of the g-th multi-input modulo 3 gate after the o-th multi-input modulo 3 gate decomposition is 0, r1 and r2 denote the two input variables of the two-input modulo 3 gate, Qg_r1mRepresents the probability that the input variable r1 is m in the g-th two-input modulo 3 multiplication gate, Qg_r2mRepresents the probability that the g-th two-input modulo 3 multiplied by the input variable r2 in the gate is m; when g is 1, Qg_r1mProbability of the 1 st input variable being m, Qg, for a multiple-input modulo-3 multiplication_r2mProbability of m being the 2 nd input variable of the multiple input modulo 3 multiplication, when g>At 1 hour, Qg_r1mFor the g-1 st probability that the two-input modulo 3 is the output variable of m, Qg_r2mThe probability that the g +1 th input variable of the multiple input modulo 3 by gate is m;

input variable x_jThe probabilities of 1 and 2 are determined byProbability pairs generated by random functions (P1, P2), P0 is 1-P1-P2; p0, P1 and P2 are each a value between 0 and 1, P0 denotes the probability that the input variable is 0, P1 denotes the probability that the input variable is 1, and P2 denotes the probability that the input variable is 2;

firstly, calculating the power consumption of the three-value FPRM circuit according to the output variable probability of the two-input modulo 3 addition gate and the output variable probability of the two-input modulo 3 multiplication gate, and expressing a power consumption estimation model of the three-value FPRM circuit as follows:

$E_{swd}=2\left(\underset{H=1}{\overset{N}{\Σ}}\left(\underset{k=1}{\overset{N_H}{\Σ}}\left(P_1{\left(k\right)}_H+P_2{\left(k\right)}_H\right)\right)+\underset{o=1}{\overset{W}{\Σ}}\left(\underset{g=1}{\overset{W_o}{\Σ}}\left(Q_1{\left(g\right)}_o+Q_2{\left(g\right)}_o\right)\right)\right)---\left(8\right)$

wherein E is_swdThe power consumption of the three-value FPRM circuit under the p polarity is represented, N is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed, and W is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed;

setting a fitness function for calculating individual fitness in the simulated annealing genetic algorithm:

according to the power consumption estimation model, a fitness function for calculating individual fitness in the simulated annealing genetic algorithm is set: in the simulated annealing genetic algorithm, the higher the fitness is, the stronger the adaptability of an individual is, but the optimal polarity of power consumption requires the lower the power consumption is, the better the fitness is, so that in order to facilitate the combination of the two, the inverse of the power consumption is adopted to represent the fitness, and the fitness function is obtained as follows:

fitness＝α/E_swd

wherein, the symbol "/" represents a division operation symbol, and the fitness represents the fitness of an individual; e_swdα is an amplification factor, and the value is a natural number which is greater than or equal to 1000;

establishing a corresponding relation between a three-value FPRM circuit and a simulated annealing genetic algorithm:

the simulated annealing genetic algorithm comprises the following key elements: individual, individual fitness, individual with the maximum fitness, cross operation, mutation operation and annealing selection operation;

the power consumption optimization of the three-value FPRM circuit comprises the following key elements: polarity, power consumption of corresponding polarity, optimal polarity, minimum power consumption, polarity exchange, polarity mutation and polarity conversion;

mapping the individuals to a three-valued FPRM circuit power consumption optimization, expressed as polarity; mapping the fitness of the individual to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the power consumption of corresponding polarity; mapping the individual with the maximum fitness to a three-value FPRM circuit for power consumption optimization, and expressing the power consumption optimization as the optimal polarity; mapping the maximum fitness to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the minimum power consumption; mapping the crossover operation to a three-valued FPRM circuit power consumption optimization, expressed as polarity interchange; mapping the variant operation to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as polarity mutation; mapping the annealing selection operation to a three-valued FPRM circuit power consumption optimization, expressed as a polarity inversion;

setting relevant parameters of the simulated annealing genetic algorithm:

the simulated annealing genetic algorithm needs to set 4 parameters: individual size w, individual number of iterationsz, gene mutation probability q, onset temperature T₀(ii) a Let the individual scale w be 50, the individual iteration number z be 20, the gene mutation probability q be 0.01, and the starting temperature T₀＝100℃；

Obtaining the maximum fitness individual and the maximum fitness by adopting a simulated annealing genetic algorithm, wherein the maximum fitness individual is the power consumption optimal polarity of the three-value FPRM circuit; the maximum fitness is the minimum power consumption of the three-value FPRM circuit.

The specific process of obtaining the individual with the maximum fitness and the maximum fitness by adopting the simulated annealing genetic algorithm in the fifth step is as follows:

fifthly, -1, generating w individuals represented by an n-bit ternary system by using a random function rand (), and respectively marking the w individuals as P1, P2, … and Pw;

fifthly-2, calculating the fitness of the v individual Pv through a fitness function, wherein v is 1,2, 3, …, w, and obtaining the fitness of individuals P1, P2, … and Pw;

fifthly-3, comparing the fitness of individuals P1, P2, … and Pw, screening the individual with the maximum fitness as the individual with the maximum fitness, and recording the individual with the maximum fitness and the maximum fitness;

fifthly-4, the individuals P1, P2, … and Pw are subjected to cross operation to generate the individuals F1, F2, … and Fw: if w is an even number, performing crossing operation on P1 and P2, P3 and P4, …, and Pw-1 and Pw in pairs respectively; if w is an odd number, carrying out cross operation on P1 and P2, P3 and P4, …, Pw-2 and Pw-1 in pairs respectively, wherein Pw does not participate in the cross operation, and Fw directly inherits Pw; performing cross operation on two individuals Pe and Pu to generate individuals Fe and Fu, wherein the specific process comprises the following steps: assigning Pe to fe and Pu to fu, randomly generating an n-bit binary code, marking the n-bit binary code as A, updating fe and fu according to the binary code A, and keeping the h bit of fe and fu unchanged when the h bit of the binary code A is 1; when the h bit of the binary code a is 0, the h bit of Fe inherits the h bit of Fu, the h bit of Fu inherits the h bit of Fe, h is 1,2, 3, …, n, Fe after the completion of the crossover operation is recorded as Fe, and Fu after the completion of the crossover operation is recorded as Fu; wherein u is e +1, when w is an even number, e is 1, 3, 5, …, w-1; u-2, 4, 6, …, w; when w is an odd number, e is 1, 3, 5, …, w-2; u-2, 4, 6, …, w-1;

fifthly, calculating the fitness of the v individual Fv through a fitness function to obtain the fitness of the individuals F1, F2, … and Fw;

fifthly-6, comparing the fitness of the individuals F1, F2, … and Fw with the fitness of the individual with the maximum fitness at present, and updating the individual with the maximum fitness and the maximum fitness;

7, carrying out mutation operation on individuals F1, F2, … and Fw: generating a value between 0 and 1 for each bit of the Fv by using a random function rand (), if the value is less than the gene mutation probability q, the bit corresponding to the value is the mutation bit of the Fv, and the mutation bit of the Fv is mutated, wherein the mutation rule is '0 → 1, 1 → 2, 2 → 0';

fifthly-8, treating the individuals F1, F2, … and Fw according to the steps of fifthly-5 to fifthly-6 to obtain the updated individuals with the maximum fitness and the maximum fitness;

fifthly-9, sorting individuals P1, P2, … and Pw according to the size of the fitness value, and sorting individuals F1, F2, … and Fw according to the size of the fitness value; selecting 2w/3 individuals with optimal fitness values from individuals P1, P2, … and Pw and individuals F1, F2, … and Fw respectively to form a new group of individuals, wherein the new individuals comprise 4w/3 individuals;

-10 multiple rounds of annealing selection on a new group of individuals: in each round of annealing selection, firstly generating an annealing temperature according to a formula (9), sequentially calculating the selection probability P (c) of each individual according to a formula (10) for the annealing temperature, and simultaneously generating a screening probability t by using a random function rand (), wherein 0< t < 1; when the individual selection probability is greater than the screening probability, the individual is selected in the round of annealing selection, the selected individual does not participate in the next round of annealing selection, other unselected individuals enter the next round of annealing selection, and the annealing selection is finished until w individual updating individuals P1, P2, … and Pw are screened;

T_l＝1/ln(l/T₀+1)(9)

$P\left(c\right)=e^{f\left(c\right)/T_l}/\underset{d=0}{\overset{4w/3}{\&Sigma;}}{e}^{f\left(d\right)/T_l}---\left(10\right)$

wherein, T_lDenotes the annealing temperature of the first round, l ═ 1,2, …; when the first round of annealing selection is carried out, l is 1, when the second round of annealing selection is carried out, l is 2, and the rest can be analogized; ln represents a logarithmic operation; t is₀Represents the initial temperature; p (c) represents the probability of the individual c; (f) (c) indicates the fitness value of the c-th individual of the new individuals; c is 1,2, 3, …, 4 w/3; (d) indicates the fitness value of the d-th individual of the new individuals; d is 1,2, 3, …, 4 w/3;

fifthly-11, processing the individuals P1, P2, … and Pw updated in the step fifthly-10 according to the step fifthly-2 to the step fifthly-3 to obtain the individual with the maximum fitness and the maximum fitness;

fifthly-12, repeating the steps of fifthly-4 to fifthly-11 until the individual iteration times z are met, and finishing the algorithm to obtain the individual with the maximum fitness and the maximum fitness;

fifthly-13, outputting the maximum fitness individual and the maximum fitness obtained in the last time, wherein the maximum fitness individual is the optimal polarity of the three-value FPRM circuit; the maximum fitness is the minimum power consumption of the three-value FPRM circuit.

Compared with the prior art, the method has the advantages that the ternary FPRM circuit is represented by a ternary FPRM logic function under the p polarity, then three-input operation contained in the ternary FPRM logic function is decomposed to obtain a plurality of two-input modulo-3 addition gates and a plurality of two-input modulo-3 multiplication gates under the p polarity, power consumption caused by the two-input modulo-3 addition gates and the two-input modulo-3 multiplication gates is used as power consumption of the ternary FPRM circuit under the p polarity, a power consumption estimation model of the ternary FPRM circuit is constructed, and finally, the power consumption optimal polarity search is carried out on the ternary FPRM circuit by adopting a simulated annealing genetic algorithm to obtain the power consumption optimal polarity search and the minimum power consumption; the method realizes the power consumption optimal polarity search of the ternary FPRM circuit by combining the established power consumption estimation model of the ternary FPRM circuit with the simulated annealing genetic algorithm, thereby realizing the power consumption optimization of the ternary FPRM circuit; the simulation verification is carried out by randomly adopting 13 MCNCBenchmark circuits, the power consumption optimal polarity searched by the method is compared with 0 polarity, the average saving of the modulo 3 plus gate number is 57.64%, the average saving of the modulo 3 plus gate number is 46.25%, and the average saving of the power consumption is 73.98%.

Detailed Description

The present invention will be described in further detail with reference to examples.

The first embodiment is as follows: a power consumption optimal polarity searching method for a three-value FPRM circuit comprises the following steps:

establishing a power consumption estimation model of a three-value FPRM circuit:

phi-1 represents a three-valued FPRM circuit in the form of a three-valued FPRM logic function:

$f^p(x_{n-1},x_{n-2},\mathrm{...},x_0)=\&CirclePlus;\underset{i=0}{\overset{3^n-1}{\&Sigma;}}{a}_i*\underset{j=0}{\overset{n-1}{\&Pi;}}{\stackrel{\&CenterDot;}{x}}_j^{i_j}---\left(1\right)$

wherein n is a function f^p(x_n-1,x_n-2,…,x₀) Number of input variables, x_n-1,x_n-2,…,x₀Representing function f^p(x_n-1,x_n-2,…,x₀) N input variables of (a) and p represents a function f^p(x_n-1,x_n-2,…,x₀) Of (1), the polarity p being represented in ternary form as p_n-1p_n-2…p₀，p_j∈ {0,1,2}, j-0, 1,2, …, n-1, ⊕ denotes a modulo-3 addition, ∑ is the cumulative sign, the sign "×" is the multiplication sign, and the subscript i-0, 1,2, …,3ⁿ1, i is represented in ternary form as i_n-1i_n-2…i₀，a_iIs the FPRM coefficient; a is_i∈ {0,1,2}, pi represents a modulo-3 multiplication operation,the expansion formula is as follows:wherein i_j∈{0,1,2}, $\begin{array}{cc}{\stackrel{\&CenterDot;}{x}}_j=(x_j\&CirclePlus;p_j),& {\stackrel{\&CenterDot;}{x}}_j^0=1,{\stackrel{\&CenterDot;}{x}}_j^1={\stackrel{\&CenterDot;}{x}}_j,{\stackrel{\&CenterDot;}{x}}_j^2={\stackrel{\&CenterDot;}{x}}_j*{\stackrel{\&CenterDot;}{x}}_j\end{array},$ Polarity p and subscript i determine the variablesA representation of (a);

the ternary FPRM logical function under the polarity of-2 p comprises two types of multi-input operations, wherein the two types of multi-input operations are respectively a multi-input modulo-3 addition operation and a multi-input modulo-3 multiplication operation, the ternary FPRM logical function is decomposed into a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations according to a ternary FPRM logical function expansion formula, then each multi-input operation is respectively decomposed into a two-input operation, and the two-input modulo-3 addition operation and the two-input modulo-3 multiplication operation are obtained, and the specific decomposition process is as follows:

taking the 1 st input variable and the 2 nd input variable of the multi-input operation as two input variables of the first second input operation to obtain an output variable of the first second input operation; taking the output variable of the first second input operation and the 3 rd input variable of the multiple input operation as two input variables of the second input operation to obtain the output variable of the second input operation; taking the output variable of the second two-input operation and the 4 th input variable of the multiple-input operation as two input variables of the third two-input operation to obtain the output variable of the third two-input operation; repeating the operation steps until all the input variables of the multi-input operation are used as the input variables of the two-input operation, and completing the decomposition of the multi-input operation;

decomposing the three-valued FPRM logic function under the p polarity to obtain a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations, wherein the multi-input modulo-3 addition operations are also called multi-input modulo-3 addition gates, the multi-input modulo-3 multiplication operations are also called multi-input modulo-3 multiplication gates, the number of the multi-input modulo-3 addition gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as N, and the number of the multi-input modulo-3 multiplication gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as W; decomposing each multi-input modulo-3 addition operation to obtain a plurality of binary input modulo-3 addition operations, decomposing each multi-input modulo-3 multiplication operation to obtain a plurality of binary input modulo-3 multiplication operations, wherein the binary input modulo-3 addition operation is also called a binary input modulo-3 addition gate, and the binary input modulo-3 multiplication operation is also called a binary input modulo-3 multiplication gate; recording the number of the two input module 3 adding gates after the H-th multiple input module 3 adding gates are decomposed as N_HH ═ 1,2, …, N; recording the number of the second input modulo 3 times gate after the o-th multiple input modulo 3 times gate is decomposed as W_o，o＝1,2,…,W；

Firstly, power consumption caused by a two-input modulo-3 adding gate and a two-input modulo-3 multiplying gate obtained after a ternary FPRM logic function under the p polarity is decomposed is taken as power consumption of a ternary FPRM circuit under the p polarity, power consumption caused by the two-input modulo-3 adding gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, power consumption caused by the two-input modulo-3 multiplying gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, the switching activity of the gate circuit is expressed by the output variable probability of an output end of the gate circuit, power consumption caused by the two-input modulo-3 adding gate is expressed by the output variable probability of an output end of the gate circuit, and power consumption caused by the two-input modulo-3 multiplying gate is expressed by;

① -4 calculating the output variable probability of the kth second input modulo-3 adding gate after H multiple input modulo-3 adding gate decomposition according to the formulas (2), (3) and (4), wherein k is 1,2, …, N_H；

P₁(k)_H＝Pk_y11*Pk_y20+Pk_y10*Pk_y21+Pk_y12*Pk_y22(2)

P₂(k)_H＝Pk_y12*Pk_y20+Pk_y11*Pk_y21+Pk_y10*Pk_y22(3)

P₀(k)_H＝1-P₁(k)_H-P₂(k)_H(4)

Calculating the output variable probability of the g-th two-input modulo 3 times gate after the o-th multiple-input modulo 3 times gate decomposition according to the formulas (5), (6) and (7), wherein g is 1,2, …, W_o：

Q₁(g)_o＝Qg_r11*Qg_r21+Qg_r12*Qg_r22(5)

Q₂(g)_o＝Qg_r11*Qg_r22+Qg_r12*Qg_r21(6)

Q₀(g)_o＝1-Q₁(g)_o-Q₂(g)_o(7)

Wherein, P₁(k)_HDenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 1, P₂(k)_HDenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 2, P₀(k)_HDenotes the probability that the k-th two-input modulo-3-add-gate output variable after the H-th multiple-input modulo-3-add-gate decomposition is 0, y1 and y2 denote the two input variables of the two-input modulo-3-add-gate, Pk_y1mRepresents the probability that the input variable y1 is m in the kth two-input modulo 3 adder, m ∈ {0,1,2}, Pk_y2mDenotes the probability that the input variable y2 is m in the k-th two-input modulo-3 adder gate, and when k is 1, Pk is_y1mProbability of m being the 1 st input variable for multiple-input modulo-3 addition, Pk_y2mProbability of m being the 2 nd input variable for multiple input modulo 3 addition, when k>1 time, Pk_y1mFor the k-1 th two-input modulo-3 plus-gate output variable, the probability of m, Pk_y2mIs a plurality ofThe probability that the (k + 1) th input variable of the input modulo-3 plus gate is m;

Q₁(g)_odenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 1, Q₂(g)_oDenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 2, Q₀(g)_oDenotes the probability that the output variable of the g-th multi-input modulo 3 gate after the o-th multi-input modulo 3 gate decomposition is 0, r1 and r2 denote the two input variables of the two-input modulo 3 gate, Qg_r1mRepresents the probability that the input variable r1 is m in the g-th two-input modulo 3 multiplication gate, Qg_r2mRepresents the probability that the g-th two-input modulo 3 multiplied by the input variable r2 in the gate is m; when g is 1, Qg_r1mProbability of the 1 st input variable being m, Qg, for a multiple-input modulo-3 multiplication_r2mProbability of m being the 2 nd input variable of the multiple input modulo 3 multiplication, when g>At 1 hour, Qg_r1mFor the g-1 st probability that the two-input modulo 3 is the output variable of m, Qg_r2mThe probability that the g +1 th input variable of the multiple input modulo 3 by gate is m;

input variable x_jThe probabilities of 1 and 2 are the pairs of probabilities generated by random functions (P1, P2), P0 ═ 1-P1-P2; p0, P1 and P2 are each a value between 0 and 1, P0 denotes the probability that the input variable is 0, P1 denotes the probability that the input variable is 1, and P2 denotes the probability that the input variable is 2;

firstly, calculating the power consumption of the three-value FPRM circuit according to the output variable probability of the two-input modulo 3 addition gate and the output variable probability of the two-input modulo 3 multiplication gate, and expressing a power consumption estimation model of the three-value FPRM circuit as follows:

$E_{swd}=2\left(\underset{H=1}{\overset{N}{\&Sigma;}}\left(\underset{k=1}{\overset{N_H}{\&Sigma;}}\left(P_1{\left(k\right)}_H+P_2{\left(k\right)}_H\right)\right)+\underset{o=1}{\overset{W}{\&Sigma;}}\left(\underset{g=1}{\overset{W_o}{\&Sigma;}}\left(Q_1{\left(g\right)}_o+Q_2{\left(g\right)}_o\right)\right)\right)---\left(8\right)$

wherein E is_swdThe power consumption of the three-value FPRM circuit under the p polarity is represented, N is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed, and W is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed;

setting a fitness function for calculating individual fitness in the simulated annealing genetic algorithm:

according to the power consumption estimation model, a fitness function for calculating individual fitness in the simulated annealing genetic algorithm is set: in the simulated annealing genetic algorithm, the higher the fitness is, the stronger the adaptability of an individual is, but the optimal polarity of power consumption requires the lower the power consumption is, the better the fitness is, so that in order to facilitate the combination of the two, the inverse of the power consumption is adopted to represent the fitness, and the fitness function is obtained as follows:

fitness＝α/E_swd

wherein, the symbol "/" represents a division operation symbol, and the fitness represents the fitness of an individual; e_swdα is an amplification factor, and the value is a natural number which is greater than or equal to 1000;

establishing a corresponding relation between a three-value FPRM circuit and a simulated annealing genetic algorithm:

the simulated annealing genetic algorithm comprises the following key elements: individual, individual fitness, individual with the maximum fitness, cross operation, mutation operation and annealing selection operation;

the power consumption optimization of the three-value FPRM circuit comprises the following key elements: polarity, power consumption of corresponding polarity, optimal polarity, minimum power consumption, polarity exchange, polarity mutation and polarity conversion;

mapping the individuals to a three-valued FPRM circuit power consumption optimization, expressed as polarity; mapping the fitness of the individual to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the power consumption of corresponding polarity; mapping the individual with the maximum fitness to a three-value FPRM circuit for power consumption optimization, and expressing the power consumption optimization as the optimal polarity; mapping the maximum fitness to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the minimum power consumption; mapping the crossover operation to a three-valued FPRM circuit power consumption optimization, expressed as polarity interchange; mapping the variant operation to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as polarity mutation; mapping the annealing selection operation to a three-valued FPRM circuit power consumption optimization, expressed as a polarity inversion;

setting relevant parameters of the simulated annealing genetic algorithm:

the simulated annealing genetic algorithm needs to set 4 parameters: individual scale w, individual iteration number z, gene mutation probability q, and initial temperature T₀(ii) a Let the individual scale w be 50, the individual iteration number z be 20, the gene mutation probability q be 0.01, and the starting temperature T₀＝100℃；

Obtaining the maximum fitness individual and the maximum fitness by adopting a simulated annealing genetic algorithm, wherein the maximum fitness individual is the power consumption optimal polarity of the three-value FPRM circuit; the maximum fitness is the minimum power consumption of the three-value FPRM circuit.

In this embodiment, the simulated annealing genetic algorithm is a mature algorithm in the prior art.

Example two: a power consumption optimal polarity searching method for a three-value FPRM circuit comprises the following steps:

establishing a power consumption estimation model of a three-value FPRM circuit:

phi-1 represents a three-valued FPRM circuit in the form of a three-valued FPRM logic function:

$f^p(x_{n-1},x_{n-2},\mathrm{...},x_0)=\&CirclePlus;\underset{i=0}{\overset{3^n-1}{\&Sigma;}}{a}_i*\underset{j=0}{\overset{n-1}{\&Pi;}}{\stackrel{\&CenterDot;}{x}}_j^{i_j}---\left(1\right)$

wherein n is a function f^p(x_n-1,x_n-2,…,x₀) Number of input variables, x_n-1,x_n-2,…,x₀Representing function f^p(x_n-1,x_n-2,…,x₀) The number of n input variables of (a),p represents a function f^p(x_n-1,x_n-2,…,x₀) Of (1), the polarity p being represented in ternary form as p_n-1p_n-2…p₀，p_j∈ {0,1,2}, j-0, 1,2, …, n-1, ⊕ denotes a modulo-3 addition, ∑ is the cumulative sign, the sign "×" is the multiplication sign, and the subscript i-0, 1,2, …,3ⁿ1, i is represented in ternary form as i_n-1i_n-2…i₀，a_iIs the FPRM coefficient; a is_i∈ {0,1,2}, pi represents a modulo-3 multiplication operation,the expansion formula is as follows:wherein i_j∈{0,1,2}, $\begin{array}{cc}{\stackrel{\&CenterDot;}{x}}_j=(x_j\&CirclePlus;p_j),& {\stackrel{\&CenterDot;}{x}}_j^0=1,{\stackrel{\&CenterDot;}{x}}_j^1={\stackrel{\&CenterDot;}{x}}_j,{\stackrel{\&CenterDot;}{x}}_j^2={\stackrel{\&CenterDot;}{x}}_j*{\stackrel{\&CenterDot;}{x}}_j\end{array},$ Polarity p and subscript i determine the variablesA representation of (a);

the ternary FPRM logical function under the polarity of-2 p comprises two types of multi-input operations, wherein the two types of multi-input operations are respectively a multi-input modulo-3 addition operation and a multi-input modulo-3 multiplication operation, the ternary FPRM logical function is decomposed into a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations according to a ternary FPRM logical function expansion formula, then each multi-input operation is respectively decomposed into a two-input operation, and the two-input modulo-3 addition operation and the two-input modulo-3 multiplication operation are obtained, and the specific decomposition process is as follows:

taking the 1 st input variable and the 2 nd input variable of the multi-input operation as two input variables of the first second input operation to obtain an output variable of the first second input operation; taking the output variable of the first second input operation and the 3 rd input variable of the multiple input operation as two input variables of the second input operation to obtain the output variable of the second input operation; taking the output variable of the second two-input operation and the 4 th input variable of the multiple-input operation as two input variables of the third two-input operation to obtain the output variable of the third two-input operation; repeating the operation steps until all the input variables of the multi-input operation are used as the input variables of the two-input operation, and completing the decomposition of the multi-input operation;

decomposing the three-valued FPRM logic function under the p polarity to obtain a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations, wherein the multi-input modulo-3 addition operations are also called multi-input modulo-3 addition gates, the multi-input modulo-3 multiplication operations are also called multi-input modulo-3 multiplication gates, the number of the multi-input modulo-3 addition gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as N, and the number of the multi-input modulo-3 multiplication gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as W; decomposing each multi-input modulo-3 addition operation to obtain a plurality of binary input modulo-3 addition operations, decomposing each multi-input modulo-3 multiplication operation to obtain a plurality of binary input modulo-3 multiplication operations, wherein the binary input modulo-3 addition operation is also called a binary input modulo-3 addition gate, and the binary input modulo-3 multiplication operation is also called a binary input modulo-3 multiplication gate; recording the number of the two input module 3 adding gates after the H-th multiple input module 3 adding gates are decomposed as N_HH ═ 1,2, …, N; recording the number of the second input modulo 3 times gate after the o-th multiple input modulo 3 times gate is decomposed as W_o，o＝1,2,…,W；

Firstly, power consumption caused by a two-input modulo-3 adding gate and a two-input modulo-3 multiplying gate obtained after a ternary FPRM logic function under the p polarity is decomposed is taken as power consumption of a ternary FPRM circuit under the p polarity, power consumption caused by the two-input modulo-3 adding gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, power consumption caused by the two-input modulo-3 multiplying gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, the switching activity of the gate circuit is expressed by the output variable probability of an output end of the gate circuit, power consumption caused by the two-input modulo-3 adding gate is expressed by the output variable probability of an output end of the gate circuit, and power consumption caused by the two-input modulo-3 multiplying gate is expressed by;

① -4 calculating the output variable probability of the kth second input modulo-3 adding gate after H multiple input modulo-3 adding gate decomposition according to the formulas (2), (3) and (4), wherein k is 1,2, …, N_H；

P₁(k)_H＝Pk_y11*Pk_y20+Pk_y10*Pk_y21+Pk_y12*Pk_y22(2)

P₂(k)_H＝Pk_y12*Pk_y20+Pk_y11*Pk_y21+Pk_y10*Pk_y22(3)

P₀(k)_H＝1-P₁(k)_H-P₂(k)_H(4)

Calculating the output variable probability of the g-th two-input modulo 3 times gate after the o-th multiple-input modulo 3 times gate decomposition according to the formulas (5), (6) and (7), wherein g is 1,2, …, W_o：

Q₁(g)_o＝Qg_r11*Qg_r21+Qg_r12*Qg_r22(5)

Q₂(g)_o＝Qg_r11*Qg_r22+Qg_r12*Qg_r21(6)

Q₀(g)_o＝1-Q₁(g)_o-Q₂(g)_o(7)

Wherein, P₁(k)_HDenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 1, P₂(k)_HDenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 2, P₀(k)_HDenotes the probability that the k-th two-input modulo-3-add-gate output variable after the H-th multiple-input modulo-3-add-gate decomposition is 0, y1 and y2 denote the two input variables of the two-input modulo-3-add-gate, Pk_y1mRepresents the probability that the input variable y1 is m in the kth two-input modulo 3 adder, m ∈ {0,1,2}, Pk_y2mDenotes the probability that the input variable y2 is m in the k-th two-input modulo-3 adder gate, and when k is 1, Pk is_y1mProbability of m being the 1 st input variable for multiple-input modulo-3 addition, Pk_y2mProbability of m being the 2 nd input variable for multiple input modulo 3 addition, when k>1 time, Pk_y1mFor the k-1 th two-input modulo 3 plus probability of the output variable being m, Pk_y2mProbability that the (k + 1) th input variable of the add gate for multiple input modulo 3 is m;

Q₁(g)_odenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 1, Q₂(g)_oDenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 2, Q₀(g)_oDenotes the probability that the output variable of the g-th multi-input modulo 3 gate after the o-th multi-input modulo 3 gate decomposition is 0, r1 and r2 denote the two input variables of the two-input modulo 3 gate, Qg_r1mRepresents the probability that the input variable r1 is m in the g-th two-input modulo 3 multiplication gate, Qg_r2mRepresents the probability that the g-th two-input modulo 3 multiplied by the input variable r2 in the gate is m; when g is 1, Qg_r1mProbability of the 1 st input variable being m, Qg, for a multiple-input modulo-3 multiplication_r2mProbability of m being the 2 nd input variable of the multiple input modulo 3 multiplication, when g>At 1 hour, Qg_r1mFor the g-1 st probability that the two-input modulo 3 is the output variable of m, Qg_r2mThe probability that the g +1 th input variable of the multiple input modulo 3 by gate is m;

input variable x_jThe probabilities of 1 and 2 are the pairs of probabilities generated by random functions (P1, P2), P0 ═ 1-P1-P2; p0, P1 and P2 are each a value between 0 and 1, P0 denotes the probability that the input variable is 0, P1 denotes the probability that the input variable is 1, and P2 denotes the probability that the input variable is 2;

firstly, calculating the power consumption of the three-value FPRM circuit according to the output variable probability of the two-input modulo 3 addition gate and the output variable probability of the two-input modulo 3 multiplication gate, and expressing a power consumption estimation model of the three-value FPRM circuit as follows:

$E_{swd}=2\left(\underset{H=1}{\overset{N}{\&Sigma;}}\left(\underset{k=1}{\overset{N_H}{\&Sigma;}}\left(P_1{\left(k\right)}_H+P_2{\left(k\right)}_H\right)\right)+\underset{o=1}{\overset{W}{\&Sigma;}}\left(\underset{g=1}{\overset{W_o}{\&Sigma;}}\left(Q_1{\left(g\right)}_o+Q_2{\left(g\right)}_o\right)\right)\right)---\left(8\right)$

wherein E is_swdThe power consumption of the three-value FPRM circuit under the p polarity is represented, N is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed, and W is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed;

setting a fitness function for calculating individual fitness in the simulated annealing genetic algorithm:

according to the power consumption estimation model, a fitness function for calculating individual fitness in the simulated annealing genetic algorithm is set: in the simulated annealing genetic algorithm, the higher the fitness is, the stronger the adaptability of an individual is, but the optimal polarity of power consumption requires the lower the power consumption is, the better the fitness is, so that in order to facilitate the combination of the two, the inverse of the power consumption is adopted to represent the fitness, and the fitness function is obtained as follows:

fitness＝α/E_swd

wherein, the symbol "/" represents a division operation symbol, and the fitness represents the fitness of an individual; e_swdα is an amplification factor, and the value is a natural number which is greater than or equal to 1000;

establishing a corresponding relation between a three-value FPRM circuit and a simulated annealing genetic algorithm:

the simulated annealing genetic algorithm comprises the following key elements: individual, individual fitness, individual with the maximum fitness, cross operation, mutation operation and annealing selection operation;

the power consumption optimization of the three-value FPRM circuit comprises the following key elements: polarity, power consumption of corresponding polarity, optimal polarity, minimum power consumption, polarity exchange, polarity mutation and polarity conversion;

mapping the individuals to a three-valued FPRM circuit power consumption optimization, expressed as polarity; mapping the fitness of the individual to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the power consumption of corresponding polarity; mapping the individual with the maximum fitness to a three-value FPRM circuit for power consumption optimization, and expressing the power consumption optimization as the optimal polarity; mapping the maximum fitness to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the minimum power consumption; mapping the crossover operation to a three-valued FPRM circuit power consumption optimization, expressed as polarity interchange; mapping the variant operation to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as polarity mutation; mapping the annealing selection operation to a three-valued FPRM circuit power consumption optimization, expressed as a polarity inversion;

setting relevant parameters of the simulated annealing genetic algorithm:

the simulated annealing genetic algorithm needs to set 4 parameters: individual scale w, individual iteration number z, gene mutation probability q, and initial temperature T₀(ii) a Let the individual scale w be 50, the individual iteration number z be 20, the gene mutation probability q be 0.01, and the starting temperature T₀＝100℃；

Obtaining the maximum fitness individual and the maximum fitness by adopting a simulated annealing genetic algorithm, wherein the maximum fitness individual is the power consumption optimal polarity of the three-value FPRM circuit; the maximum fitness is the minimum power consumption of the three-value FPRM circuit.

In this embodiment, the specific process of obtaining the individual with the maximum fitness and the maximum fitness by using the simulated annealing genetic algorithm in the fifth step is as follows:

fifthly, -1, generating w individuals represented by an n-bit ternary system by using a random function rand (), and respectively marking the w individuals as P1, P2, … and Pw;

fifthly-2, calculating the fitness of the v individual Pv through a fitness function, wherein v is 1,2, 3, …, w, and obtaining the fitness of individuals P1, P2, … and Pw;

fifthly-3, comparing the fitness of individuals P1, P2, … and Pw, screening the individual with the maximum fitness as the individual with the maximum fitness, and recording the individual with the maximum fitness and the maximum fitness;

fifthly-4, the individuals P1, P2, … and Pw are subjected to cross operation to generate the individuals F1, F2, … and Fw: if w is an even number, performing crossing operation on P1 and P2, P3 and P4, …, and Pw-1 and Pw in pairs respectively; if w is an odd number, carrying out cross operation on P1 and P2, P3 and P4, …, Pw-2 and Pw-1 in pairs respectively, wherein Pw does not participate in the cross operation, and Fw directly inherits Pw; performing cross operation on two individuals Pe and Pu to generate individuals Fe and Fu, wherein the specific process comprises the following steps: assigning Pe to fe and Pu to fu, randomly generating an n-bit binary code, marking the n-bit binary code as A, updating fe and fu according to the binary code A, and keeping the h bit of fe and fu unchanged when the h bit of the binary code A is 1; when the h bit of the binary code a is 0, the h bit of Fe inherits the h bit of Fu, the h bit of Fu inherits the h bit of Fe, h is 1,2, 3, …, n, Fe after the completion of the crossover operation is recorded as Fe, and Fu after the completion of the crossover operation is recorded as Fu; wherein u is e +1, when w is an even number, e is 1, 3, 5, …, w-1; u-2, 4, 6, …, w; when w is an odd number, e is 1, 3, 5, …, w-2; u-2, 4, 6, …, w-1;

fifthly, calculating the fitness of the v individual Fv through a fitness function to obtain the fitness of the individuals F1, F2, … and Fw;

fifthly-6, comparing the fitness of the individuals F1, F2, … and Fw with the fitness of the individual with the maximum fitness at present, and updating the individual with the maximum fitness and the maximum fitness;

7, carrying out mutation operation on individuals F1, F2, … and Fw: generating a value between 0 and 1 for each bit of the Fv by using a random function rand (), if the value is less than the gene mutation probability q, the bit corresponding to the value is the mutation bit of the Fv, and the mutation bit of the Fv is mutated, wherein the mutation rule is '0 → 1, 1 → 2, 2 → 0';

fifthly-8, treating the individuals F1, F2, … and Fw according to the steps of fifthly-5 to fifthly-6 to obtain the updated individuals with the maximum fitness and the maximum fitness;

fifthly-9, sorting individuals P1, P2, … and Pw according to the size of the fitness value, and sorting individuals F1, F2, … and Fw according to the size of the fitness value; selecting 2w/3 individuals with optimal fitness values from individuals P1, P2, … and Pw and individuals F1, F2, … and Fw respectively to form a new group of individuals, wherein the new individuals comprise 4w/3 individuals;

-10 multiple rounds of annealing selection on a new group of individuals: in each round of annealing selection, firstly generating an annealing temperature according to a formula (9), sequentially calculating the selection probability P (c) of each individual according to a formula (10) for the annealing temperature, and simultaneously generating a screening probability t by using a random function rand (), wherein 0< t < 1; when the individual selection probability is greater than the screening probability, the individual is selected in the round of annealing selection, the selected individual does not participate in the next round of annealing selection, other unselected individuals enter the next round of annealing selection, and the annealing selection is finished until w individual updating individuals P1, P2, … and Pw are screened;

T_l＝1/ln(l/T₀+1)(9)

$P\left(c\right)=e^{f\left(c\right)/T_l}/\underset{d=0}{\overset{4w/3}{\&Sigma;}}{e}^{f\left(d\right)/T_l}---\left(10\right)$

wherein, T_lDenotes the annealing temperature of the first round, l ═ 1,2, …; when the first round of annealing selection is carried out, l is 1, when the second round of annealing selection is carried out, l is 2, and the rest can be analogized; ln represents a logarithmic operation; t is₀Represents the initial temperature; p (c) represents the probability of the individual c; (f) (c) indicates the fitness value of the c-th individual of the new individuals; c is 1,2, 3, …, 4 w/3; (d) indicates the fitness value of the d-th individual of the new individuals; d is 1,2, 3, …, 4 w/3;

fifthly-11, processing the individuals P1, P2, … and Pw updated in the step fifthly-10 according to the step fifthly-2 to the step fifthly-3 to obtain the individual with the maximum fitness and the maximum fitness;

fifthly-12, repeating the steps of fifthly-4 to fifthly-11 until the individual iteration times z are met, and finishing the algorithm to obtain the individual with the maximum fitness and the maximum fitness;

fifthly-13, outputting the maximum fitness individual and the maximum fitness obtained in the last time, wherein the maximum fitness individual is the optimal polarity of the three-value FPRM circuit; the maximum fitness is the minimum power consumption of the three-value FPRM circuit.

The method for searching the optimal power consumption polarity is realized by C language through VC6.0 compiling under the operating environment of a Windows764 bit operating system, Intel (R) core (TM) i3-2130CPU3.40GHZ and 4GRAM, and randomly adopts 13 MCNCBenchmark circuits for simulation verification to compare the optimal power consumption polarity searched by the method with the 0 polarity. To calculate the switching activity of a ternary FPRM circuit, 15 sets of input signal probabilities were randomly generated: (P1, P2) { (0.21,0.53), (0.49,0.30), (0.33,0.24), (0.68,0.13), (0.15,0.26), (0.57,0.22), (0.18,0.51), (0.71,0.24), (0.08,0.35), (0.57,0.32), (0.46,0.28), (0.17,0.05), (0.32,0.43), (0.14,0.72), (0.25,0.61) }.

The results of the optimal polarity search using the power consumption optimal polarity search method of the present invention are shown in table 1. In the table, a column 1 indicates a circuit name, and a column 2 indicates the number of input/output variables; the row 3, the row 4 and the row 5 respectively represent the number of gates added by the second input module 3 under the polarity of 0, the number of gates multiplied by the second input module 3 and the power consumption of the circuit in sequence; the column 6, the column 7, the column 8 and the column 9 respectively show the second input modulo 3 plus gate number, the second input modulo 3 multiplying gate number and the power consumption of the three-valued FPRM circuit under the optimum polarity and the optimum polarity searched by the method of the invention.

TABLE 1 ternary FPRM circuits optimal polarity search results

The optimal polarity is shown in table 2 as the percentage savings in modulo 3 plus gate number, modulo 3 times gate number, and power consumption compared to 0 polarity. The number of gates modulo 3 plus, the number of gates modulo 3 times, and the percentage of power savings are defined as follows:

${\mathrm{Save}}_{Mod3-A}\%=\frac{Mod3-A_0-Mod3-A_{SAGA}}{Mod3-A_0}\&times;100\%---\left(11\right)$

${\mathrm{Save}}_{Mod3-M}\%=\frac{Mod3-M_0-Mod3-M_{SAGA}}{Mod3-M_0}\&times;100\%---\left(12\right)$

${\mathrm{Save}}_{Power}\%=\frac{{\mathrm{Power}}_0-{\mathrm{Power}}_{SAGA}}{{\mathrm{Power}}_0}\&times;100\%---\left(13\right)$

wherein, Save_Mod3-A、Save_Mod3-MAnd Save_PowerSequentially and respectively representing the modulo 3 plus gate number, the modulo 3 by gate number and the power consumption saving; mod3-A₀、Mod3-M₀And Power₀Sequentially and respectively representing the gate adding quantity of the lower die 3 with the polarity of 0, the gate multiplying quantity of the die 3 and the power consumption; mod3-A_SAGA、Mod3-M_SAGAAnd SA_SAGASequentially and respectively representing the gate adding quantity of the lower die 3 with the optimal polarity, the gate multiplying quantity of the die 3 and the power consumption size searched by the method. Using the method of the present invention, the gate count and the power savings percentage of the ternary FPRM circuit are shown in Table 2.

TABLE 2 three-valued FPRM circuit gate count and percentage power savings

The analysis data shows that the optimal power consumption polarity searched by the method has obvious optimization effect compared with the 0 polarity, wherein the clpl circuit saves 80.00 percent, 66.67 percent and 89.78 percent of the modulo 3 gate adding quantity, the modulo 3 gate multiplying quantity and the power consumption respectively, and the 13 test circuits save 57.64 percent, 46.25 percent and 73.98 percent of the modulo 3 gate adding quantity, the modulo 3 gate multiplying quantity and the power consumption averagely.

Claims (2)

1. A power consumption optimal polarity searching method for a three-value FPRM circuit is characterized by comprising the following steps:

establishing a power consumption estimation model of a three-value FPRM circuit:

phi-1 represents a three-valued FPRM circuit in the form of a three-valued FPRM logic function:

wherein n is a function f^p(x_n-1,x_n-2,…,x₀) Number of input variables, x_n-1,x_n-2,…,x₀Representing function f^p(x_n-1,x_n-2,…,x₀) N input variables of (a) and p represents a function f^p(x_n-1,x_n-2,…,x₀) Of (1), the polarity p being represented in ternary form as p_n-1p_n-2…p₀，p_j∈{0,1,2}，j＝0,1,2,…,n-1，Indicating a modulo-3 addition, ∑ an accumulated sign, a sign "×" a multiplying sign, a subscript i 0,1,2, …,3ⁿ1, i is represented in ternary form as i_n-1i_n-2…i₀，a_iIs the FPRM coefficient; a is_i∈ {0,1,2}, pi represents a modulo-3 multiplication operation,the expansion formula is as follows:wherein i_j∈{0，1，2}， Polarity p and subscript i determine the variablesA representation of (a);

the ternary FPRM logical function under the polarity of-2 p comprises two types of multi-input operations, wherein the two types of multi-input operations are respectively a multi-input modulo-3 addition operation and a multi-input modulo-3 multiplication operation, the ternary FPRM logical function is decomposed into a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations according to a ternary FPRM logical function expansion formula, then each multi-input operation is respectively decomposed into a two-input operation, and the two-input modulo-3 addition operation and the two-input modulo-3 multiplication operation are obtained, and the specific decomposition process is as follows:

taking the 1 st input variable and the 2 nd input variable of the multi-input operation as two input variables of the first second input operation to obtain an output variable of the first second input operation; taking the output variable of the first second input operation and the 3 rd input variable of the multiple input operation as two input variables of the second input operation to obtain the output variable of the second input operation; taking the output variable of the second two-input operation and the 4 th input variable of the multiple-input operation as two input variables of the third two-input operation to obtain the output variable of the third two-input operation; repeating the operation steps until all the input variables of the multi-input operation are used as the input variables of the two-input operation, and completing the decomposition of the multi-input operation;

decomposing the three-valued FPRM logic function under the p polarity to obtain a plurality of multi-input modulo-3 addition operations and a plurality of multi-input modulo-3 multiplication operations, wherein the multi-input modulo-3 addition operations are also called multi-input modulo-3 addition gates, the multi-input modulo-3 multiplication operations are also called multi-input modulo-3 multiplication gates, the number of the multi-input modulo-3 addition gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as N, and the number of the multi-input modulo-3 multiplication gates decomposed by the three-valued FPRM logic function under the p polarity is recorded as W; decomposing each multi-input modulo-3 addition operation to obtain a plurality of binary input modulo-3 addition operations, decomposing each multi-input modulo-3 multiplication operation to obtain a plurality of binary input modulo-3 multiplication operations, wherein the binary input modulo-3 addition operation is also called a binary input modulo-3 addition gate, and the binary input modulo-3 multiplication operation is also called a binary input modulo-3 multiplication gate; recording the number of the two input module 3 adding gates after the H-th multiple input module 3 adding gates are decomposed as N_HH ═ 1,2, …, N; recording the number of the second input modulo 3 times gate after the o-th multiple input modulo 3 times gate is decomposed as W_o，o＝1,2,…,W；

Firstly, power consumption caused by a two-input modulo-3 adding gate and a two-input modulo-3 multiplying gate obtained after a ternary FPRM logic function under the p polarity is decomposed is taken as power consumption of a ternary FPRM circuit under the p polarity, power consumption caused by the two-input modulo-3 adding gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, power consumption caused by the two-input modulo-3 multiplying gate is expressed by the switching activity of the binary input modulo-3 multiplying gate, the switching activity of the gate circuit is expressed by the output variable probability of an output end of the gate circuit, power consumption caused by the two-input modulo-3 adding gate is expressed by the output variable probability of an output end of the gate circuit, and power consumption caused by the two-input modulo-3 multiplying gate is expressed by;

① -4 calculating the output variable probability of the kth second input modulo-3 adding gate after H multiple input modulo-3 adding gate decomposition according to the formulas (2), (3) and (4), wherein k is 1,2, …, N_H；

P₁(k)_H＝Pk_y11*Pk_y20+Pk_y10*Pk_y21+Pk_y12*Pk_y22(2)

P₂(k)_H＝Pk_y12*Pk_y20+Pk_y11*Pk_y21+Pk_y10*Pk_y22(3)

P₀(k)_H＝1-P₁(k)_H-P₂(k)_H(4)

Calculating the output variable probability of the g-th two-input modulo 3 times gate after the o-th multiple-input modulo 3 times gate decomposition according to the formulas (5), (6) and (7), wherein g is 1,2, …, W_o：

Q₁(g)_o＝Qg_r11*Qg_r21+Qg_r12*Qg_r22(5)

Q₂(g)_o＝Qg_r11*Qg_r22+Qg_r12*Qg_r21(6)

Q₀(g)_o＝1-Q₁(g)_o-Q₂(g)_o(7)

Wherein, P₁(k)_HDenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 1, P₂(k)_HDenotes the probability that the output variable of the kth second input modulo 3 plus gate after the H multiple input modulo 3 plus gate decomposition is 2, P₀(k)_HDenotes the probability that the k-th two-input modulo-3-add-gate output variable after the H-th multiple-input modulo-3-add-gate decomposition is 0, y1 and y2 denote the two input variables of the two-input modulo-3-add-gate, Pk_y1mDenotes the probability of m being the input variable y1 in the kth two-input modulo 3 adder, m ∈ {0,1,2}, Pk_y2mDenotes the probability that the input variable y2 is m in the k-th two-input modulo-3 adder gate, and when k is 1, Pk is_y1mProbability of m being the 1 st input variable for multiple-input modulo-3 addition, Pk_y2mProbability of m being the 2 nd input variable for multiple input modulo 3 addition, when k>1 time, Pk_y1mFor the k-1 th two-input modulo-3 plus-gate output variable, the probability of m, Pk_y2mProbability that the (k + 1) th input variable of the add gate for multiple input modulo 3 is m;

Q₁(g)_odenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 1, Q₂(g)_oDenotes the probability that the output variable of the g-th second input modulo 3 by gate after the o-th multiple input modulo 3 by gate decomposition is 2, Q₀(g)_oDenotes the probability that the output variable of the g-th multi-input modulo 3 gate after the o-th multi-input modulo 3 gate decomposition is 0, r1 and r2 denote the two input variables of the two-input modulo 3 gate, Qg_r1mRepresents the probability that the input variable r1 is m in the g-th two-input modulo 3 multiplication gate, Qg_r2mRepresents the probability that the g-th two-input modulo 3 multiplied by the input variable r2 in the gate is m; when g is 1, Qg_r1mProbability of the 1 st input variable being m, Qg, for a multiple-input modulo-3 multiplication_r2mProbability of m being the 2 nd input variable of the multiple input modulo 3 multiplication, when g>At 1 hour, Qg_r1mFor the g-1 st probability that the two-input modulo 3 is the output variable of m, Qg_r2mThe probability that the g +1 th input variable of the multiple input modulo 3 by gate is m;

input variable x_jThe probabilities of 1 and 2 are the pairs of probabilities generated by random functions (P1, P2), P0 ═ 1-P1-P2; p0, P1 and P2 are each a value between 0 and 1, P0 denotes the probability that the input variable is 0, P1 denotes the probability that the input variable is 1, and P2 denotes the probability that the input variable is 2;

firstly, calculating the power consumption of the three-value FPRM circuit according to the output variable probability of the two-input modulo 3 addition gate and the output variable probability of the two-input modulo 3 multiplication gate, and expressing a power consumption estimation model of the three-value FPRM circuit as follows:

wherein E is_swdThe power consumption of the three-value FPRM circuit under the p polarity is represented, N is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed, and W is the number of the multi-input modulo-3 addition gates after the three-value FPRM logic function under the p polarity is decomposed;

setting a fitness function for calculating individual fitness in the simulated annealing genetic algorithm:

according to the power consumption estimation model, a fitness function for calculating individual fitness in the simulated annealing genetic algorithm is set: in the simulated annealing genetic algorithm, the higher the fitness is, the stronger the adaptability of an individual is, but the optimal polarity of power consumption requires the lower the power consumption is, the better the fitness is, so that in order to facilitate the combination of the two, the inverse of the power consumption is adopted to represent the fitness, and the fitness function is obtained as follows:

fitness＝α/E_swd

wherein, the symbol "/" represents a division operation symbol, and the fitness represents the fitness of an individual; e_swdα is an amplification factor, and the value is a natural number which is greater than or equal to 1000;

establishing a corresponding relation between a three-value FPRM circuit and a simulated annealing genetic algorithm:

the simulated annealing genetic algorithm comprises the following key elements: individual, individual fitness, individual with the maximum fitness, cross operation, mutation operation and annealing selection operation;

the power consumption optimization of the three-value FPRM circuit comprises the following key elements: polarity, power consumption of corresponding polarity, optimal polarity, minimum power consumption, polarity exchange, polarity mutation and polarity conversion;

mapping the individuals to a three-valued FPRM circuit power consumption optimization, expressed as polarity; mapping the fitness of the individual to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the power consumption of corresponding polarity; mapping the individual with the maximum fitness to a three-value FPRM circuit for power consumption optimization, and expressing the power consumption optimization as the optimal polarity; mapping the maximum fitness to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as the minimum power consumption; mapping the crossover operation to a three-valued FPRM circuit power consumption optimization, expressed as polarity interchange; mapping the variant operation to the power consumption optimization of the three-value FPRM circuit, and expressing the power consumption optimization as polarity mutation; mapping the annealing selection operation to a three-valued FPRM circuit power consumption optimization, expressed as a polarity inversion;

setting relevant parameters of the simulated annealing genetic algorithm:

the simulated annealing genetic algorithm needs to set 4 parameters: individual scale w, individual iteration number z, gene mutation probability q, and initial temperature T₀(ii) a Let the individual scale w be 50, the individual iteration number z be 20, the gene mutation probability q be 0.01, and the starting temperature T₀＝100℃；

Obtaining the maximum fitness individual and the maximum fitness by adopting a simulated annealing genetic algorithm, wherein the maximum fitness individual is the power consumption optimal polarity of the three-value FPRM circuit; the maximum fitness is the minimum power consumption of the three-value FPRM circuit.

2. The method as claimed in claim 1, wherein the step (v) of obtaining the individual with the maximum fitness and the maximum fitness by using the simulated annealing genetic algorithm comprises:

fifthly, -1, generating w individuals represented by an n-bit ternary system by using a random function rand (), and respectively marking the w individuals as P1, P2, … and Pw;

fifthly-2, calculating the fitness of the v individual Pv through a fitness function, wherein v is 1,2, 3, …, w, and obtaining the fitness of individuals P1, P2, … and Pw;

fifthly-3, comparing the fitness of individuals P1, P2, … and Pw, screening the individual with the maximum fitness as the individual with the maximum fitness, and recording the individual with the maximum fitness and the maximum fitness;

fifthly-4, the individuals P1, P2, … and Pw are subjected to cross operation to generate the individuals F1, F2, … and Fw: if w is an even number, performing crossing operation on P1 and P2, P3 and P4, …, and Pw-1 and Pw in pairs respectively; if w is an odd number, carrying out cross operation on P1 and P2, P3 and P4, …, Pw-2 and Pw-1 in pairs respectively, wherein Pw does not participate in the cross operation, and Fw directly inherits Pw; performing cross operation on two individuals Pe and Pu to generate individuals Fe and Fu, wherein the specific process comprises the following steps: assigning Pe to fe and Pu to fu, randomly generating an n-bit binary code, marking the n-bit binary code as A, updating fe and fu according to the binary code A, and keeping the h bit of fe and fu unchanged when the h bit of the binary code A is 1; when the h bit of the binary code a is 0, the h bit of Fe inherits the h bit of Fu, the h bit of Fu inherits the h bit of Fe, h is 1,2, 3, …, n, Fe after the completion of the crossover operation is recorded as Fe, and Fu after the completion of the crossover operation is recorded as Fu; wherein u is e +1, when w is an even number, e is 1, 3, 5, …, w-1; u-2, 4, 6, …, w; when w is an odd number, e is 1, 3, 5, …, w-2; u-2, 4, 6, …, w-1;

fifthly, calculating the fitness of the v individual Fv through a fitness function to obtain the fitness of the individuals F1, F2, … and Fw;

fifthly-6, comparing the fitness of the individuals F1, F2, … and Fw with the fitness of the individual with the maximum fitness at present, and updating the individual with the maximum fitness and the maximum fitness;

7, carrying out mutation operation on individuals F1, F2, … and Fw: generating a value between 0 and 1 for each bit of the Fv by using a random function rand (), if the value is less than the gene mutation probability q, the bit corresponding to the value is the mutation bit of the Fv, and the mutation bit of the Fv is mutated, wherein the mutation rule is '0 → 1, 1 → 2, 2 → 0';

fifthly-8, treating the individuals F1, F2, … and Fw according to the steps of fifthly-5 to fifthly-6 to obtain the updated individuals with the maximum fitness and the maximum fitness;

fifthly-9, sorting individuals P1, P2, … and Pw according to the size of the fitness value, and sorting individuals F1, F2, … and Fw according to the size of the fitness value; selecting 2w/3 individuals with optimal fitness values from individuals P1, P2, … and Pw and individuals F1, F2, … and Fw respectively to form a new group of individuals, wherein the new individuals comprise 4w/3 individuals;

-10 multiple rounds of annealing selection on a new group of individuals: in each round of annealing selection, firstly generating an annealing temperature according to a formula (9), sequentially calculating the selection probability P (c) of each individual according to a formula (10) for the annealing temperature, and simultaneously generating a screening probability t by using a random function rand (), wherein 0< t < 1; when the individual selection probability is greater than the screening probability, the individual is selected in the round of annealing selection, the selected individual does not participate in the next round of annealing selection, other unselected individuals enter the next round of annealing selection, and the annealing selection is finished until w individual updating individuals P1, P2, … and Pw are screened;

T_l＝1/ln(l/T₀+1)(9)

wherein, T_lDenotes the annealing temperature of the first round, l ═ 1,2, …; when the first round of annealing selection is carried out, l is 1, when the second round of annealing selection is carried out, l is 2, and the rest can be analogized; ln represents a logarithmic operation; t is₀Represents the initial temperature; p (c) represents the probability of the individual c; (f) (c) indicates the fitness value of the c-th individual of the new individuals; c is 1,2, 3, …, 4 w/3; (d) indicates the fitness value of the d-th individual of the new individuals; d is 1,2, 3, …, 4 w/3;

fifthly-11, processing the individuals P1, P2, … and Pw updated in the step fifthly-10 according to the step fifthly-2 to the step fifthly-3 to obtain the individual with the maximum fitness and the maximum fitness;

fifthly-12, repeating the steps of fifthly-4 to fifthly-11 until the individual iteration times z are met, and finishing the algorithm to obtain the individual with the maximum fitness and the maximum fitness;

fifthly-13, outputting the maximum fitness individual and the maximum fitness obtained in the last time, wherein the maximum fitness individual is the optimal polarity of the three-value FPRM circuit; the maximum fitness is the minimum power consumption of the three-value FPRM circuit.